阅读说明：本技术 一种卫星测控通信副载波同步方法 (Satellite measurement and control communication subcarrier synchronization method ) 是由 张士伟 邢斯瑞 沈晨阳 于 2021-09-10 设计创作，主要内容包括：本发明涉及一种卫星测控通信副载波同步方法,该方法通过FFT和PLL1的联合工作实现载波的同步和跟踪,再利用PLL2对遥控副载波进行跟踪,实现副载波同步,其中PLL2通过以下步骤设计得到：计算遥控副载波的频偏和频率变化率,并根据频偏选择快捕带和快捕时间的设计值；设计PLL2的整个环路,包括比较器及鉴相器、环路滤波器和DDS；对整个环路的稳定性、跟踪精度分别进行分析；对整个环路的快捕带和快捕时间进行分析,比较实际仿真结果和理论结果；对整个环路的捕获带和捕获时间进行分析,判断频率牵引时间是否满足使用要求；对整个环路的同步带和同步时间进行分析,得到最终的PLL2。本发明具有跟踪相位准确、速度快等优点。(The invention relates to a satellite measurement and control communication subcarrier synchronization method, which realizes carrier synchronization and tracking through the joint work of FFT and PLL1, and then realizes subcarrier synchronization by tracking a remote control subcarrier through PLL2, wherein the PLL2 is designed through the following steps: calculating the frequency deviation and the frequency change rate of the remote control subcarrier, and selecting the design values of the fast capture zone and the fast capture time according to the frequency deviation; designing the whole loop of the PLL2, including a comparator and phase detector, a loop filter and a DDS; respectively analyzing the stability and the tracking precision of the whole loop; analyzing the fast capture zone and the fast capture time of the whole loop, and comparing the actual simulation result with the theoretical result; analyzing the capture zone and the capture time of the whole loop, and judging whether the frequency traction time meets the use requirement; the timing belt and timing time of the entire loop are analyzed to obtain the final PLL 2. The invention has the advantages of accurate tracking phase, high speed and the like.)

1. A satellite measurement and control communication subcarrier synchronization method is characterized in that carrier synchronization and tracking are achieved through the combined work of FFT and PLL1, remote control subcarriers are obtained, then PLL2 is used for tracking the remote control subcarriers, subcarrier synchronization is achieved, and the PLL2 is designed through the following steps:

the method comprises the following steps: calculating the frequency deviation and the frequency change rate of the remote control subcarrier, and selecting the design values of a fast capture zone and fast capture time according to the frequency deviation;

step two: designing the whole loop of the PLL2, wherein the whole loop comprises a comparator, a phase discriminator, a loop filter and a DDS, determining a Z-domain transfer function and a phase gain of the DDS, and determining a coefficient of the loop filter;

step three: analyzing the stability of the whole loop, calculating a stability margin, and adjusting parameters according to the stability margin to enable the stability margin to meet the use requirement;

step four: analyzing the tracking precision of the whole loop to obtain the density ratio of the signal to noise spectrum of the input signal under the requirement of different phase precision standard deviations;

step five: analyzing the fast capture zone and the fast capture time of the whole loop, and comparing the actual simulation result with the theoretical result;

step six: analyzing the capture zone and the capture time of the whole loop, and judging whether the frequency traction time meets the use requirement;

step seven: and analyzing the synchronous belt and the synchronous time of the whole loop, judging whether the maximum synchronous scanning rate of the ideal secondary loop is greater than the frequency change rate, and if so, obtaining the final PLL 2.

2. The satellite measurement and control communication subcarrier synchronization method according to claim 1, wherein the DDS comprises a phase accumulator, a lookup table unit and a lookup table address truncating unit;

the input of the phase accumulator comprises a frequency control word and an error signal, the frequency control word and the error signal are accumulated under the control of a working clock, an accumulated result is sent to the address truncation unit of the lookup table after passing through a modulus taking and phase register, and the number of bits of the phase accumulator is 32;

the lookup table address truncation unit is used for truncating the low order of the 32-bit address of the phase accumulator to generate a 12-bit lookup table address, and the lookup table address is used for addressing the lookup table to output two paths of orthogonal local signals;

the lookup table unit stores sine signals and cosine signals of one period, and samples 2 of one period¹²And a point outputting a sine output signal and a cosine output signal.

3. The satellite measurement and control communication subcarrier synchronization method according to claim 2, wherein the working clock is f_clk3.5MHz, the frequency control word is FCW f_subc×2^N/f_clk＝8000×2³²9817068, 32 1/f are selected for the loop closed-loop period_clkN is the number of bits in the phase accumulator, 32, the Z-domain transfer function of DDS isH(z)＝4.61×10^-8/(z-1), the phase gain of DDS is K_DDS＝4.61×10^-8。

4. The method as claimed in claim 1, wherein in the whole loop of the PLL2, the ramp signal is the phase of the input signal, the comparator compares the phase of the input signal with the phase of the local recovery signal, and then inputs the phase difference into the phase detector, the output of the phase detector is filtered by the loop filter and then outputs to the DDS, the DDS adjusts the phase of its output signal by the input error signal to form a closed-loop feedback, and the Z-domain transfer function of the whole PLL2 phase-locked loop is as follows:

wherein, c₁And c₂Is a loop filter coefficient, and xi is damping ratio, omega_nIs the undamped natural angular frequency, K, of the loop_DDSAnd T is the closed loop period of the loop.

5. The satellite measurement and control communication subcarrier synchronization method according to claim 4, wherein a design value of the fast capture band is ± 50Hz, a damping ratio is ξ ═ 0.707, and a loop undamped natural oscillation angular frequency corresponding to the ± 50Hz fast capture band is ω_n222.18rad/s, loop filter coefficient c₁＝613567，c₂＝88。

Technical Field

The invention belongs to the technical field of satellite wireless communication, and particularly relates to a satellite measurement and control communication subcarrier synchronization method.

Background

The unified S-band (USB) measurement and control is a measurement and control mode commonly used by the current satellite, and the USB measurement and control belongs to satellite wireless communication. For a satellite measurement and control receiver, a carrier synchronization and tracking technology is key to correctly and stably realize the reception of a remote control instruction, and if the synchronization performance is poor, an error code causes the instruction to be an invalid instruction, so that the measurement and control effect of a satellite is influenced.

The traditional carrier synchronization is based on a mode of a frequency locking ring and a phase locking ring, but in actual satellite engineering measurement and control application, because the communication distance is very long, the received signal is weak, the signal to noise ratio is poor, the frequency locking ring has large oscillation when tracking the carrier frequency, and when the phase locking ring is rotated after the frequency locking ring is stably tracked, the frequency difference can not be guaranteed to be positioned in a capture band of the phase locking ring, so that the phase locking ring can not be locked, the carrier capture needs to be carried out again, the capture time is prolonged, the capture probability is reduced, and the satellite measurement and control communication application is not suitable.

Disclosure of Invention

The invention provides a satellite measurement and control communication subcarrier synchronization method, which aims to solve the problems of the traditional carrier synchronization method in the prior art, realize the rapid acquisition and tracking of instruction signals and the correct and stable receiving of measurement and control instructions aiming at the characteristics of large Doppler and high dynamic of wireless signals caused by the high-speed motion of low-earth orbit satellites and the like.

In order to achieve the purpose, the invention adopts the following technical scheme:

a satellite measurement and control communication subcarrier synchronization method is characterized in that carrier synchronization and tracking are achieved through the joint work of FFT and PLL1, remote control subcarriers are obtained, then PLL2 is used for tracking the remote control subcarriers, subcarrier synchronization is achieved, and the PLL2 is designed through the following steps:

the method comprises the following steps: calculating the frequency deviation and the frequency change rate of the remote control subcarrier, and selecting the design values of a fast capture zone and fast capture time according to the frequency deviation;

step two: designing the whole loop of the PLL2, wherein the whole loop comprises a comparator, a phase discriminator, a loop filter and a DDS, determining a Z-domain transfer function and a phase gain of the DDS, and determining a coefficient of the loop filter;

step three: analyzing the stability of the whole loop, calculating a stability margin, and adjusting parameters according to the stability margin to enable the stability margin to meet the use requirement;

step four: analyzing the tracking precision of the whole loop to obtain the density ratio of the signal to noise spectrum of the input signal under the requirement of different phase precision standard deviations;

step five: analyzing the fast capture zone and the fast capture time of the whole loop, and comparing the actual simulation result with the theoretical result;

step six: analyzing the capture zone and the capture time of the whole loop, and judging whether the frequency traction time meets the use requirement;

step seven: and analyzing the synchronous belt and the synchronous time of the whole loop, judging whether the maximum synchronous scanning rate of the ideal secondary loop is greater than the frequency change rate, and if so, obtaining the final PLL 2.

The satellite measurement and control communication subcarrier synchronization method provided by the invention adopts an architecture of FFT + PLL1+ PLL2, wherein the FFT mainly realizes coarse capture of a carrier, the PLL1 realizes fine tracking of a carrier phase on the basis of the FFT, fast capture tracking of a large Doppler range and high dynamic signal is realized through mutual matching of the FFT and the PLL1, and the PLL2 mainly completes tracking of a subcarrier. The invention has the following advantages:

(1) the large Doppler range and high dynamic signal can be captured and tracked;

(2) the method has the characteristics of high tracking precision, good stability and the like;

(3) the invention adopts the IIR filter, and can accelerate the locking time of the signal.

Drawings

FIG. 1 is a flow chart of a satellite measurement and control communication subcarrier synchronization method according to the present invention;

FIG. 2 is a phase model diagram of PLL 2;

FIG. 3 is a DDS schematic block diagram;

FIG. 4 is an open-loop Bode diagram of a Z-domain system;

FIG. 5 is a graph showing the relationship between loop bandwidth, input signal to noise spectral density ratio, and steady state phase error standard deviation;

FIG. 6 is a simulation of a rapid trap;

FIG. 7 is an error response curve at an output frequency difference of 50 Hz;

FIG. 8 is a graph of frequency pulling time comparison between a theoretical model, a phase model, and a frequency model;

FIG. 9 is a graph of frequency pulling time at different delay stages;

fig. 10 is a frequency model diagram of PLL 2.

Detailed Description

The technical solution of the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.

As shown in fig. 1, in an embodiment of the present invention, a satellite measurement and control communication subcarrier synchronization method is disclosed, which implements synchronization and tracking of carriers through joint work of FFT and PLL1, acquires remote control subcarriers, and then tracks the remote control subcarriers with PLL2 to implement subcarrier synchronization.

The USB measurement and control modulates the remote control subcarrier to a carrier with higher frequency through phase modulation, and the general USB measurement and control requires that the capture range of the Doppler frequency offset of the carrier of a receiver is +/-115 kHz, and the Doppler change rate is +/-32 kHz/s. The carrier synchronization and tracking are mainly realized by the joint work of FFT and PLL1, a reasonable FFT working frequency is designed by selecting a proper FFT point number according to the requirement of indexes, and the frequency resolution and analysis time of the FFT are designed to meet the time requirement of carrier capture and tracking. Then, the FFT calculation is carried out on the signal to obtain the maximum value of the FFT, the frequency control word corresponding to the maximum value is output to the PLL1, the PLL1 captures and tracks the carrier wave by taking the maximum value as an initial value, the PLL1 is used for realizing the accurate tracking of the carrier wave, the tracking of the carrier wave can be completed through the framework of the FFT + PLL1, and then the output of the low-pass filtering can be obtained to the remote control subcarrier. The PLL2 primarily performs tracking of the remote control subcarrier.

The PLL2 of the present invention is designed by the following steps:

step one (S100): and calculating the frequency deviation and the frequency change rate of the remote control subcarrier, and selecting the design values of the fast capture zone and the fast capture time according to the frequency deviation.

Since Doppler is represented in the frequency domainThe frequency deviation is represented as compression and broadening of a signal period in a time domain, when a carrier with Doppler is tracked and then removed through demodulation, the Doppler still exists in a subcarrier, and the relation between the Doppler condition and the carrier is f_{subc_d}＝f_subcf_{c_d}/f_cWherein f is_{subc_d}And f_{c_d}Doppler frequency, f, of subcarrier and carrier respectively_subcAnd f_cThe doppler frequency and doppler change rate of the subcarrier residue are calculated for the subcarrier frequency and carrier frequency, respectively, and then used as the input for designing the subcarrier tracking PLL2, from which the fast acquisition band and fast acquisition time of the PLL2 can be designed.

The general carrier Doppler capture range required by USB measurement and control is +/-115 kHz, the received signal is down-converted to zero frequency and Doppler is analyzed by 1024-point FFT with a sampling rate of 250kHz, the analysis frequency range is +/-125 kHz, the analysis time is 4.096ms, the frequency resolution is 244Hz, a certain margin carrier is selected during design, and the designed value of a fast capture band of PLL1 is +/-500 Hz.

When the carrier wave realizes the tracking, the Doppler frequency of the subcarrier is f_{subc_d}＝f_subcf_{c_d}/f_cThe designed fast capture band of PLL2 is selected to have a Doppler frequency of less than + -10 Hz, a Doppler change rate of + -0.2 Hz/s, and a margin for the residual of the subcarrier calculated by the equation, and + -50 Hz.

Step two (S200): the overall loop of PLL2 is designed, which includes the comparator and phase detector, the loop filter, and the DDS, of PLL2, and determines the Z-domain transfer function and phase gain of the DDS, as well as determining the coefficients of the loop filter.

As shown in fig. 2, the overall loop of PLL2 includes three parts: a comparator, a phase discriminator, a loop filter and a DDS. The ramp-up signal is the phase of the input signal, the comparator compares the phase of the input signal with the phase of the local recovery signal, then the phase difference is input into a phase discriminator (the phase discriminator performs phase discrimination by adopting a sine function), the output of the phase discriminator is filtered by a loop filter and then output to a DDS and an oscilloscope, the DDS adjusts the phase of the output signal of the DDS through the input error signal, and then closed-loop feedback is formed. The Z-domain transfer function that can be derived from each component for the entire PLL2 phase-locked loop is as follows:

the poles of the closed loop transfer functions calculated by the two modes are ensured to be the same, and the following steps can be deduced:

wherein, c₁And c₂The coefficient of the loop filter is shown, xi is a damping ratio, which mainly affects overshoot and response time, and 0.707 and omega are generally adopted in general engineering_nIs the undamped natural angular frequency, K, of the loop_DDSAnd T is the closed loop period of the loop.

The phase discriminator adopts a sine function to discriminate phase, because the phase discriminator is sine, the output value of the phase discriminator is +/-1, the normalization effect can be realized, the phase discriminator cannot adopt a multiplier to discriminate phase and input signal amplitude or be related, the design of loop filter coefficients is very effective, and the change of filter parameters caused by the difference of input signal amplitude can be avoided.

The DDS is a direct digital frequency synthesizer, which is mainly realized by a lookup table, and a control word of the DDS consists of two parts, namely frequency control of a local oscillator and an error signal. The error signal e (n) causes a DDS output frequency of: f. of_out＝e(n)×f_clk/2^NWherein f is_clkAnd N is the working clock of the DDS, and the length of a phase control word, namely the number of bits of a phase accumulator. Assuming that the loop closed loop period is T, the error signal e (n) is sampled every T seconds to correct the center frequency f₀. The Z-domain phase transfer function of the DDS only takes into account the phase change caused by the error signal e (n), the phase output at time nT is as follows:

2πf₀nT+φ(nT)＝2πf₀(n-1)T+φ((n-1)T)+2πf₀T+2πe((n-1)T)f_clk/2^NT

the equation removes the carrier nominal frequency terms on both sides and rewrites them to the discrete form phi (n) ═ phi (n-1) +2 pi e (n-1) f_clk/2^NT, then the phase Z domain transfer function of the DDS is: h (z) ═ 2 pi f_clk/2^NT/(z-1), DDS phase gain is K_DDS＝2πf_clk/2^NT。

The DDS is an important component of the entire PLL2, and its constituent schematic block diagram is shown in fig. 3, and mainly includes a phase accumulator, a lookup table unit, and a lookup table address truncating unit. The input of the phase accumulator comprises a frequency control word and an error signal, the frequency control word and the error signal are accumulated under the control of a clock, an accumulated result is sent to a lookup table address truncation unit after passing through a modulus and phase register, and the digit of the phase accumulator is 32 bits. The lookup table address truncation unit is mainly used for truncating the low order of the 32-bit address of the phase accumulator, generating a 12-bit lookup table address after the low order of the address is rounded down by the multiplier, and inputting the lookup table address into the lookup table unit, wherein the lookup table address is used for addressing the lookup table and outputting two paths of orthogonal local signals. The lookup table unit stores sine signals and cosine signals of one period, and the sine signals and the cosine signals of one period are sampled by 2¹²The point, namely the address line is 12 bits, wherein the quantizer mainly completes the amplitude quantization of the signal to meet the requirement of FPGA fixed point, and the sine signal lookup table and the cosine signal lookup table correspondingly output sine output and cosine output after respectively passing through respective quantizer wave, subtracter and gain. In the design of the DDS of the present invention, the parameters are set as follows: the working clock is f_clk3.5MHz, the frequency control word is FCW f_subc×2^Nf_clk＝8000×2³²3500000-9817068, and the closed loop period of the loop is selected to be 32 1f_clkN is the number of bits in the phase accumulator, 32, the Z-domain transfer function of DDS is h (Z) 4.61 × 10^-8/(z-1), the phase gain of DDS is K_DDS＝4.61×10^-8。

The loop filter is also an important component of the PLL2, is closely related to indexes such as a fast capture band of the loop filter and a steady-state phase difference of the loop, and affects the stability of the loop, for design, theIs of importance. The digital loop filter adopts an ideal integral filter H(s) (1+ s tau)₂)sτ₁It is changed from S domain to Z domain form by bilinear transformation, and the Z domain transfer function is H (Z) ═ 2 tau₂+T)2τ₁+Tz^-1(τ₁-τ₁z^-1)＝c₁+c₂z^-1(1-z^-1) In which τ is₁、τ₂For the digital domain loop filter coefficient c₁、c₂The corresponding analog domain coefficients. The Z threshold transfer function of the loop filter can be seen to be composed of an integral link and a direct current link.

The loop filter is selected as an ideal integral filter, the parameters of the ideal integral filter influence the frequency response of the filter, the frequency response of the ideal integral filter determines the direct current gain, the suppression of the beat signal and the passing range of the beat signal, and simultaneously determines the stability of the system, so the design of the loop filter parameters is important for the design of the whole loop. In the design of the loop filter, the damping ratio is xi ═ 0.707, and the loop undamped natural vibration angular frequency corresponding to a +/-50 Hz fast capture band is omega_n222.18rad/s, the overall loop filter coefficient is c₁＝613567，c₂88, the analog domain coefficient corresponding to the digital domain loop filter coefficient is tau₁＝Tc₂＝1.04×10^-7，τ₂＝c₁×T/c₂-T2＝0.0064。

Step three (S300): and analyzing the stability of the whole loop of the PLL2 designed in the step two, calculating a stability margin, and adjusting parameters according to the stability margin so that the stability margin meets the use requirement.

This step analyzes the stability of the loop: and calculating the pole of the system, analyzing the stability margin of the system, including the phase margin and the amplitude margin, and adjusting the parameters of the system according to the result to ensure that the phase margin and the amplitude margin of the system meet the use requirement. As shown in fig. 4, which is an open-loop bode diagram of the Z-domain system, it can be seen that the amplitude crossing frequency is the fast capture frequency of the system, the phase margin is 65.4 degrees, and the system is robust against the influence of the fluctuation that may exist.

Step four (S400): and analyzing the tracking precision of the whole loop to obtain the density ratio of the signal to noise spectrum of the input signal under the requirement of different phase precision standard deviations.

Because different applications have different requirements on the steady-state phase difference, if the demodulation of the remote control command is simply carried out, the steady-state phase difference of pi/10 can meet the use requirements, but the precision of distance measurement is difficult to ensure in the application occasions such as distance measurement. The steady state phase standard deviation of the entire loop of the design is estimated. The tracking precision of the system is analyzed in the step, and the signal-to-noise spectrum density ratio condition of the input signal under the requirement of different phase precision standard deviations is obtained.

The recovered carrier phase standard deviations were analyzed as follows:2B_Lfor the bandwidth of the loop, SN₀Is the input signal-to-noise spectral density ratio. FIG. 5 is a graph showing the relationship between loop bandwidth, input signal to noise spectral density ratio, and steady state phase error standard deviation, and FIG. 5 shows the input signal to noise spectral density ratio SN required to achieve the desired noise standard deviation for a conventional loop bandwidth setting₀。

Step five (S500): and analyzing the fast capture zone and the fast capture time of the whole loop, and comparing the actual simulation result with the theoretical result.

The design of the fast capture band and the loop filter is closely related, the output of the phase detector is a beat signal cos (2 pi Δ ft + phi) with the amplitude of 1, wherein Δ f is the difference frequency of the input signal and the frequency of the local oscillator signal, if the frequency increment obtained by controlling DDS by an error signal obtained by the beat signal through the loop filter is the difference frequency, the difference frequency is the fast capture band of the PLL, and the working frequency range of the PLL is limited in the fast capture band. The frequency response of the loop filter is:when in useIndicating that the signal frequency offset is within the fast-catch band. When the envelope of the response is within the allowable error range, the unit step response curve of the second-order system is necessarily within the allowable error range, so the transition time (i.e. the fast capture time) of the system can be obtained by the following formulaWhen Δ is 1%, t_kuaibu≈5ξω_n。

When the designed value of the fast capture band is ± 50Hz, it can be seen from fig. 6 that the fast capture band of the loop is around ± 55Hz, i.e. the range of the captured frequency offset is (-55, 55), which totals 110 Hz. Omega of the design_n222.18rad/s, range f of the quick catch zone_kuaibu＝2ξω_n2π＝2×0.707×222.18/2π＝50Hz。

When the envelope of the response is within the allowable error range, the unit step response curve of the second-order system is necessarily within the allowable error range, so the transition time (i.e. the fast capture time) of the system can be obtained by the following formulaWhen Δ is 1%, t_kuaibu≈5ξω_n0.031. The actual simulation results are consistent with the theory, as shown in fig. 7.

Step six (S600): and analyzing the capture zone and the capture time of the whole loop, and judging whether the frequency traction time meets the use requirement.

Capture band of sinusoidal second order loopSince the loop filter has a transfer function ofF (j0) ∞, so the capture band of the second-order loop is infinity. The capture time is generally frequency traction time, when the initial frequency difference is not in the quick capture zone, frequency traction is generated to increase the locking time, and the frequency traction timeDifferent delay links can be introduced for different design implementations, so that pull-in time is increased, and the pull-in time needs to be measured and analyzed to determine whether the use requirements are met.

When the initial frequency difference of the input signal is larger than the quick capture band and smaller than the capture band, the phase-locked loop can realize locking, but a frequency traction process is carried out until the phase-locked loop enters the quick capture band. The frequency pulling time of the initial frequency difference between 200 Hz and 1100Hz is shown in FIG. 8, comparing the pull-in time between the theoretical model, the phase model and the frequency model, it can be seen that the simulation result of the phase model and the theoretical calculationThe result of (a) is consistent, and the frequency model of the PLL2 (as shown in fig. 10) causes the pull-in time to increase due to the introduction of an extra delay element such as low-pass filtering during loop processing. Fig. 9 shows the case of no delay element and the frequency pulling time of the delay elements of 4, 8, 12 and 16 orders, and it can be seen that the more the delay elements, the longer the frequency pulling time, and the slower the acquisition and tracking of the signal. The length of the signal capturing time is determined by the length of the frequency pulling time, and in the actual design, appropriate parameters are selected according to requirements to optimize links which can play a delay role in the whole loop.

Step seven (S700): and analyzing the synchronous belt and the synchronous time of the whole loop, judging whether the maximum synchronous scanning rate of the ideal secondary loop is greater than the frequency change rate, and if so, obtaining the final PLL 2.

When the loop is locked, the natural frequency difference is slowly increased until the loop is out of lock, and the maximum natural frequency difference capable of maintaining the loop to be locked is called a synchronous belt. When the loop is locked, the instantaneous frequency difference is equal to 0, and the control voltage is direct current. For a loop with sinusoidal phase discrimination characteristics, there is Δ ω₀＝K_ddsF(j0)sin(θ_e(∞)) when theta_eSince the maximum natural frequency difference for maintaining the loop lock is obtained when (∞) ═ pi/2, theoretically, the timing belt of the second-order loop may be infinity.

For a phase-locked loop with sinusoidal phase discrimination characteristics, the phase-locked loop is inputThe signal is a frequency ramp signal with a phase theta₁(t)＝0.5×R×t²The steady state phase error after loop locking is a fixed valueThat is to say the steady state phase difference is related to the sweep rate R and the undamped natural angular frequency of the system. When the scanning rate is less thanTime of flightThe equation has a solution, i.e. the maximum synchronous scan rate of the ideal second order loop isDetermining the maximum synchronous scan rate of the ideal secondary loopAnd if the frequency change rate is far larger than the frequency change rate of the remote control subcarrier calculated in the step one, the PLL2 is shown to meet the requirements, and the final PLL2 can be obtained. When the angular frequency of the undamped natural vibration of the loop corresponding to the +/-50 Hz fast capture zone is omega_nWhen the Doppler frequency is 222.18rad/s, the Doppler frequency change rate is more than +/-0.2 Hz/s.

The satellite measurement and control communication subcarrier synchronization method provided by the invention adopts an architecture of FFT + PLL1+ PLL2, wherein the FFT mainly realizes coarse capture of a carrier, the PLL1 realizes fine tracking of a carrier phase on the basis of the FFT, fast capture tracking of a large Doppler range and high dynamic signal is realized through mutual matching of the FFT and the PLL1, and the PLL2 mainly completes tracking of a subcarrier. The invention has the following advantages:

(1) the large Doppler range and high dynamic signal can be captured and tracked;

(2) the method has the characteristics of high tracking precision, good stability and the like;

(3) the order of a low-pass filter in the frequency model influences the pull-in time of the system, a fir filter is adopted in the conventional design, and the IIR filter is adopted in the invention because the order is relatively higher and the delay is more, so that the locking time of the signal can be accelerated compared with the fir filter.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.