阅读说明：本技术 一种半导体器件及电子设备 (Semiconductor device and electronic equipment ) 是由 姚亚玲 伍得阳 朱千明 于 2019-04-30 设计创作，主要内容包括：本申请提供了一种半导体器件及电子设备,该半导体器件包括一个裸芯,以及设置在所述裸芯中的振荡器和屏蔽罩；其中,所述振荡器包括谐振腔,所述谐振腔包括电感；所述屏蔽罩用于罩住所述电感。本申请提供的半导体器件通过屏蔽罩罩住电感,从而在振荡器工作时,可以对该电感的电磁辐射进行屏蔽。(The application provides a semiconductor device and electronic equipment, the semiconductor device includes a bare chip, and an oscillator and a shielding case arranged in the bare chip; wherein the oscillator comprises a resonant cavity comprising an inductance; the shielding cover is used for covering the inductor. The semiconductor device provided by the application covers the inductor through the shielding cover, so that when the oscillator works, the electromagnetic radiation of the inductor can be shielded.)

A semiconductor device, comprising:

a bare chip, and an oscillator and a shielding cover arranged in the bare chip; wherein the oscillator comprises a resonant cavity comprising an inductance;

the shielding cover is used for covering the inductor.

The semiconductor device of claim 1, wherein the resonant cavity further comprises: the variable capacitor and the switched capacitor array are respectively connected with the inductor in parallel; the shield is further configured to shield at least one of the variable capacitor and the switched capacitor array.

The semiconductor device according to claim 1 or 2, wherein the oscillator further comprises: a cross-coupling tube coupled to the resonant cavity; the shielding case is also used for covering the cross coupling pipe.

The semiconductor device according to any one of claims 1 to 3, further comprising: an encapsulation structure covering the die, the die comprising: the packaging structure comprises a substrate and a plurality of metal layers arranged on the substrate in a stacked mode, wherein at least two first metal layers in the metal layers are respectively provided with a shielding ring, a shielding layer is arranged on the packaging structure, and the shielding layer is electrically connected with at least two shielding rings arranged on the at least two first metal layers to form the shielding cover.

The semiconductor device according to claim 4, wherein the shield ring provided on each first metal layer is a metal ring.

The semiconductor device according to claim 4 or 5, wherein the inductor is provided on at least one second metal layer of the plurality of metal layers; at least one of the at least two first metal layers is different from the at least one second metal layer, and at least one of the at least two first metal layers is located on the at least one second metal layer.

The semiconductor device of claim 4, wherein a vertical projection of each shield ring on the at least one second metal layer surrounds the inductor.

The semiconductor device according to any one of claims 4 to 7, wherein the structure of each shield ring is a symmetrical structure, the structure of the inductor is a symmetrical structure, and a symmetry axis of the symmetrical structure is coaxial with a symmetry axis of the inductor.

The semiconductor device according to any one of claims 4 to 8, wherein adjacent shield rings of the at least two shield rings are electrically connected through a via.

The semiconductor device according to any one of claims 4 to 9, wherein the shield layer is electrically connected to the uppermost shield ring of the at least two shield rings through a plurality of metal posts.

The semiconductor device of claim 10, wherein the inductor has a symmetrical structure, and the plurality of metal pillars are arranged symmetrically along a symmetry axis of the inductor.

The semiconductor device according to claim 10 or 11, wherein the plurality of metal pillars includes a plurality of first metal pillars and a plurality of second metal pillars, and wherein the first metal pillars and the second metal pillars have different diameters.

The semiconductor device according to any one of claims 10 to 12, wherein when adjacent ones of the at least two shield rings are electrically connected through a via; or the shielding layer is electrically connected with the shielding ring positioned on the uppermost layer in the at least two shielding rings through a plurality of metal posts;

and the gap between any adjacent metal columns and the gap between any adjacent via holes are determined according to the radiation frequency of the inductor and a target attenuation value.

The semiconductor device of claim 13, wherein a gap between any adjacent metal pillars and a gap between any adjacent vias is less than one tenth of a wavelength corresponding to a frequency of radiation of the inductor.

The semiconductor device according to any one of claims 4 to 14, further comprising: a ground layer disposed in the die, the ground layer being between the substrate and the at least one second metal layer.

The semiconductor device according to any one of claims 1 to 15, wherein the inductor comprises: the inductor comprises a first inductor and a second inductor which are connected in series, wherein the first inductor and the second inductor are in a symmetrical structure.

A semiconductor device is characterized by comprising a bare chip, an oscillator and a shielding structure, wherein the oscillator and the shielding structure are arranged in the bare chip; wherein the content of the first and second substances,

the oscillator comprises a resonant cavity comprising an inductance;

the shielding structure at least comprises a first shielding ring which is arranged on the same layer as the inductor and surrounds the inductor, and at least one second shielding ring which is arranged on the different layer from the inductor; wherein the first shield ring is electrically connected to the at least one second shield ring.

The semiconductor device of claim 17, wherein the die comprises: the metal layer structure comprises a substrate and a plurality of metal layers which are arranged on the substrate in a laminated mode; wherein the inductor and the first shield ring are disposed on at least one second metal layer of the plurality of metal layers; the second shield ring is disposed on at least one first metal layer of the plurality of metal layers.

The semiconductor device of claim 18, wherein a perpendicular projection of each second shield ring on the at least one second metal layer surrounds the inductor.

The semiconductor device according to claim 18 or 19, wherein the first shield ring and each second shield ring have a symmetrical structure, and the inductor has a symmetrical structure;

and the respective symmetry axes of the first and second shield rings are coaxial with the symmetry axis of the inductor.

The semiconductor device according to claim 18 or 19, wherein adjacent ones of the first and second shield rings are electrically connected by a via.

The semiconductor device according to any one of claims 17 to 21, further comprising: covering the packaging structure of bare core, the shielding structure still includes the shielding layer that sets up on the packaging structure, just first shield ring reaches the shield ring that is located the superiors in at least one second shield ring with the shielding layer is connected through a plurality of metal posts electricity.

The semiconductor device according to claim 22, wherein a structure of the inductor is a symmetrical structure; the metal posts are symmetrically arranged along the symmetry axis of the inductor.

The semiconductor device according to claim 22 or 23, wherein the plurality of metal pillars comprises a plurality of first metal pillars and a plurality of second metal pillars, and wherein the first metal pillars and the second metal pillars have different diameters.

The semiconductor device according to any one of claims 22 to 24, wherein when adjacent ones of the at least two shield rings are electrically connected through a via; or the shielding layer is electrically connected with the shielding ring positioned on the uppermost layer in the at least two shielding rings through a plurality of metal posts;

and the gap between any adjacent metal columns and the gap between any adjacent via holes are determined according to the radiation frequency of the inductor and a target attenuation value.

The semiconductor device of claim 25, wherein a gap between any adjacent metal pillars and a gap between any adjacent vias is less than one tenth of a wavelength corresponding to a frequency of radiation of the inductor.

The semiconductor device of any of claims 18-26, further comprising a ground layer disposed in the die, the ground layer being positioned between the substrate and the at least one second metal layer.

An electronic device comprising a substrate, and the semiconductor device according to any one of claims 1 to 16 or the semiconductor device according to any one of claims 17 to 27, the semiconductor device being provided over the substrate.