阅读说明：本技术 一种功率因数矫正装置及控制芯片 (Power factor correcting device and control chip ) 是由 涂才根 张胜 谭在超 罗寅 丁国华 于 2021-09-22 设计创作，主要内容包括：本发明公开了一种功率因数矫正控制芯片,控制芯片包括供电及偏置模块、振荡器模块、非线性增益模块、比较器CMP、电流运算放大器OTA1、驱动模块以及电压运算放大器OTA2,辅助供电端通过VIN管脚连接供电及偏置模块,所述电流运算放大器OTA1负输入端接IS管脚,其输出端接非线性增益模块,所述电压运算放大器OTA2负输入端接VS管脚,其输出端接非线性增益模块,非线性增益模块输出两路信号分别送至比较器CMP的正负输入端,一路信号VP为受控参考电压,另一路信号VM为受控的斜坡信号,本发明通过电压环、电流环的双环控制,无需专门设计复杂的乘法器结构,即可实现PFC技术,既简化了控制IC的设计,又减少了IC封装引脚,缩小了封装体积,同时又省去了诸多的外围器件。(The invention discloses a power factor correction control chip, which comprises a power supply and bias module, an oscillator module, a nonlinear gain module, a comparator CMP, a current operational amplifier OTA1, a drive module and a voltage operational amplifier OTA2, wherein an auxiliary power supply end IS connected with the power supply and bias module through a VIN pin, the negative input end of the current operational amplifier OTA1 IS connected with an IS pin, the output end IS connected with the nonlinear gain module, the negative input end of the voltage operational amplifier OTA2 IS connected with a VS pin, the output end IS connected with the nonlinear gain module, the nonlinear gain module outputs two paths of signals which are respectively sent to the positive and negative input ends of the comparator CMP, one path of signal VP IS a controlled reference voltage, the other path of signal VM IS a controlled ramp signal, the invention can realize the PFC technology through double-ring control of an electric pressure ring and an electric current ring without specially designing a complex multiplier structure, the design of the control IC is simplified, the IC packaging pins are reduced, the packaging volume is reduced, and a plurality of peripheral devices are saved.)

1. A power factor correction control chip IS characterized by comprising a power supply and bias module, an oscillator module, a nonlinear gain module, a comparator CMP, a current operational amplifier OTA1, an RS trigger, a driving module and a voltage operational amplifier OTA2, wherein an auxiliary power supply end IS connected with the power supply and bias module through a VIN pin, the negative input end of the current operational amplifier OTA1 IS connected with an IS pin, the output end of the current operational amplifier OTA 3526 IS connected with a nonlinear gain module, the negative input end of the voltage operational amplifier OTA2 IS connected with a VS pin, the output end of the voltage operational amplifier OTA2 IS connected with the nonlinear gain module, two paths of signals output by the nonlinear gain module are respectively sent to the positive input end and the negative input end of the comparator CMP, one path of signals VP IS controlled reference voltage, and the other path of signals VM IS controlled ramp signals.

2. The pfc control chip of claim 1, wherein the non-linear gain module comprises a transistor Q1, the ICONP signal is connected to the base of a transistor Q1, the collector of the transistor Q1 is connected to the PM0OS mirror P1 and the PMOS mirror P2, the drain of the PMOS mirror P2 is connected to ground through a resistor R6, the drain of the PMOS mirror is connected to the positive input of the comparator CMP, the emitter of the transistor Q1 is connected to a resistor R5, the VCOMP signal is connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the PMOS mirror P3 and the PMOS mirror P4, the drain of the PMOS mirror P4 is connected to ground through a capacitor C4, the drain of the transistor CMP is connected to the negative input, the negative input of the comparator CMP is connected to ground through a pull-down transistor N1, the pull-down transistor N1 is connected to the lower gate of the transistor Q2 is connected to a resistor R7.

3. The PFC control chip of claim 2, wherein the PMOS mirror transistor P1 and the PMOS mirror transistor P2 are connected via a gate terminal, the gate terminal of the PMOS mirror transistor P1 is connected to a drain terminal, the PMOS mirror transistor P3 and the PMOS mirror transistor P4 are connected via a gate terminal, and the gate terminal and the drain terminal of the PMOS mirror transistor P3 are connected.

4. The PFC control chip of claim 3, wherein the non-linear gain block is connected to an input of the comparator CMP.

5. The PFC control chip of claim 4, wherein the positive input of the current operational amplifier OTA1 is set to a fixed value voltage.

6. A power factor correction device with a power factor correction control chip according to any one of claims 1 to 5, wherein the device comprises a control chip IC, a rectifier bridge, a filter capacitor C1, a resistor R0, a buffer resistor R1, a current sampling resistor R2, a current loop compensation capacitor C2, a voltage loop compensation capacitor C3, an inductor L and a pre-supply diode D6, the buffer resistor R1 IS connected with the negative input terminal of a current operational amplifier OTA1 through an IS pin, and the output terminal of the current operational amplifier OTA1 and the current loop compensation capacitor C2 are connected with a non-linear gain module through an ICOMP pin.

7. The apparatus as claimed in claim 6, wherein the intermediate node between the resistor R3 and the resistor R4 is connected to the negative input terminal of the operational voltage amplifier OTA2 through the VS pin of the control chip IC, and the output terminals of the voltage loop compensation capacitor C3 and the operational voltage amplifier OTA2 are connected to the nonlinear gain module through the VCOMP pin.

8. The apparatus for power factor correction according to claim 7, wherein the buffer resistor R1 and the current loop compensation capacitor C2 are connected to the current sampling resistor R2.

9. The apparatus of claim 8, wherein the resistor R3 and the resistor R4 form an output voltage sampling network, and the pre-power diode D6 is connected in parallel with the inductor L to form a pre-power output.

10. The apparatus for power factor correction according to claim 9, wherein the resistor R0 is an oscillation frequency setting resistor, and the oscillation frequency setting resistor is connected to the oscillator module via an RT pin.

Technical Field

The invention relates to the technical field of power management, in particular to a power factor correction control chip.

Background

With the development of power electronic technology, the power density of the electric energy conversion device is greatly improved, and the size and the weight of the device are smaller and smaller. When a large number of power electronic equipment are connected into a power grid for use, alternating current needs to be converted into direct current, harmonic waves are generated when various equipment are applied, harmonic current flows into a public power grid, the voltage waveform of the power grid is distorted, and the power grid is polluted.

In order to avoid polluting the power grid, electronic equipment is generally required to be designed by modification so as to reduce the harmonic content of input current introduced by the electronic equipment. Therefore, the Power Factor Correction (PFC) technology is widely applied, after the PFC technology is carried out, the current extracted from an alternating current power grid by the electronic equipment is in a sine wave form, the phase of the current follows the alternating current voltage, and for the electronic equipment, the input voltage and the input current reach the same frequency and phase state, so that the input current harmonic wave can be greatly reduced, and the power factor value of the scheme is close to 1.

The existing PFC technology usually requires a built-in multiplier, which is used to ensure that the input current follows the frequency and phase of the input voltage. The prior art PFC is shown in fig. 1. D1-D4 are rectifier bridges; c1 is a filter capacitor, and the capacitance value is usually lower than 200 nF; r1 and R2 form a sampling network of a line voltage Vbus, and the middle node is connected with a VRMS pin of the IC; l is an inductor; d5 is a freewheeling diode; n1 is a power tube; r4 is a current sampling resistor; r3 sets the resistance for the switching frequency; r5 is the multiplier output resistance; c2 is current loop compensation capacitance; c3 is a voltage loop compensation capacitor; r6 and R7 form an output sampling network, and the middle node is connected with a VS pin of the IC; cout is the output capacitance.

In the prior art, the pins VS, VCOMP, the operational amplifier OTA1 and the external compensation capacitor C3 form a voltage loop; pin IS, ICOMP, operational amplifier OTA2 and external compensation capacitor C2 form a current loop. The function of the voltage loop IS to design the output voltage Vout of the overall scheme, and the function of the current loop IS to control the average current of the IS samples, i.e., the positive input average current of the operational OTA2 IS equal to the negative input. Due to the design of the multiplier Multplier, one input end of the multiplier is VRMS, the signal waveform of the multiplier is also in a half sine wave shape, the other input end of the multiplier is the output of the operational amplifier OTA1, and the output voltage of the voltage loop is relatively small in fluctuation because the bandwidth of the voltage loop is not high, so that the output of the multiplier is also in a half sine wave shape. From the above analysis, the average current shape of the current sampling pin IS should also be a half sine wave shape, and the IS sampling current reflects the input current Iin, so that the input voltage Vbus and the input current Iin are in the same frequency and phase, the harmonic content IS reduced, and the power factor value IS improved.

However, in the prior art, a multiplier needs to be designed, so that the design difficulty is increased, two pins, namely VRMS and MULT, need to be added due to the use of the multiplier, so that the size is increased on the package, and the VRMS pin needs a sampling network to realize the sampling of the input voltage Vbus.

Disclosure of Invention

In order to solve the problems, the invention discloses a power factor correction control chip which comprises a power supply and bias module, an oscillator module, an RS trigger, a nonlinear gain module, a comparator CMP, a current operational amplifier OTA1, a driving module and a voltage operational amplifier OTA2, wherein an auxiliary power supply end IS connected with the power supply and bias module through a VIN pin, the negative input end of the current operational amplifier OTA1 IS connected with an IS pin, the output end of the current operational amplifier OTA1 IS connected with the nonlinear gain module, the negative input end of the voltage operational amplifier OTA2 IS connected with a VS pin, the output end of the voltage operational amplifier OTA2 IS connected with the nonlinear gain module, the nonlinear gain module outputs two paths of signals which are respectively sent to the positive input end and the negative input end of the comparator CMP, one path of signal VP IS a controlled reference voltage, and the other path of signal VM IS a controlled ramp signal.

In the scheme, the LDO/BIAS/UVLO is a power supply and BIAS module and generates a low-voltage power supply, BIAS voltage/current, an enable signal and the like required by an internal module; OSC is an oscillator module, and oscillation frequency is set through an external resistor of an RT pin; the nonlinear gain module is controlled by the output of a current loop and the output of a voltage loop, and the Driver is a driving module.

As an improvement of the present invention, the non-linear gain module comprises a transistor Q1, the ICONP signal is connected to the base of a transistor Q1, the collector of the transistor Q1 is connected to the PM0OS mirror P1 and the PMOS mirror P2, the drain of the PMOS mirror P2 is connected to ground by a resistor R6, the drain is connected to the positive input of a comparator CMP, the emitter of the transistor Q1 is connected to a resistor R5, the VCOMP signal is connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the PMOS mirror P3 and the PMOS mirror P4, the emitter of the transistor Q2 is connected to a resistor R7, the drain of the PMOS mirror P4 is connected to ground by a capacitor C4, the drain is connected to the negative input of the comparator CMP, the negative input of the comparator CMP is connected to ground by a pull-down transistor N1, the gate of the pull-down transistor N1 is connected to the driving module, the output of the comparator is connected to the S terminal of the RS trigger, the clock signal R of the RS trigger is connected to a reverse driving module, meanwhile, the Q end of the RS trigger is connected with the grid end of the N1 through an inverter.

As an improvement of the invention, the PMOS mirror tube P1 and the PMOS mirror tube P2 are connected through a grid end, the grid end of the PMOS mirror tube P1 is connected with a drain end, the PMOS mirror tube P3 and the PMOS mirror tube P4 are connected through a grid end, and the grid end and the drain end of the PMOS mirror tube P3 are connected.

As a modification of the present invention, the positive input terminal of the current operational amplifier OTA1 is set to a fixed value voltage.

As an improvement of the invention, the nonlinear gain module is connected to the input of the comparator CMP.

The device comprises a control chip IC, a rectifier bridge, a filter capacitor C1, a resistor R0, a buffer resistor R1, a current sampling resistor R2, a current loop compensation capacitor C2, a voltage loop compensation capacitor C3, an inductor L, a pre-supply diode D6, a power switch tube N2, a freewheeling diode D5, a resistor R3, a resistor R4 and an output capacitor Cout, wherein the buffer resistor R1 IS connected with the negative input end of a current operational amplifier OTA1 through an IS pin, and the output end of the current operational amplifier OTA 35 1 and the current loop compensation capacitor are connected with a nonlinear gain module through an ICOMP pin.

As a modification of the present invention, the middle node between the resistor R3 and the resistor R4 is connected to the negative input terminal of the voltage operational amplifier OTA2 through the VS pin of the control chip IC, and the output terminals of the voltage loop compensation capacitor C3 and the voltage operational amplifier OTA2 are connected to the nonlinear gain module through the VCOMP pin.

As an improvement of the invention, a buffer resistor R1 and a current loop compensation capacitor C2 are connected with a sampling resistor R2.

As an improvement of the present invention, the resistor R3 and the resistor R4 form an output voltage sampling network, and the pre-power diode D6 is connected in parallel with the inductor L to form a pre-power output.

As a modification of the present invention, the resistor R0 is an oscillation frequency setting resistor, and the oscillation frequency setting resistor is connected to the oscillator module through an RT pin.

The invention has the beneficial effects that:

1) the invention provides a power factor correction device, a control chip only needs 8 pins, and the whole scheme is simpler;

2) the PFC technology can be realized only by utilizing a voltage loop and a current loop, a built-in multiplier and related functional pins are omitted, the periphery is saved, and the volume of the scheme is reduced.

Drawings

Fig. 1 is a circuit structure diagram of a PFC technique in the prior art.

Fig. 2 is a circuit diagram of the PFC technique according to the present invention.

Fig. 3 is a circuit diagram of the nonlinear gain module according to the present invention.

Fig. 4 is a graph of the relationship between the comparator input signal and the output duty cycle.

Detailed Description

The present invention will be further illustrated with reference to the accompanying figures 1-4 and the following detailed description, which should be understood to be illustrative only and not to limit the scope of the invention.

Example (b): as shown in fig. 2, the present embodiment provides a power factor correction device, where the device includes a control chip IC, a rectifier bridge, a filter capacitor C1, a resistor R0, a buffer resistor R1, a current sampling resistor R2, a current loop compensation capacitor C2, a voltage loop compensation capacitor C3, an inductor L, a pre-supply diode D6, a power switch tube N2, a freewheeling diode D5, a resistor R3, a resistor R4, and output capacitors Count, D1-D4, to form the rectifier bridge, a capacitance value of the filter capacitor C1 is usually lower than 200nF, the resistor R0 is an oscillation frequency setting resistor, and is placed between an RT pin and ground, the oscillation frequency setting resistor is connected to an oscillator module through the RT pin, and a voltage loop compensation capacitor C3 is placed between a VCOMP pin and ground. The resistor R1 IS connected with the negative input end of the current operational amplifier OTA1 through an IS pin, the output end of the current operational amplifier OTA1 and the current loop compensation capacitor are connected with the nonlinear gain module through an ICOMP pin, the middle node of the resistor R3 and the resistor R4 IS connected with the negative input end of the voltage operational amplifier OTA2 through a VS pin of the control chip IC, and the capacitor C3 and the output end of the voltage operational amplifier OTA2 are connected with the nonlinear gain module through a VCOMP pin. The resistor R1 and the current loop compensation capacitor C2 are connected with the sampling resistor R2. The resistor R3 and the resistor R4 form an output voltage sampling network, and the pre-power diode D6 is connected with the inductor L in parallel to form pre-power output.

The working principle is as follows: after the system is powered on, Vbus generates a voltage signal in a half sine wave shape, the Vbus firstly supplies power for output through a pre-power supply diode D6, and the output voltage Vout is quickly powered on. When the VS voltage is lower than 3V, the voltage loop OTA2 inside the chip generates a higher voltage on VCOMP, and in a NonlinerGain module (non-linear gain module), the higher the voltage of VCOMP, the larger the output duty cycle, and therefore the output voltage Vout will rise; when the output voltage rises above the target value, i.e. the VS voltage is higher than 3V, the VCOMP voltage will drop, the duty cycle will be reduced, and the output voltage Vout will be lowered, so that the output voltage Vout can be adjusted to the target voltage by the voltage loop, and the voltage sampling pin VS is maintained at about 3V.

For the current loop, the positive input of OTA1 IS set to a lower voltage (e.g., 20 mV), the negative input IS pin IS, and the sampling voltage at pin IS always a negative voltage due to the placement of sampling resistor R2, which actually reflects the inductor current Iin. The greater the input current Iin, the lower IS voltage (greater absolute value) and therefore the greater the ICOMP voltage output by the operational amplifier OTA1, which in a NonlinerGain module results in a lower duty cycle and a lower ICOMP voltage results in a higher duty cycle. For the operational amplifier OTA1, the ICOMP voltage IS actually an integral voltage of the IS voltage, and the lower the IS voltage (the higher the absolute value), i.e., the larger Iin, i.e., the larger the sampling current Isense on the sampling resistor R2, the larger the ICOMP voltage.

For the Boost system, if the Iin current is the Isense current, the current is as follows:

Isense=Iin（1）

for the current op-amp OTA1, the ICOMP voltage IS the integral of the IS voltage, and then:

Avg（|IS|）∝ ICOMP（2）

Avg（Isense）∝ ICOMP（3）

for Boost topology, the duty cycle has the following relationship to the line voltage Vbus:

1/D ∝ Vbus（4）

the nonlinear gain module of the invention is set to realize the following relationship:

1/ICOMP ∝ D（5）

then, through the conversion of the above relation, there must be:

Vbus ∝ Iin（6）

namely, the input voltage is in direct proportion to the input current, thereby realizing the PFC function.

As shown in fig. 2, a power factor correction control chip comprises a power supply and bias module, an oscillator module, a nonlinear gain module, a comparator CMP, a current operational amplifier OTA1, a driving module and a voltage operational amplifier OTA2, wherein an auxiliary power supply terminal IS connected with the power supply and bias module through a VIN pin, a negative input terminal of the current operational amplifier OTA1 IS connected with an IS pin, the output end of the current operational amplifier OTA1 is connected with the nonlinear gain module, the positive input end of the current operational amplifier OTA1 is provided with a voltage with the value of 20mV, the negative input end of the voltage operational amplifier OTA2 is connected with the VS pin, the output end of the comparator is connected with a nonlinear gain module, the nonlinear gain module is connected with the input end of a comparator CMP, the nonlinear gain module outputs two paths of signals to be respectively sent to the positive input end and the negative input end of the comparator CMP, one path of signal VP is a controlled reference voltage, and the other path of signal VM is a controlled ramp signal. The LDO/BIAS/UVLO is a power supply and BIAS module and generates a low-voltage power supply, BIAS voltage/current, an enabling signal and the like required by an internal module; OSC is an oscillator module, and oscillation frequency is set through an external resistor of an RT pin; the nonlinear gain module is controlled by the output of a current loop and the output of a voltage loop, and the Driver is a driving module.

As shown in fig. 3, the nonlinear gain module includes a transistor Q1, the ICONP signal is connected to the base of a transistor Q1, the collector of the transistor Q1 is connected to the PM0OS mirror P1 and the PMOS mirror P2, the drain of the PMOS mirror P2 is connected to ground through a resistor R6, the drain is connected to the positive input of the comparator CMP, the PMOS mirror P1 is connected to the PMOS mirror P2 through a gate, the gate of the PMOS mirror P1 is connected to the drain, the PMOS mirror P3 is connected to the PMOS mirror P4 through a gate, and the gate of the PMOS mirror P3 is connected to the drain. An emitter of the triode Q1 is connected with a resistor R5, a VCOMP signal is connected with a base of the triode Q2, a collector of the triode Q2 is connected with a PMOS mirror tube P3 and a PMOS mirror tube P4, an emitter of the triode Q2 is connected with a resistor R7, a drain of the PMOS mirror tube P4 is connected with a capacitor C4 in a grounding mode, a drain of the capacitor C4 is connected with a negative input end of a comparator CMP at the same time, a pull-down tube N1 is arranged in a grounding mode on the negative input end of the comparator CMP, a gate end of the pull-down tube N1 is connected with a driving module, an output of the comparator is connected with an S end of an RS trigger, an R end of the RS trigger is connected with a clock signal CLK, a Q end of the RS trigger is sent to the driving module through an inverter, and a Q end of the RS trigger is connected with a gate end of the N1 through an inverter.

In fig. 2, the ratio of the two groups of mirror tubes is set to be 1: 1, the positive input voltage VP of the comparator can be expressed as:

（7）

the slope of the comparator negative terminal VM, i.e. the charging current to the capacitor C1, can be expressed as:

（8）

for the comparator CMP, if the low level is output, the Gate is controlled to output the high level, and the low level of the clock signal CLK controls the Gate to output the low level.

For the voltage loop, the VCOMP voltage controls the duty ratio by controlling the slope of the rising slope of the negative input VM of the comparator, i.e. the larger the VCOMP voltage, the larger the rising slope of VM, the earlier the output is turned on, i.e. the duty ratio is increased, whereas the lower the VCOMP voltage, the lower the duty ratio.

When the current loop controls the duty ratio of the output Gate, when the voltage loop is already in a stable state, namely the slope of the VM slope waveform is unchanged, the higher the VP voltage is, the smaller the duty ratio is. Fig. 4 shows a graph of the comparator input signal versus the output duty cycle, and it is clear that the VP voltage and the Gate duty cycle D exhibit an inverse relationship, namely:

1/D ∝ VP（9）

by combining the formula (7) and the formula (9), 1/ICOMP ^ D can be obtained, that is, the device system and the control chip provided by the invention can meet the requirement of the formula (5).

In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various modifications can be made to the embodiments described in the foregoing embodiments, or some or all of the technical features of the embodiments can be equivalently replaced, and the modifications or the replacements do not make the essence of the corresponding technical solutions depart from the scope of the embodiments of the present invention.