阅读说明：本技术 一种非易失性存储阵列的软错误检测方法及装置 (Soft error detection method and device for nonvolatile memory array ) 是由 王碧 王昭昊 赵巍胜 赵元富 王亮 陈雷 于 2021-09-15 设计创作，主要内容包括：本发明提供一种非易失性存储阵列的软错误检测方法及装置,所述方法包括：获取第一存储单元的存储状态和对应的第二存储单元的存储状态；若判断获知所述第一存储单元的存储状态与对应的第二存储单元的存储状态相同,则终止读取操作；其中,所述第一存储单元与对应的第二存储单元是物理隔离的。所述装置用于执行上述方法。本发明实施例提供的非易失性存储阵列的软错误检测方法及装置,避免读取错误数据,提高了非易失性存储阵列的可靠性。(The invention provides a soft error detection method and a device of a nonvolatile memory array, wherein the method comprises the following steps: acquiring a storage state of a first storage unit and a storage state of a corresponding second storage unit; if the storage state of the first storage unit is judged to be the same as that of the corresponding second storage unit, the reading operation is terminated; wherein the first memory cell is physically isolated from the corresponding second memory cell. The device is used for executing the method. The soft error detection method and the device for the nonvolatile memory array provided by the embodiment of the invention can avoid reading error data and improve the reliability of the nonvolatile memory array.)

1. A method of soft error detection for a non-volatile memory array, comprising:

acquiring a storage state of a first storage unit and a storage state of a corresponding second storage unit;

if the storage state of the first storage unit is judged to be the same as that of the corresponding second storage unit, the reading operation is terminated; wherein the first memory cell is physically isolated from the corresponding second memory cell.

2. The method of claim 1, further comprising:

and if the storage state of the first storage unit is judged to be different from the storage state of the corresponding second storage unit, acquiring corresponding data based on the storage state of the first storage unit.

3. The method of claim 1, further comprising:

writing the same data into the first storage unit and the corresponding second storage unit; when the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

4. The method of claim 1, further comprising:

and prompting that the read data has errors.

5. The method of claim 1, wherein the first memory cell and the second memory cell have different bit lines and a lateral distance between the first memory cell and the second memory cell is greater than a predetermined distance.

6. A soft error detection apparatus for a non-volatile memory array, comprising:

the acquisition module is used for acquiring the storage state of the first storage unit and the storage state of the corresponding second storage unit;

the judging module is used for terminating the reading operation after judging that the storage state of the first storage unit is the same as that of the corresponding second storage unit; wherein the first memory cell is physically isolated from the corresponding second memory cell.

7. The apparatus of claim 6, wherein the determining module is further configured to:

and after judging that the storage state of the first storage unit is different from that of the corresponding second storage unit, acquiring corresponding data based on the storage state of the first storage unit.

8. The apparatus of claim 6, further comprising:

the writing module is used for writing the same data into the first storage unit and the corresponding second storage unit; when the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 1 to 5 are implemented when the computer program is executed by the processor.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a soft error detection method and device for a nonvolatile memory array.

Background

At present, a Magnetic Random Access Memory (MRAM) using spin electron storage has performances of nonvolatile, radiation resistance, high speed, high density and low power consumption, is applied to the aerospace field, and is expected to become a next-generation general Memory.

With the development of process technology, the structure and performance of MRAM are also optimized, and Spin Orbit Torque (SOT) MRAM has the advantages of sub-nanosecond writing speed, extremely low power consumption and high reliability. The Magnetic Tunnel Junction (MTJ) of the SOT-MRAM is a three-port device comprising a heavy metal layer, a free layer, a barrier layer, a reference layer and other structures, and a storage unit of the device consists of 2 transistors and 1 Magnetic storage unit MTJ, so that read-write path isolation is realized, and read-write interference is avoided. However, the subnanosecond writing speed of the SOT-MRAM makes the magnetization reversal time width of the SOT-MTJ close to the pulse width of the radiation current, which results in the storage state of the SOT-MTJ being susceptible to Single-Event transient interference, and the writing mechanism of the SOT-MRAM is sensitive to Single-Event Upset (SEU) and multi-Bit Upsets (MBU).

Disclosure of Invention

To solve the problems in the prior art, embodiments of the present invention provide a soft error detection method and apparatus for a nonvolatile memory array, which can effectively determine a data read error generated by a high-energy particle bombardment on the nonvolatile memory array, so as to improve radiation resistance and reliability of a nonvolatile memory cell and the nonvolatile memory array.

In one aspect, the present invention provides a soft error detection method for a nonvolatile memory array, including:

acquiring a storage state of a first storage unit and a storage state of a corresponding second storage unit;

if the storage state of the first storage unit is judged to be the same as that of the corresponding second storage unit, the reading operation is terminated; wherein the first memory cell is physically isolated from the corresponding second memory cell.

In another aspect, the present invention provides a soft error detection apparatus for a non-volatile memory array, comprising:

the acquisition module is used for acquiring the storage state of the first storage unit and the storage state of the corresponding second storage unit;

the judging module is used for terminating the reading operation after judging that the storage state of the first storage unit is the same as that of the corresponding second storage unit; wherein the first memory cell is physically isolated from the corresponding second memory cell.

In another aspect, the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements the steps of the soft error detection method for a nonvolatile memory array according to any of the above embodiments.

In yet another aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the soft error detection method for a non-volatile memory array according to any one of the above embodiments.

The soft error detection method and device for the nonvolatile memory array provided by the embodiment of the invention can acquire the storage state of the first storage unit and the storage state of the corresponding second storage unit, and terminate the reading operation after judging that the storage state of the first storage unit is the same as the storage state of the corresponding second storage unit, thereby avoiding reading error data and improving the reliability of the nonvolatile memory array.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. In the drawings:

FIG. 1 is a flowchart illustrating a method for soft error detection of a non-volatile memory array according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a soft error detection apparatus for a non-volatile memory array according to an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a soft error detection apparatus for a non-volatile memory array according to another embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a soft error detection apparatus for a non-volatile memory array according to yet another embodiment of the present invention.

Fig. 5 is a schematic physical structure diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

In order to facilitate understanding of the technical solutions provided in the present application, the following first describes relevant contents of the technical solutions in the present application. The method comprises the steps of carrying out positioning analysis on the sensitivity of a nonvolatile memory array, when a certain memory cell of the nonvolatile memory array selected by addressing is subjected to write operation, enabling ungated transistors of a column where the memory cell is located to be sensitive tubes, enabling a sensitive path to be composed of the unselected memory cell, a Bit Line (BL for short) and a Source Line (SL for short) of the selected memory cell, and accordingly influencing the storage state of the unselected memory cell of the column, and causing reading errors when the memory cell is subjected to read operation. Therefore, the soft error detection method for the nonvolatile memory array provided by the embodiment of the invention is suitable for all nonvolatile memory arrays with the write pulse width less than or equal to the radiation pulse width, and can effectively detect the error of read data, thereby improving the radiation resistance and the reliability of the nonvolatile memory unit. The nonvolatile memory array may be a memory array in an MRAM, among others.

Fig. 1 is a schematic flowchart of a soft error detection method for a nonvolatile memory array according to a first embodiment of the present invention, and as shown in fig. 1, the soft error detection method for a nonvolatile memory array according to the present invention includes:

s101, acquiring a storage state of a first storage unit and a storage state of a corresponding second storage unit;

specifically, when data is read from a first memory cell of a nonvolatile memory array, a memory state of the first memory cell of the nonvolatile memory array may be acquired, and a memory state of a second memory cell corresponding to the first memory cell may be acquired. The first storage unit and the second storage unit are minimum storage units in a nonvolatile storage array, and the corresponding relation between the first storage unit and the second storage unit is preset.

For example, for SOT-MRAM, SOT-MTJ is the smallest memory cell. The free layer of the SOT-MTJ has the same magnetization direction as the reference layer (parallel state), and the magnetoresistance is in a low resistance state; when the magnetization directions of the free layer and the reference layer of the SOT-MTJ are different (non-parallel state), the magnetoresistance is in a high resistance state. The 0 and the 1 are recorded through the magnetic resistance, the storage state of the SOT-MTJ can be obtained through the magnetic resistance, the low magnetic resistance corresponds to one storage state, the high magnetic resistance corresponds to the other storage state, the storage state corresponding to the low magnetic resistance can be marked as a parallel state, and the storage state corresponding to the high magnetic resistance is marked as a non-parallel state.

S102, if the storage state of the first storage unit is judged to be the same as that of the corresponding second storage unit, the reading operation is terminated; wherein the first memory cell is physically isolated from the corresponding second memory cell.

Specifically, after the storage state of the first storage unit and the storage state of the corresponding second storage unit are obtained, the storage state of the first storage unit is compared with the storage state of the second storage unit, and if the storage state of the first storage unit is the same as the storage state of the second storage unit, which indicates that data is wrong, the reading operation of the data is terminated. The first storage unit and the corresponding second storage unit are physically isolated, and the purpose of physical isolation is to avoid that a radiation current pulse caused by the high-energy particles simultaneously interferes with data of the first storage unit and data of the second storage unit, for example, the first storage unit and the second storage unit are in different columns, and the interval between the first storage unit and the second storage unit is ensured to be larger than a single-particle influence range.

For example, for the SOT-MRAM, after obtaining the storage state of the SOT-MTJ1 and the corresponding storage state of the SOT-MTJ2, the storage state of the SOT-MTJ1 is compared with the storage state of the SOT-MTJ2, and if the storage state of the SOT-MTJ1 is parallel and the storage state of the SOT-MTJ2 is parallel, or the storage state of the SOT-MTJ1 is non-parallel and the storage state of the SOT-MTJ2 is non-parallel, indicating that an error occurs in the data, the read operation of the data is terminated. If the storage state of the SOT-MTJ1 is parallel and the storage state of the SOT-MTJ2 is non-parallel, or the storage state of the SOT-MTJ1 is non-parallel and the storage state of the SOT-MTJ2 is parallel, the storage state of the SOT-MTJ1 and the storage state of the SOT-MTJ2 are different, which indicates that the data is accurate, and the data can be read.

The soft error detection method for the nonvolatile memory array provided by the embodiment of the invention can acquire the storage state of the first memory cell and the storage state of the corresponding second memory cell, and after judging that the storage state of the first memory cell is the same as the storage state of the corresponding second memory cell, the reading operation is terminated, so that the reading of error data is avoided, and the reliability of the nonvolatile memory array is improved.

On the basis of the foregoing embodiments, further, the method for detecting a soft error of a nonvolatile memory array according to an embodiment of the present invention further includes:

and if the storage state of the first storage unit is judged to be different from the storage state of the corresponding second storage unit, acquiring corresponding data based on the storage state of the first storage unit.

Specifically, the storage state of the first storage unit is compared with the storage state of the second storage unit, and if the storage state of the first storage unit is different from the storage state of the second storage unit, it is indicated that the data is correct, and corresponding data can be obtained according to the storage state of the first storage unit, so that the data stored in the first storage unit can be read. The data corresponding to the storage state is set according to actual needs, and the embodiment of the invention is not limited.

For example, for SOT-MRAM, a low magnetoresistance may be set for 0 and a high magnetoresistance for 1; or a low magnetic resistance is set to correspond to 1, and a high magnetic resistance and a low magnetic resistance correspond to 0.

On the basis of the foregoing embodiments, further, the method for detecting a soft error of a nonvolatile memory array according to an embodiment of the present invention further includes:

writing the same data into the first storage unit and the corresponding second storage unit; when the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

Specifically, when data is written into a first memory cell of the nonvolatile memory array, the same data is written into the first memory cell and a corresponding second memory cell, that is, when 1 is written into the first memory cell, 1 is also written into a second memory cell corresponding to the first memory cell; when 0 is written into the first memory cell, 0 is also written into the second memory cell corresponding to the first memory cell. When the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

For example, for SOT-MRAM, SOT-MTJ1 stores a 1 in the parallel state, then the corresponding SOT-MTJ2 of SOT-MTJ1 stores a 1 in the non-parallel state; the SOT-MTJ1 stores a 0 in the non-parallel state, then the corresponding SOT-MTJ2 of SOT-MTJ1 stores a 0 in the parallel state.

On the basis of the foregoing embodiments, further, the method for detecting a soft error of a nonvolatile memory array according to an embodiment of the present invention further includes:

and prompting that the read data has errors.

Specifically, after the storage state of the first storage unit is judged to be the same as the storage state of the corresponding second storage unit, an error in reading data can be prompted.

For example, "error" information is output to indicate that an error occurred in the read data.

In addition to the above embodiments, the first memory cell and the second memory cell have different bit lines and a lateral distance between the first memory cell and the second memory cell is greater than a predetermined distance.

Specifically, in order to avoid that the data reading and writing of the first memory cell affects the data reading and writing of the second memory cell, the first memory cell and the second memory cell have different bit lines, that is, the first memory cell and the second memory cell are connected to different bit lines, and a lateral distance between the first memory cell and the second memory cell is greater than a preset distance. The preset distance is set according to actual needs, and the embodiment of the invention is not limited.

The soft error detection method of the nonvolatile memory array provided by the embodiment of the invention has the following advantages:

(1) the first memory cell and the corresponding second memory cell of the nonvolatile memory array are arranged by a physical isolation method, so that the memory cell and the reference cell of the same word line are prevented from being simultaneously subjected to MBU, and the reliability of the nonvolatile memory is improved.

(2) For the sensitive characteristic of the nonvolatile memory array, the mode that the storage state of the first storage unit is different from the storage state of the corresponding second storage unit is used as read data is utilized, the reliability of the read data can be improved, the mode is multiplexed to be used as MBU detection, redundant MTJ is not additionally added, the circuit structure is simple, and the process is easy to realize.

Fig. 2 is a schematic structural diagram of a soft error detection apparatus of a nonvolatile memory array according to an embodiment of the present invention, and as shown in fig. 2, the soft error detection apparatus of a nonvolatile memory array according to an embodiment of the present invention includes an obtaining module 201 and a determining module 202, where:

the obtaining module 201 is configured to obtain a storage state of a first storage unit and a storage state of a corresponding second storage unit; the judging module 202 is configured to terminate the reading operation after judging that the storage state of the first storage unit is the same as the storage state of the corresponding second storage unit; wherein the first memory cell is physically isolated from the corresponding second memory cell.

Specifically, when data is read from a first storage unit of the nonvolatile storage array, the obtaining module 201 may obtain a storage state of the first storage unit of the nonvolatile storage array, and obtain a storage state of a second storage unit corresponding to the first storage unit. The first storage unit and the second storage unit are minimum storage units in a nonvolatile storage array, and the corresponding relation between the first storage unit and the second storage unit is preset.

After the storage state of the first storage unit and the storage state of the corresponding second storage unit are obtained, the determining module 202 compares the storage state of the first storage unit with the storage state of the second storage unit, and if the storage state of the first storage unit is the same as the storage state of the second storage unit, it indicates that the data is in error, and the data reading operation is terminated. The first storage unit and the corresponding second storage unit are physically isolated, and the purpose of physical isolation is to avoid that a radiation current pulse caused by the high-energy particles simultaneously interferes with data of the first storage unit and data of the second storage unit, for example, the first storage unit and the second storage unit are in different columns, and the interval between the first storage unit and the second storage unit is ensured to be larger than a single-particle influence range.

The soft error detection device for the nonvolatile memory array provided by the embodiment of the invention can acquire the storage state of the first memory cell and the storage state of the corresponding second memory cell, and after judging that the storage state of the first memory cell is the same as the storage state of the corresponding second memory cell, the read operation is terminated, so that the read of error data is avoided, and the reliability of the nonvolatile memory array is improved.

On the basis of the foregoing embodiments, further, the determining module 202 is further configured to:

and after judging that the storage state of the first storage unit is different from that of the corresponding second storage unit, acquiring corresponding data based on the storage state of the first storage unit.

Specifically, the judging module 202 compares the storage state of the first storage unit with the storage state of the second storage unit, and if the storage state of the first storage unit is different from the storage state of the second storage unit, it indicates that the data is correct, and may obtain corresponding data according to the storage state of the first storage unit, so as to read the storage data of the first storage unit. The data corresponding to the storage state is set according to actual needs, and the embodiment of the invention is not limited.

Fig. 3 is a schematic structural diagram of a soft error detection apparatus for a nonvolatile memory array according to another embodiment of the present invention, and as shown in fig. 3, on the basis of the foregoing embodiments, further, the soft error detection apparatus for a nonvolatile memory array according to an embodiment of the present invention further includes a writing module 203, where:

the writing module 203 is configured to write the same data into the first storage unit and the corresponding second storage unit; when the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

Specifically, when data is written into a first memory cell of the nonvolatile memory array, the write module 203 writes the same data into the first memory cell and a corresponding second memory cell, that is, when 1 is written into the first memory cell, 1 is also written into a second memory cell corresponding to the first memory cell; when 0 is written into the first memory cell, 0 is also written into the second memory cell corresponding to the first memory cell. When the same data is stored, the storage state of the first storage unit is opposite to that of the corresponding second storage unit.

Fig. 4 is a schematic structural diagram of a soft error detection apparatus for a nonvolatile memory array according to another embodiment of the present invention, as shown in fig. 4, based on the foregoing embodiments, further, the soft error detection apparatus for a nonvolatile memory array according to an embodiment of the present invention further includes a prompt module 204, where:

the prompting module 204 is used for prompting that an error occurs in the read data.

Specifically, after determining that the storage state of the first storage unit is the same as the storage state of the corresponding second storage unit, the prompt module 204 may prompt that an error occurs in the read data.

The embodiment of the apparatus provided in the embodiment of the present invention may be specifically configured to execute the processing flows of the above method embodiments, and the functions of the apparatus are not described herein again, and refer to the detailed description of the above method embodiments.

The apparatuses, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or implemented by a product with certain functions. A typical implementation device is an electronic device, which may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

In a typical example, the electronic device specifically includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the steps of the soft error detection method of the nonvolatile memory array described above when executing the program.

Referring now to FIG. 5, a block diagram of a physical structure of an electronic device 600 suitable for implementing embodiments of the present application is shown.

As shown in fig. 5, the electronic apparatus 600 includes a Central Processing Unit (CPU)601 that can perform various appropriate works and processes according to a program stored in a Read Only Memory (ROM)602 or a program loaded from a storage section 608 into a Random Access Memory (RAM)) 603. In the RAM603, various programs and data necessary for the operation of the system 600 are also stored. The CPU601, ROM602, and RAM603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

The following components are connected to the I/O interface 605: an input portion 606 including a keyboard, a mouse, and the like; an output portion 607 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The driver 610 is also connected to the I/O interface 605 as needed. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 610 as necessary, so that a computer program read out therefrom is mounted as necessary on the storage section 608.

In particular, according to an embodiment of the present invention, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, an embodiment of the invention includes a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the soft error detection method for a non-volatile memory array described above.

In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 609, and/or installed from the removable medium 611.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.