阅读说明：本技术 一种集成无源器件的滤波器晶圆级封装结构及其方法 (Filter wafer-level packaging structure integrated with passive device and method thereof ) 是由 陈崧 杨佩佩 朱其壮 金科 吕军 于 2021-09-28 设计创作，主要内容包括：本发明实施例公开了一种集成无源器件的滤波器晶圆级封装结构及其方法。集成无源器件的滤波器晶圆级封装结构包括：晶圆衬底；滤波器结构,位于晶圆衬底的一侧,滤波器结构包括电极和叉指换能结构；封装绝缘层,位于滤波器结构远离晶圆衬底的一侧；封装绝缘层覆盖滤波器结构且完全或者不完全暴露电极,并与晶圆衬底围成封闭的容纳腔；叉指换能结构位于容纳腔内；金属无源器件层,位于封装绝缘层内且与电极电接触；金属无源器件层包括多个连接端子,封装绝缘层完全或者不完全暴露连接端子。本实施例的技术方案,在滤波器晶圆级封装过程中实现了无源器件与滤波器晶圆级的集成,从而实现了滤波器芯片的集成化和微型化以及集成工艺流程的简单化和低成本化。(The embodiment of the invention discloses a filter wafer level packaging structure of an integrated passive device and a method thereof. The wafer-level packaging structure of the filter integrated with the passive device comprises: a wafer substrate; the filter structure is positioned on one side of the wafer substrate and comprises an electrode and an interdigital transduction structure; the packaging insulating layer is positioned on one side of the filter structure, which is far away from the wafer substrate; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity with the wafer substrate in an enclosing way; the interdigital transduction structure is positioned in the accommodating cavity; the metal passive device layer is positioned in the packaging insulating layer and is electrically contacted with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals. According to the technical scheme of the embodiment, the passive device and the filter wafer level are integrated in the filter wafer level packaging process, so that the integration and the miniaturization of a filter chip and the simplification and the low cost of an integration process flow are realized.)

1. A filter wafer level package structure of an integrated passive device, comprising:

a wafer substrate;

the filter structure is positioned on one side of the wafer substrate and comprises an electrode and an interdigital transduction structure;

the packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity together with the wafer substrate; the interdigital transduction structure is positioned in the accommodating cavity;

a metal passive device layer located within the encapsulation insulating layer and in electrical contact with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals.

2. The integrated passive device filter wafer level package structure of claim 1, wherein the package insulating layer comprises:

the first packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the first packaging insulating layer covers the filter structure, completely or incompletely exposes the electrodes, and is not in contact with the interdigital transduction structure;

the second packaging insulating layer is positioned on one side, far away from the wafer substrate, of the first packaging insulating layer; the second packaging insulating layer covers the first packaging insulating layer, completely or incompletely exposes the electrodes, and encloses the wafer substrate to form a containing cavity, and the containing cavity is not in contact with the interdigital transduction structure;

a third encapsulating insulating layer; the metal passive device layer is located between the third packaging insulating layer and the second packaging insulating layer, and the third packaging insulating layer completely or incompletely exposes the connecting terminal.

3. The integrated passive device filter wafer level package structure of claim 1, wherein the metal passive device layer comprises a plurality of passive device patterns;

the passive device pattern and the connecting terminal are integrally formed.

4. The integrated passive device filter wafer level package structure of claim 3,

the passive device pattern comprises a spiral inductor pattern; the spiral direction of the spiral inductor pattern is located in the plane of the metal passive device layer.

5. The integrated passive device filter wafer level package structure of claim 4,

the thickness of the spiral inductor pattern is in the order of microns;

the magnitude of the line width and the line spacing of the spiral inductor pattern are both in the micrometer level.

6. The integrated passive device filter wafer level package structure of claim 2,

the thickness of the first packaging insulating layer is 5 mu m to 50 um; the thickness of the second packaging insulating layer is 5um to 100 um; the thickness of the third package insulating layer is 5 μm to 50 um.

7. The integrated passive device filter wafer level package structure of claim 1, further comprising: a metal rewiring layer;

the metal rewiring layer is positioned on one side, far away from the wafer substrate, of the packaging insulating layer and covers the insulating layer; the metal rewiring layer comprises a plurality of bonding pads; the welding pads are in electrical contact with the connecting terminals and in one-to-one correspondence with the connecting terminals.

8. The integrated passive device filter wafer level package structure of claim 7, further comprising: a solder resist layer and solder balls;

the solder mask layer is positioned on one side of the metal rewiring layer, which is far away from the packaging insulating layer, and covers the metal rewiring layer; the solder mask layer completely or incompletely exposes the pad;

the solder balls are positioned on one side, far away from the solder mask layer, of the soldering pad, and the solder balls are in electrical contact with the soldering pad and in one-to-one correspondence with the soldering pad.

9. A wafer-level packaging method for a filter of an integrated passive device is characterized by comprising the following steps:

providing a wafer substrate, wherein a filter structure is formed on one side of the wafer substrate and comprises an electrode and an interdigital transduction structure;

forming a packaging insulating layer and a metal passive device layer on one side of the filter structure far away from the wafer substrate; the packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity together with the wafer substrate; the interdigital transduction structure is positioned in the accommodating cavity; the metal passive device layer is positioned in the packaging insulating layer and is electrically contacted with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals.

10. The integrated passive device filter wafer level packaging method of claim 9, wherein the forming a package insulating layer and a metal passive device layer on a side of the filter structure away from the wafer substrate comprises:

forming a first dry film layer on one side, far away from the wafer substrate, of the filter structure by adopting a spraying process or a laminating process, wherein the first dry film layer covers the filter structure; etching the first dry film layer by adopting a photoetching process to form a first packaging insulating layer, wherein the first packaging insulating layer completely or incompletely exposes the electrode and is not contacted with the interdigital transducing structure;

forming a second dry film layer on one side, far away from the wafer substrate, of the first packaging insulating layer by adopting a laminating process, wherein the second dry film layer covers the first packaging insulating layer; etching the second dry film layer by adopting a photoetching process to form a second packaging insulating layer, wherein the second packaging insulating layer completely or incompletely exposes the electrode and encloses a containing cavity with the wafer substrate, and the containing cavity is not contacted with the interdigital transduction structure;

forming a metal seed layer and an electroplating metal layer on one side of the second packaging insulating layer, which is far away from the wafer substrate, by adopting a physical vapor deposition process and an electroplating process, wherein the electroplating metal layer covers the second packaging insulating layer and is in electrical contact with the electrode; etching the electroplated metal layer by adopting a photoetching process to form a metal passive device layer, wherein the metal passive device layer comprises a plurality of passive device patterns and a plurality of connecting terminals, and the passive device patterns and the connecting terminals are integrally formed;

forming a third dry film layer on one side, far away from the second packaging insulating layer, of the metal passive device layer by adopting a spraying process, wherein the third dry film layer covers the metal passive device layer; and etching the third dry film layer by adopting a photoetching process to form a third packaging insulating layer, wherein the connecting terminal is completely or incompletely exposed by the third packaging insulating layer.

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a wafer-level packaging structure of a filter integrated with a passive device and a method thereof.

Background

With the rapid development of communication technology, people have increasingly high demands for miniaturized and high-performance filters.

In the prior art, a filter and passive devices (inductors, capacitors and the like) are fixed on a packaging substrate, and electrical connection is realized through bonding wires/metal layer wiring. Alternatively, the passive device is additionally packaged into a separate device and then connected to the filter, which results in high processing cost and complicated packaging process. Or, the passive device is integrated on the glass substrate and bonded with the wafer level through the bonding process, however, the thermal expansion coefficients of the layers are not matched, and the process flow is complex. Or after the passive device is integrated into the packaging cover plate, the packaging cover plate and the wafer level are respectively processed and bound and bonded through the copper column, and the process flow is still complicated. Still other ways of integrating the filter with passive devices are not suitable for surface acoustic wave filters (SAW).

Disclosure of Invention

The embodiment of the invention provides a passive device integrated filter wafer level packaging structure and a passive device integrated filter wafer level packaging method, which are used for realizing the integration of a passive device and a filter wafer level in the filter wafer level packaging process, thereby realizing the integration and the miniaturization of a filter chip and the simplification and the low cost of an integration process flow.

In a first aspect, an embodiment of the present invention provides a passive device integrated filter wafer level package structure, where the passive device integrated filter wafer level package structure includes: a wafer substrate; the filter structure is positioned on one side of the wafer substrate and comprises an electrode and an interdigital transduction structure; the packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity together with the wafer substrate; the interdigital transduction structure is positioned in the accommodating cavity; a metal passive device layer located within the encapsulation insulating layer and in electrical contact with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals.

Optionally, the package insulating layer includes: the first packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the first packaging insulating layer covers the filter structure, completely or incompletely exposes the electrodes, and is not in contact with the interdigital transduction structure;

the second packaging insulating layer is positioned on one side, far away from the wafer substrate, of the first packaging insulating layer; the second packaging insulating layer covers the first packaging insulating layer, completely or incompletely exposes the electrodes, and encloses the wafer substrate to form a containing cavity, and the containing cavity is not in contact with the interdigital transduction structure;

a third encapsulating insulating layer; the metal passive device layer is located between the third packaging insulating layer and the second packaging insulating layer, and the third packaging insulating layer completely or incompletely exposes the connecting terminal.

Optionally, the metal passive device layer includes a plurality of passive device patterns; the passive device pattern and the connecting terminal are integrally formed.

Optionally, the passive device pattern includes a spiral inductor pattern; the spiral direction of the spiral inductor pattern is located in the plane of the metal passive device layer.

Optionally, the thickness of the spiral inductor pattern is in the order of micrometers; the magnitude of the line width and the line spacing of the spiral inductor pattern are both in the micrometer level.

Optionally, the thickness of the first encapsulation insulating layer is 5 μm to 50 μm; the thickness of the second packaging insulating layer is 5-100 μm; the third encapsulation insulating layer has a thickness of 5 to 50 μm.

Optionally, the method further includes: a metal rewiring layer; the metal rewiring layer is positioned on one side, far away from the wafer substrate, of the packaging insulating layer and covers the packaging insulating layer; the metal rewiring layer comprises a plurality of bonding pads; the welding pads are in electrical contact with the connecting terminals and in one-to-one correspondence with the connecting terminals.

Optionally, the method further includes: a solder resist layer and solder balls; the solder mask layer is positioned on one side of the metal rewiring layer, which is far away from the packaging insulating layer, and covers the metal rewiring layer; the solder mask layer completely or incompletely exposes the pad; the solder balls are positioned on one side, far away from the solder mask layer, of the soldering pad, and the solder balls are in electrical contact with the soldering pad and in one-to-one correspondence with the soldering pad.

In a second aspect, an embodiment of the present invention further provides a passive device integrated filter wafer level packaging method, where the passive device integrated filter wafer level packaging method includes:

providing a wafer substrate, wherein a filter structure is formed on one side of the wafer substrate and comprises an electrode and an interdigital transduction structure;

forming a packaging insulating layer and a metal passive device layer on one side of the filter structure far away from the wafer substrate; the packaging insulating layer is positioned on one side, far away from the wafer substrate, of the filter structure; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity together with the wafer substrate; the interdigital transduction structure is positioned in the accommodating cavity; the metal passive device layer is positioned in the packaging insulating layer and is electrically contacted with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals.

Optionally, the forming of the package insulating layer and the metal passive device layer on the side of the filter structure away from the wafer substrate includes:

forming a first dry film layer on one side, far away from the wafer substrate, of the filter structure by adopting a spraying process or a laminating process, wherein the first dry film layer covers the filter structure; etching the first dry film layer by adopting a photoetching process to form a first packaging insulating layer, wherein the first packaging insulating layer completely or incompletely exposes the electrode and is not contacted with the interdigital transducing structure;

forming a second dry film layer on one side, far away from the wafer substrate, of the first packaging insulating layer by adopting a laminating process, wherein the second dry film layer covers the first packaging insulating layer; etching the second dry film layer by adopting a photoetching process to form a second packaging insulating layer, wherein the second packaging insulating layer completely or incompletely exposes the electrode and encloses a containing cavity with the wafer substrate, and the containing cavity is not contacted with the interdigital transduction structure;

forming a metal seed layer and an electroplating metal layer on one side of the second packaging insulating layer, which is far away from the wafer substrate, by adopting a physical vapor deposition process and an electroplating process, wherein the electroplating metal layer covers the second packaging insulating layer and is in electrical contact with the electrode; etching the electroplated metal layer by adopting a photoetching process to form a metal passive device layer, wherein the metal passive device layer comprises a plurality of passive device patterns and a plurality of connecting terminals, and the passive device patterns and the connecting terminals are integrally formed;

forming a third dry film layer on one side, far away from the second packaging insulating layer, of the metal passive device layer by adopting a spraying process, wherein the third dry film layer covers the metal passive device layer; and etching the third dry film layer by adopting a photoetching process to form a third packaging insulating layer, wherein the connecting terminal is completely or incompletely exposed by the third packaging insulating layer.

The invention provides a filter wafer level packaging structure of an integrated passive device and a method thereof, wherein the structure comprises a wafer substrate and a filter structure; the filter structure is located on one side of the wafer substrate and comprises electrodes and interdigital transducing structures. The method comprises the steps of arranging a packaging insulating layer and a metal passive device layer; wherein the packaging insulating layer is positioned on one side of the filter structure far away from the wafer substrate; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity with the wafer substrate in an enclosing way; the interdigital transduction structure is positioned in the accommodating cavity; the metal passive device layer is positioned in the packaging insulating layer and electrically contacted with the electrode; the metal passive device layer comprises a plurality of connecting terminals, and the packaging insulating layer completely or incompletely exposes the connecting terminals, so that the passive device and the filter wafer level are integrated in the filter wafer level packaging process, and the integration and the miniaturization of the filter chip and the simplification and the low cost of the integration process flow are realized.

Drawings

Fig. 1 is a schematic structural diagram of a wafer level package structure of a filter integrated with a passive device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another filter wafer level package structure of an integrated passive device according to an embodiment of the present invention;

fig. 3 is a schematic top view of a spiral inductor pattern according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a top view of another spiral inductor pattern provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another filter wafer level package structure of an integrated passive device according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another filter wafer level package structure of an integrated passive device according to an embodiment of the present invention;

fig. 7 is a flowchart of a wafer level packaging method for a passive device integrated filter according to an embodiment of the present invention;

fig. 8 is a flowchart of a wafer level packaging method for a passive device integrated filter according to an embodiment of the present invention;

fig. 9 is a structural diagram of a filter wafer level packaging method for integrated passive devices according to an embodiment of the present invention;

fig. 10 is a structural diagram of another implementation of a wafer level packaging method for a filter integrated with passive devices according to an embodiment of the present invention;

fig. 11 is a structural diagram of another implementation process of a wafer level packaging method for a filter integrated with a passive device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a wafer level package structure of a filter integrated with a passive device according to an embodiment of the present invention. Referring to fig. 1, the filter wafer level package structure of the integrated passive device includes: a wafer substrate 10; a filter structure 20 located on one side of the wafer substrate 10, the filter structure 20 including an electrode 21 and an interdigital transducing structure 22; a packaging insulating layer 30 located on one side of the filter structure 20 away from the wafer substrate 10; the packaging insulating layer 30 covers the filter structure 20, completely or incompletely exposes the electrode 21, and encloses a closed accommodating cavity 31 with the wafer substrate 10; the interdigital transduction structure 22 is positioned in the accommodating cavity 31; a metal passive device layer 40 located within the encapsulation insulation layer 30 and in electrical contact with the electrode 21; the metal passive device layer 40 includes a plurality of connection terminals 41, and the encapsulation insulating layer 30 completely or incompletely exposes the connection terminals 41.

In particular, the filter structure 20 may be a surface acoustic filter structure SAW, an interdigital transducer structure 22, i.e. an interdigital transducer of a surface acoustic filter structure. The wafer substrate 10 and the filter structure 20 constitute a filter wafer level. The encapsulation insulation layer 30 is used to encapsulate the filter wafer level. The metal passive device layer 40 includes any passive device, such as a capacitor, an inductor, etc. The material of the metal passive device layer 40 may be a metal material, such as copper, gold, etc., which is not limited in this embodiment. The plurality of connection terminals 41 in the metal passive device layer 40 may be output terminals and/or output terminals of passive devices, such as solder tails of inductors, pins, signal output terminals, or signal input terminals. The integration of the metal passive device layer 40 with the wafer level of the filter can improve the performance of the filter chip, thereby improving the reliability of the filter chip. For example, the inductor is integrated with the filter wafer level, so that the characteristics and performance of the inductor are integrated in the filter wafer level, and the input voltage and the output voltage of the filter chip are stable. The interdigital transducer structure 22 is positioned in the closed accommodating cavity 31 and is not in contact with the accommodating cavity 31, so that the good performance of the filter structure 20 is ensured.

In this embodiment, in the process of packaging the filter wafer level by using the packaging insulating layer 30, the metal passive device layer 40 is formed in the packaging insulating layer 30, that is, the passive device is formed in the packaging insulating layer 30, so that the packaging insulating layer 30 is used for packaging not only the filter wafer level but also the metal passive device layer 40; meanwhile, the filter wafer level, the metal passive device layer 40 and the packaging insulating layer 30 are stacked in a three-dimensional mode, a filter wafer level packaging structure of the integrated passive device stacked in the three-dimensional mode is formed, the metal passive device layer 40 is in electric contact with the electrode 21, therefore, the metal passive device layer 40 is directly and electrically connected with the filter wafer level, electric connection is achieved without the need of bonding wires or metal layer wiring, and the electrode 21 of the filter wafer level is led out through the metal passive device layer 40.

In addition, as illustrated in fig. 1, the package insulating layer 30 exposes the connection terminal 41 in the metal passive device layer 40, so as to ensure that the external semiconductor device is electrically connected to the metal passive device layer 40, that is, the external semiconductor device is electrically connected to the passive device, and normal use performance of the filter chip is ensured. The encapsulation insulating layer 30 may be disposed according to actual requirements to completely or incompletely expose the electrode 21, so as to ensure reliable electrical connection between the metal passive device layer 40 and the electrode 21. Similarly, the completely or incompletely exposed connecting terminals 41 of the package insulating layer 30 may be disposed according to actual requirements, so as to ensure that the external semiconductor device and the metal passive device layer 40 can be reliably electrically connected.

By adopting the technical scheme of the embodiment, after the filter wafer-level packaging structure of the integrated passive device is formed, the filter wafer-level packaging structure of the integrated passive device is cut into single filter chips according to the positions of the cutting channels, and the cutting processing can be carried out by adopting a metal blade or a laser cutting technology. The implementation adopts a three-dimensional stacking mode for packaging design, thereby greatly reducing the packaging area and the size of the filter chip and simplifying the wafer level packaging process, thereby improving the packaging efficiency and reducing the packaging cost; the metal passive device layer 40 is in direct electrical contact connection with the SAW, so that the position of a transmission zero point of the filter chip can be adjusted, signal suppression of a specific frequency band is realized, and the performance of the filter chip is effectively improved; in addition, the metal passive device layer 40 is in direct electrical contact connection with the SAW, so that short-distance interconnection is realized, the electrical quality of the filter chip is effectively improved, and the line interconnection loss in the filter chip is reduced.

Fig. 2 is a schematic structural diagram of another wafer-level package structure of a filter integrated with a passive device according to an embodiment of the present invention. Referring to fig. 2, on the basis of the above embodiments, optionally, the encapsulation insulating layer 30 includes: a first package insulating layer 301 located on a side of the filter structure 20 away from the wafer substrate 10; the first encapsulating insulating layer 301 covers the filter structure 20 and completely or incompletely exposes the electrodes 21 and does not contact the interdigital transducing structure 22. A second packaging insulation layer 302, which is located on one side of the first packaging insulation layer 301 far away from the wafer substrate 10; the second packaging insulating layer 302 covers the first packaging insulating layer 301, completely or incompletely exposes the electrodes 21, and encloses a containing cavity 31 with the wafer substrate 10, the interdigital transducing structure 22 is located in the containing cavity 31, and the containing cavity 31 is not in contact with the interdigital transducing structure 22. A third encapsulating insulating layer 303; the metal passive device layer 40 is located between the third encapsulation insulating layer 303 and the second encapsulation insulating layer 302, and the third encapsulation insulating layer 303 completely or incompletely exposes the connection terminal 41.

Specifically, the materials of the first package insulating layer 301, the second package insulating layer 302, and the third package insulating layer 303 ensure that the filter crystal source stage and the metal passive device layer 40 can be packaged, insulated, and protected, and the reliable accommodating cavity 31 is formed, which is not specifically limited in this embodiment. Illustratively, the first encapsulating insulating layer 301 may be a photosensitive organic insulating coating/dry film layer. The material of the second insulating encapsulating layer 302 may be a polymer photosensitive dry film material. The material of the third encapsulation insulating layer 303 may be a photosensitive organic insulating material. Wherein, the dry film layer is not easy to collapse, thereby avoiding causing adverse effect on the wafer level of the filter.

In this embodiment, the first package insulating layer 301 and the second package insulating layer 302 may be formed first, the metal passive device layer 40 may be formed, and the third package insulating layer 303 may be formed finally. Thus, the metal passive device layer 40 is formed in the process of forming the packaging insulating layer 30 for packaging the filter wafer level, so that the same packaging insulating layer 30 not only has a packaging effect on the filter wafer level but also has a packaging effect on the metal passive device layer 40, and meanwhile, a three-dimensional stacked filter wafer level packaging structure of an integrated passive device is formed, and the integration of the passive device and the filter wafer is realized, and meanwhile, the miniaturization of a filter chip is realized.

On the basis of the above embodiments, optionally, the thickness of the first encapsulation insulating layer 301 is 5 μm to 50 μm; the thickness of the second encapsulating insulating layer 302 is 5 μm to 100 μm; the thickness of the third encapsulating insulating layer 303 is 5 μm to 50 μm. The thicknesses of the first package insulating layer 301, the second package insulating layer 302, and the third package insulating layer 303 may be set according to actual requirements, so as to ensure that the filter wafer level and the metal filter layer are packaged at the same time and ensure good integration of the two (for example, direct electrical connection between the two and reliability of performance of the two), which is not particularly limited in this embodiment.

With continued reference to fig. 2, based on the above embodiments, optionally, the perpendicular distance between the surface of the electrode 21 away from the wafer substrate 10 and the surface of the metal passive device layer 40 away from the wafer substrate 10 is a first distance d 1; the vertical distance between the surface of the electrode 21 away from the wafer substrate 10 and the surface of the second packaging insulation layer 302 away from the wafer substrate 10 is a second distance d 2; the first distance d1 is greater than the second distance d2, and the difference between the first distance d1 and the second distance d2 is greater than or equal to 5 μm, so as to ensure the formation of passive devices in the metal passive device layer 40.

With continued reference to fig. 2, based on the above embodiments, the metal passive-device layer 40 includes a plurality of passive-device patterns 42; the passive device pattern 42 is integrally formed with the connection terminal 41. The passive device pattern 42 corresponds to a passive device, and the connection terminal 41 corresponds to an output terminal or an input terminal of the passive device, so that the connection terminal 41 and the passive device pattern 42 can be etched together and are integrally formed, the passive device pattern 42 and the connection terminal 41 are guaranteed to be made of the same material and reliably electrically connected, and the process flow is simplified.

On the basis of the above embodiments, optionally, the passive device pattern 42 includes a spiral inductor pattern; the spiral direction x of the spiral inductor pattern is in the plane of the metal passive device layer 40. The inductance pattern may have other shapes than a spiral shape, and is not particularly limited herein. In the process of packaging the wafer level of the filter by using the packaging insulating layer 30, the inductor pattern and the connection terminal 41 thereof are formed in the packaging insulating layer 30, so that the characteristics and the performance of the inductor are integrated in the filter chip, the input voltage and the output voltage of the filter chip are stable, and the reliability of the filter chip is improved.

For example, fig. 3 is a schematic top view structure diagram of a spiral inductor pattern provided in an embodiment of the present invention, and fig. 4 is a schematic top view structure diagram of another spiral inductor pattern provided in an embodiment of the present invention. On the basis of the above embodiments, optionally, the number of the thicknesses of the spiral inductor patterns is in a micron level, and the specific selection of the thicknesses of the spiral inductor patterns corresponds to the optimal working performance and the optimal working state of the filter chip; illustratively, the spiral inductor pattern has a thickness greater than or equal to 3 μm; with continued reference to fig. 3 or fig. 4, the order of magnitude of the line width m1 and the line spacing m2 of the spiral inductor pattern is on the micrometer scale, and the specific selection of the line width m1 and the line spacing m2 of the spiral inductor pattern corresponds to the optimal operating performance and the optimal operating state of the filter chip; illustratively, the line width m1 and the line spacing m2 of the spiral inductor pattern are both less than or equal to 5 μm, so as to ensure the reliability of the performance of the spiral inductor pattern. The thickness of the spiral inductor pattern, the line width m1 of the spiral inductor pattern, and the line spacing m2 also determine performance parameters of the spiral inductor, so the thickness of the spiral inductor pattern, the line width of the spiral inductor pattern, and the line spacing can be set according to actual needs, and are not particularly limited.

Fig. 5 is a schematic structural diagram of another wafer-level package structure of a filter integrated with a passive device according to an embodiment of the present invention. Referring to fig. 5, based on the above embodiments, optionally, the passive device integrated filter wafer level package structure further includes: a metal rewiring layer 50; the metal rewiring layer 50 is positioned on one side of the packaging insulation layer 30 far away from the wafer substrate 10 and covers the packaging insulation layer 30; the metal rewiring layer 50 includes a plurality of pads 51; the pads 51 are in electrical contact with the connection terminals 41 and correspond one-to-one to the connection terminals 41. That is, the metal redistribution layer 50 may be made of nickel/gold (Ni/Au), and the connection terminals 41 of the metal passive device layer 40 are rearranged by providing the metal redistribution layer 50, so as to replace the conventional wire/gold wire bonding between devices, simplify the process and reduce the cost. In addition, the size of the pad 51 may be set in conformity with the size of the connection terminal 41, which is not particularly limited.

Fig. 6 is a schematic structural diagram of another wafer-level package structure of a filter integrated with a passive device according to an embodiment of the present invention. Referring to fig. 6, based on the above embodiments, optionally, the passive device integrated filter wafer level package structure further includes: solder resist layer 60 and solder balls 70; the solder mask layer 60 is positioned on one side of the metal rewiring layer 50 away from the package insulating layer 30 and covers the metal rewiring layer 50; the solder mask layer 60 completely or incompletely exposes the pads; the solder balls 70 are located on the side of the pad away from the solder mask layer 60, and the solder balls 70 are in electrical contact with the pads 51 and in one-to-one correspondence with the pads 51. The solder resist layer 60 covering the metal rewiring layer 50 and the third package insulating layer 303 may be formed on the side of the metal rewiring layer 50 away from the package insulating layer 30 by spin coating, spray coating, screen printing, or the like. The material of the solder resist layer 60 may be a negative photosensitive polymer.

With continued reference to fig. 6, based on the above embodiments, optionally, the vertical distance between the surface of the solder resist layer 60 away from the wafer substrate 10 and the surface of the solder balls 70 away from the wafer substrate 10 is a third distance d 3; the third distance d3 is 40 μm to 80 μm; the solder ball 70 is, for example, a solder ball, and the diameter of the solder ball 70 is, for example, 50 μm to 120 μm.

The embodiment of the invention also provides a wafer-level packaging method for the filter of the integrated passive device, which can be used for preparing the wafer-level packaging structure for the filter of the integrated passive device in any technical scheme. Fig. 7 is a flowchart of a wafer level packaging method for a passive device integrated filter according to an embodiment of the present invention. Referring to fig. 7, the method for wafer level packaging of a filter integrated with passive devices includes:

and S10, providing a wafer substrate, wherein a filter structure is formed on one side of the wafer substrate, and the filter structure comprises electrodes and an interdigital transduction structure.

S11, forming a packaging insulating layer and a metal passive device layer on one side of the filter structure far away from the wafer substrate; the packaging insulating layer is positioned on one side of the filter structure far away from the wafer substrate; the packaging insulating layer covers the filter structure, completely or incompletely exposes the electrode, and forms a closed accommodating cavity with the wafer substrate in an enclosing way; the interdigital transduction structure is positioned in the accommodating cavity; the metal passive device layer is positioned in the packaging insulating layer and electrically contacted with the electrode; the metal passive device layer includes a plurality of connection terminals, and the encapsulation insulating layer completely or incompletely exposes the connection terminals.

The filter wafer level packaging method of the integrated passive device and the filter wafer level packaging structure of the integrated passive device provided by the embodiment of the invention belong to the same invention concept, the same technical effect can be realized by the two, and repeated contents are not repeated here.

Fig. 8 is a flowchart of another method for wafer-level packaging of a filter integrated with a passive device according to an embodiment of the present invention. Referring to fig. 8, on the basis of the foregoing embodiments, optionally, the step S11 of forming a package insulating layer and a metal passive device layer on a side of the filter structure away from the wafer substrate includes:

s110, forming a first dry film layer on one side, far away from the wafer substrate, of the filter structure by adopting a spraying process or a laminating process, wherein the first dry film layer covers the filter structure; and etching the first dry film layer by adopting a photoetching process to form a first packaging insulating layer, wherein the first packaging insulating layer completely or incompletely exposes the electrode and is not contacted with the interdigital transducing structure.

For example, fig. 9 is a structural diagram involved in the implementation of a wafer level packaging method for a filter integrated with passive devices according to an embodiment of the present invention, and referring to fig. 9, the first packaging insulation layer 301 does not completely expose the electrodes 21 and the interdigital transducing structures 22 do not contact.

S111, forming a second dry film layer on one side, far away from the wafer substrate, of the first packaging insulating layer by adopting a laminating process, wherein the second dry film layer covers the first packaging insulating layer; and etching the second dry film layer by adopting a photoetching process to form a second packaging insulating layer, wherein the second packaging insulating layer completely or incompletely exposes the electrode and encloses a containing cavity with the wafer substrate, and the containing cavity is not contacted with the interdigital transducing structure.

For example, fig. 10 is a structural diagram involved in implementation of another method for packaging a passive integrated device at a wafer level, which is provided by an embodiment of the present invention, and referring to fig. 10, a second package insulation layer 302 does not completely expose an electrode 21 and encloses a receiving cavity 31 with a wafer substrate 10, an interdigital transducer structure 22 is located in the receiving cavity 31, and the receiving cavity 31 is not in contact with the interdigital transducer structure 22.

S112, forming a metal seed layer and an electroplating metal layer on one side, far away from the wafer substrate, of the second packaging insulating layer in sequence by adopting a physical vapor deposition process and an electroplating process, wherein the electroplating metal layer covers the second packaging insulating layer and is in electrical contact with the electrode; and etching the electroplated metal layer by adopting a photoetching process to form a metal passive device layer, wherein the metal passive device layer comprises a plurality of passive device patterns and a plurality of connecting terminals, and the passive device patterns and the connecting terminals are integrally formed.

Illustratively, a copper (Cu) seed layer is sputtered on the surface of the second package insulating layer 302 by using a Physical Vapor Deposition (PVD) process, and then an electroplated copper layer is formed on the surface of the copper seed layer by using an electroplated copper process, where the electroplated copper layer is electrically contacted with the electrode 21 to achieve direct electrical connection with the electrode 21 and lead out the electrode 21, and then the electroplated copper layer is etched by using a photolithography process, such as a CuTi etching process, to etch the passive device pattern 42 and the connection terminal 41, so as to form the metal passive device layer 40. Fig. 11 is a structural diagram involved in the implementation of another method for packaging a passive device integrated on a wafer level filter according to an embodiment of the present invention, and referring to fig. 11, a metal passive device layer 40 is electrically connected to an electrode 21, so as to directly electrically connect to the electrode 21 and lead out the electrode 21.

S113, forming a third dry film layer on one side, far away from the second packaging insulating layer, of the metal passive device layer by adopting a spraying process, wherein the third dry film layer covers the metal passive device layer; and etching the third dry film layer by adopting a photoetching process to form a third packaging insulating layer, wherein the third packaging insulating layer completely or incompletely exposes the connecting terminal. Here, referring to fig. 2, the third encapsulation insulating layer 303 is formed using a semiconductor spray process, and the third encapsulation insulating layer 303 does not completely expose the connection terminal 41.

S114, forming a metal rewiring layer; the metal rewiring layer is positioned on one side of the packaging insulating layer, which is far away from the wafer substrate, and covers the packaging insulating layer; the metal rewiring layer comprises a plurality of bonding pads; the bonding pads are in electrical contact with the connecting terminals and correspond to the connecting terminals one to one. Here, referring to fig. 5, the electrode 21 on the surface of the second package insulating layer 302 is led out to the surface of the third package insulating layer 303 and rewired on the surface of the third package insulating layer 303 by using a physical vapor deposition process and an etching process, and the surface of the rewired electrode 21 is plated with a nickel-gold protective layer by using an electroless nickel-gold plating process to form the metal rewiring layer 50.

S115, forming a solder mask layer and a solder ball in sequence; the solder mask layer is positioned on one side of the metal rewiring layer away from the packaging insulating layer and covers the metal rewiring layer; the solder mask layer completely or incompletely exposes the pad; the solder balls are positioned on one side of the welding pad far away from the welding resistance layer, and the solder balls are in electric contact with the welding pad and are in one-to-one correspondence with the welding pad. Here, referring to fig. 6, the solder resist layer 60 may be formed using a photolithography process.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.