阅读说明：本技术 低导通电阻可重构计算芯片用晶体管及制造方法 (Transistor for low-on-resistance reconfigurable computing chip and manufacturing method ) 是由 靳晓诗 张寿强 于 2021-08-31 设计创作，主要内容包括：本发明公开了低导通电阻可重构计算芯片用晶体管及制造方法,通过对半导体薄膜两侧同时形成正负掺杂,当可重构电极对重构电荷存储层编程写入正电荷时,半导体两侧形成电子堆积区,使低导通电阻可重构计算芯片用晶体管工作在导带电子导通模式,当可重构电极对重构电荷存储层编程写入负电荷时,半导体两侧形成空穴堆积区,使低导通电阻可重构计算芯片用晶体管工作在价带空穴导通模式,实现对低导通电阻可重构计算芯片用晶体管导电类型的可编程操作。本发明同时公开了一种兼容于CMOS集成电路工艺技术的低导通电阻可重构计算芯片用晶体管的制造方法。(The invention discloses a transistor for a low-conduction-resistance reconfigurable computing chip and a manufacturing method thereof.A positive doping and a negative doping are simultaneously formed on two sides of a semiconductor film, when a reconfigurable electrode pair reconfigurable charge storage layer is programmed and written with positive charges, an electron accumulation area is formed on two sides of the semiconductor, so that the transistor for the low-conduction-resistance reconfigurable computing chip works in a conduction band electron conduction mode, when the reconfigurable electrode pair reconfigurable charge storage layer is programmed and written with negative charges, a hole accumulation area is formed on two sides of the semiconductor, so that the transistor for the low-conduction-resistance reconfigurable computing chip works in a valence band hole conduction mode, and the programmable operation of the conduction type of the transistor for the low-conduction-resistance reconfigurable computing chip is realized. The invention also discloses a manufacturing method of the transistor for the low-on-resistance reconfigurable computing chip, which is compatible with the CMOS integrated circuit process technology.)

1. A low on-resistance reconfigurable transistor for a computing chip includes a substrate (1), characterized in that: a buried oxide layer (2) is arranged above the substrate (1), the buried oxide layer (2) is an insulating material layer, and intrinsic silicon (3), a negative doped source region (4), a positive doped source region (5), a negative doped drain region (6), a positive doped drain region (7), an insulating dielectric layer (8), a reconfigurable tunneling insulating layer (9), a gate electrode insulating layer (10), a reconfigurable charge storage layer (11) and a gate electrode (12) are arranged above the buried oxide layer (2); the intrinsic silicon (3) is a semiconductor material, and the upper surface and the central parts of the front and rear side surfaces of the intrinsic silicon (3) are in contact with the gate electrode insulating layers (10);

the left and right sides of the upper surface and the front and back side surfaces of the intrinsic silicon (3) are in contact with the reconfigurable tunneling insulating layer (9); the upper surface and the front and back side surfaces of the intrinsic silicon (3) are positioned between the gate electrode insulating layer (10) and the reconfigurable tunneling insulating layer (9) and are in mutual contact with the insulating medium layer (8);

the negative doping source region (4) and the positive doping source region (5) are semiconductor regions doped with V group elements and III group elements respectively; the negative doped source region (4) and the positive doped source region (5) are simultaneously positioned on the left side of the intrinsic silicon (3) and are in mutual contact with the left side surface of the intrinsic silicon (3); the front side surface of the negative doping source region (4) and the back side surface of the positive doping source region (5) are in contact with the insulating medium layer (8); the rear side surface of the negative doping source region (4) and the front side surface of the positive doping source region (5) are contacted with each other;

the left sides of the upper surfaces of the negative doping source region (4) and the positive doping source region (5) are mutually contacted with the source electrode (15) to form a reverse blocking type ohmic contact; the right sides of the upper surfaces of the negative doping source region (4) and the positive doping source region (5) are mutually contacted with the insulating medium layer (8);

the negative doped drain region (6) and the positive doped drain region (7) are semiconductor regions doped with V group elements and III group elements respectively; the negative doped drain region (6) and the positive doped drain region (7) are simultaneously positioned on the right side of the intrinsic silicon (3) and are in contact with the right side surface of the intrinsic silicon (3); the front side surface of the negative doped drain region (6) and the back side surface of the positive doped drain region (7) are in contact with the insulating medium layer (8); the rear side surface of the negative doped drain region (6) and the front side surface of the positive doped drain region (7) are in contact with each other;

the right sides of the upper surfaces of the negative doped drain region (6) and the positive doped drain region (7) are in mutual contact with the drain electrode (16) to form a reverse blocking type ohmic contact; the left sides of the upper surfaces of the negative doped drain region (6) and the positive doped drain region (7) are mutually contacted with the insulating medium layer (8);

the insulating medium layer (8) is made of an insulating medium material;

the reconfigurable tunneling insulating layer (9) is an insulating dielectric material with the thickness lower than 3 nanometers; the upper surface and the front and back side surfaces of the reconfigurable tunneling insulating layer (9) are in contact with the lower surfaces of the left side and the right side of the reconfigurable charge storage layer (11); the reconfigurable charge storage layer (11) is one of polycrystalline silicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide;

the gate electrode insulating layer (10) is made of an insulating dielectric material; the upper surface and front and rear side surfaces of the gate electrode insulating layer (10) are in contact with the gate electrode (12);

the upper surface of the reconfigurable charge storage layer (11) is in contact with the lower surface of the reconfigurable electrode insulating layer (13); the outer surface and the inner surface of the left side and the right side of the reconfigurable charge storage layer (11) are in contact with the insulating medium layer (8); the reconfigurable charge storage layer (11) is in an inverted U shape and is positioned above the reconfigurable tunneling insulating layer (9); the reconfigurable charge storage layer (11) is insulated and isolated from the outside through the insulating medium layer (8) and the reconfigurable tunneling insulating layer (9);

the gate electrode (12) is one of polysilicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide; the outer surfaces of the upper surface and the left and right sides of the gate electrode (12) are mutually contacted with the insulating medium layer (8);

the reconfigurable electrode insulating layer (13) is made of an insulating dielectric material; the upper surface of the reconfigurable electrode insulating layer (13) is in contact with the reconfigurable electrode (14); the thickness of the reconfigurable electrode insulating layer (13) is larger than that of the reconfigurable tunneling insulating layer (9);

the reconfigurable electrode (14) is one of polycrystalline silicon, metal, alloy or metal silicide;

the source electrode (15) is one of polysilicon, metal, alloy or metal silicide; the source electrode (15) is insulated and isolated from the reconfigurable charge storage layer (11) and the reconfigurable electrode (14) through an insulating medium layer (8);

the drain electrode (16) is one of polysilicon, metal, alloy or metal silicide; the drain electrode (16) is insulated and isolated from the reconfigurable charge storage layer (11) and the reconfigurable electrode (14) through the insulating medium layer (8).

2. A method of using a transistor for a low on-resistance reconfigurable computing chip as claimed in claim 1, wherein:

positive voltage is applied to the reconfigurable electrode (14) relative to a source electrode (15) and a drain electrode (16), a reconfigurable tunneling insulating layer (9) is utilized to generate an insulating layer tunneling effect under high field intensity, negative charges are written into the reconfigurable charge storage layer (11), the reconfigurable charge storage layer (11) generates a negative electric field effect on the left end and the right end of intrinsic silicon (3), hole accumulation layers are formed on the left end and the right end of the intrinsic silicon (3), and P-type mode programming of the transistor for the low-on-resistance reconfigurable computing chip is completed;

the reconfigurable electrode (14) is applied with negative voltage relative to the source electrode (15) and the drain electrode (16), the reconfigurable tunneling insulating layer (9) is utilized to generate an insulating layer tunneling effect under high field intensity, positive charges are written into the reconfigurable charge storage layer (11), the reconfigurable charge storage layer (11) generates a positive electric field effect on the left end and the right end of the intrinsic silicon (3), electron accumulation layers are formed on the left end and the right end of the intrinsic silicon (3), and N-type mode programming of the transistor for the low-conduction-resistance reconfigurable computing chip is completed.

3. A method of manufacturing a transistor for a low on-resistance reconfigurable computing chip as claimed in claim 1, wherein:

the method comprises the following steps: providing an SOI wafer, wherein the lowest part of the SOI wafer is a substrate (1), a buried oxide layer (2) is arranged on the substrate, the upper surface of the buried oxide layer (2) is a semiconductor film, and intrinsic silicon (3) is preliminarily formed through photoetching, etching and deposition processes;

step two: respectively forming a negative doping source region (4), a positive doping source region (5), a negative doping drain region (6) and a positive doping drain region (7) by an ion implantation process;

step three: depositing an insulating medium layer on the basis of the second step by a deposition process, flattening the insulating medium layer until the intrinsic silicon (3) is exposed, preliminarily forming an insulating medium layer (8), etching the insulating medium layer at the central parts of the left side and the right side of the front surface and the rear surface of the intrinsic silicon (3) by an etching process until the buried oxide layer (2) is exposed, and further forming the insulating medium layer (8);

step four: depositing an insulating medium on the basis of the third step through a deposition process, and then performing planarization treatment until the intrinsic silicon (3) is exposed to preliminarily form a reconfigurable tunneling insulating layer (9) and a gate electrode insulating layer (10);

step five: etching a part of the region formed in the fourth step and positioned in front of the reconfigurable tunneling insulating layer (9) formed in the front part of the semiconductor thin film (3) to expose the buried oxide layer (2) through an etching process on the basis of the fourth step; etching off the front part area of the gate electrode insulating layer (10) at the part in front of the semiconductor film (3) formed in the fourth step until the buried oxide layer (2) is exposed; etching a part of the area formed in the fourth step and positioned behind the reconfigurable tunneling insulating layer (9) formed and positioned at the rear part of the semiconductor film (3) until the buried oxide layer (2) is exposed; etching off a part of the region formed in the fourth step and positioned behind the gate electrode insulating layer (10) at the rear part of the semiconductor film (3) until the buried oxide layer (2) is exposed;

step six: depositing one of metal, alloy, polycrystalline silicon or metal silicide on the basis of the fifth step through a deposition process, and then performing planarization treatment until the semiconductor film (3) is exposed to preliminarily form a reconfigurable charge storage layer (11) and a gate electrode (12);

step seven: depositing an insulating layer on the basis of the sixth step by a deposition process, etching the central part and the central parts on the left side and the right side of the insulating layer by an etching process until the semiconductor film (3) is exposed, depositing the insulating layer by the deposition process, and flattening until the insulating dielectric layer (8) is exposed to further form a reconfigurable tunneling insulating layer (9) and a gate electrode insulating layer (10); etching the reconfigurable charge storage layer (11) which is initially formed in the sixth step from the front area of the reconfigurable tunneling insulating layer (9) to the exposure step and the reconfigurable charge storage layer (11) which is initially formed in the sixth step from the rear area of the reconfigurable tunneling insulating layer (9) to the exposure step by an etching process; etching away the region in front of the gate electrode insulating layer (10) to expose the gate electrode (12) preliminarily formed in the step six and the region below the gate electrode insulating layer (10) to expose the gate electrode (12) preliminarily formed in the step six; depositing one of metal, alloy, polycrystalline silicon or metal silicide by a deposition process, and further forming a reconfigurable charge storage layer (11) and a gate electrode (12) by planarization processing until an insulating dielectric layer (8) is exposed;

step eight: depositing an insulating layer on the basis of the seventh step by a deposition process, etching the insulating layer above the reconfigurable tunneling insulating layer (9), the gate electrode insulating layer (10) and the reconfigurable charge storage layer (11) and the gate electrode (12) generated in the seventh step by an etching process after planarization to further form an insulating dielectric layer (8), depositing one of metal, alloy, polysilicon or metal silicide by the deposition process, planarizing to expose the insulating dielectric layer (8), and further forming the reconfigurable charge storage layer (11) and the gate electrode (12);

step nine: depositing an insulating layer on the basis of the eighth step by a deposition process, etching the insulating layer above the reconfigurable charge storage layer (11) generated in the eighth step by an etching process after planarization to further form an insulating dielectric layer (8), depositing one of metal, alloy, polysilicon or metal silicide by the deposition process, and planarizing until the insulating dielectric layer (8) is exposed to further form the reconfigurable charge storage layer (11);

step ten: depositing an insulating layer on the basis of the ninth step through a deposition process, etching the insulating layer above the reconfigurable charge storage layer (11) generated in the ninth step and between two side parts of the reconfigurable charge storage layer (11) through an etching process after planarization to further form an insulating dielectric layer (8), depositing one of metal, alloy, polycrystalline silicon or metal silicide through the deposition process, and planarizing until the insulating dielectric layer (8) is exposed to further form the reconfigurable charge storage layer (11);

step eleven: depositing an insulating layer on the basis of the tenth step through a deposition process, etching the insulating layer above the reconfigurable charge storage layer (11) generated in the tenth step through an etching process after planarization to further form an insulating dielectric layer (8), depositing the insulating layer through the deposition process, and planarizing until the insulating dielectric layer (8) is exposed to form a reconfigurable electrode insulating layer (13); depositing an insulating layer by a deposition process, etching the insulating layer above the reconfigurable electrode insulating layer (13) by an etching process after planarization to further form an insulating dielectric layer (8), depositing one of metal, alloy, polysilicon or metal silicide by the deposition process, and planarizing until the insulating dielectric layer (8) is exposed to form a reconfigurable electrode (14);

step twelve: etching off the middle area of the left side of the insulating dielectric layer (8) to expose the upper surfaces of the left side partial areas of the negative doping source area (4) and the positive doping source area (5) through an etching process on the basis of the eleventh step; etching the middle part area of the right side of the insulating medium layer (8) until the upper surfaces of the right side part areas of the negative doped drain area (6) and the positive doped drain area (7) are exposed; and then one of metal, alloy or metal silicide is deposited through a deposition process, and then planarization treatment is carried out until the upper surface of the isolation insulating medium (8) is exposed, so that a source electrode (15) and a drain electrode (16) are formed.

Technical Field

The invention belongs to the technical field of CMOS integrated circuits, and relates to a transistor for a low-on resistance reconfigurable computing chip and a manufacturing method, wherein the transistor is suitable for the design and manufacturing technology of a high-integration low-power-consumption CMOS integrated circuit.

Background

Depending on the progress of the process, the performance of processors under conventional computing architectures may be continually improved enough to meet the rapidly growing market demands. As moore's law becomes more and more gradual, the way of improving performance by relying on the process is difficult to continue, and exploring a new architecture becomes another way of improving the performance of the processor. Reconfigurable computing architectures are gaining increasing attention. In 2015, reconfigurable Computing (CGRA) is applied to AI computing and neural network computing scenes, a series of AI chips are designed, and in the same year, international semiconductor technology roadmap introduces CGRA as the most promising future non-Von Neumann architecture. In 2017, the department of advanced research and development (ERI) of the United states department of defense has introduced an electronic renaming program, and emphasizes the software-defined hardware architecture, which is a reconfigurable computing architecture with programmability for both software and hardware. From 2016, a plurality of international major companies actively introduce reconfigurable computing technology, and new products are planned to be launched to the market. The CGRA framework has natural expandability, and the characteristics of high energy efficiency and flexibility can be very suitable for the cloud market through calculation capacity expansion. The current reconfigurable computing allows the design of the module level, the logic gate level and even the transistor level, for the design of the transistor level, the minimum unit in the reconfigurable computing architecture is the MOSFET field effect transistor, the conduction type, namely the N type or the P type, is determined when the chip process is completed, for the designer of the reconfigurable computing architecture, the proportion of the two types of transistors required may have great difference, so the transistor with the reconfigurable conduction type is manufactured, which has important significance for improving the utilization efficiency of the transistor level of the reconfigurable computing architecture chip, some reconfigurable transistors based on the source-drain Schottky barrier are proposed, the conduction type can be defined by a programming gate, however, the reconfigurable transistor based on the Schottky barrier has larger source-drain parasitic resistance, and is difficult to generate higher current when being conducted, that is, the on-resistance is high when the switch is turned on, which is not favorable for the transmission of electrical signals.

Disclosure of Invention

Object of the Invention

Aiming at the problems that the source-drain parasitic resistance is large, the on-resistance is high, high current is difficult to generate during conduction, and electric signal transmission is not facilitated, the transistor for the low-on-resistance reconfigurable computing chip and the manufacturing method are developed.

Technical scheme

The transistor for the low-on-resistance reconfigurable computing chip comprises a substrate, wherein a buried oxide layer is arranged above the substrate, the buried oxide layer is an insulating material layer, and intrinsic silicon, a negative doped source region, a positive doped source region, a negative doped drain region, a positive doped drain region, an insulating dielectric layer, a reconfigurable tunneling insulating layer, a gate electrode insulating layer, a reconfigurable charge storage layer and a gate electrode are arranged above the buried oxide layer; the intrinsic silicon is a semiconductor material, and the central parts of the upper surface and the front and back side surfaces of the intrinsic silicon are in contact with the gate electrode insulating layer; the left side and the right side of the upper surface and the front side and the back side of the intrinsic silicon are in mutual contact with the reconfigurable tunneling insulating layer; the upper surface and the front and back side surfaces of the intrinsic silicon are positioned between the gate electrode insulating layer and the reconfigurable tunneling insulating layer and are in mutual contact with the insulating medium layer; the negative doping source region and the positive doping source region are semiconductor regions doped with V group elements and III group elements respectively; the negative doping source region and the positive doping source region are simultaneously positioned on the left side of the intrinsic silicon and are in mutual contact with the left surface of the intrinsic silicon; the front side surface of the negative doping source region and the back side surface of the positive doping source region are in mutual contact with the insulating medium layer; the rear side surface of the negative doping source region and the front side surface of the positive doping source region are contacted with each other; the left sides of the upper surfaces of the negative doping source region and the positive doping source region are mutually contacted with the source electrode to form a reverse blocking type ohmic contact; the right sides of the upper surfaces of the negative doping source region and the positive doping source region are mutually contacted with the insulating medium layer; the negative doped drain region and the positive doped drain region are semiconductor regions doped with V group elements and III group elements respectively; the negative doped drain region and the positive doped drain region are simultaneously positioned on the right side of the intrinsic silicon and are in contact with the right side surface of the intrinsic silicon; the front side surface of the negative doped drain region and the back side surface of the positive doped drain region are in contact with the insulating medium layer; the rear side surface of the negative doped drain region and the front side surface of the positive doped drain region are in contact with each other; the right sides of the upper surfaces of the negative doped drain region and the positive doped drain region are in mutual contact with the drain electrode to form a reverse blocking type ohmic contact; the left sides of the upper surfaces of the negative doped drain region and the positive doped drain region are in mutual contact with the insulating medium layer; the insulating medium layer is made of insulating medium materials; the reconfigurable tunneling insulating layer is an insulating dielectric material with the thickness lower than 3 nanometers; the upper surface and the front and back side surfaces of the reconfigurable tunneling insulating layer are in mutual contact with the lower surfaces of the left side and the right side of the reconfigurable charge storage layer; the reconfigurable charge storage layer is one of polysilicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide; the gate electrode insulating layer is made of an insulating dielectric material; the upper surface and front and rear side surfaces of the gate electrode insulating layer are in contact with the gate electrode; the upper surface of the reconfigurable charge storage layer is in contact with the lower surface of the reconfigurable electrode insulating layer; the outer surface and the inner surface of the left side and the right side of the reconfigurable charge storage layer are in contact with the insulating medium layer; the reconfigurable charge storage layer is in an inverted U shape and is positioned above the reconfigurable tunneling insulating layer; the reconfigurable charge storage layer is insulated and isolated from the outside through the insulating medium layer and the reconfigurable tunneling insulating layer; the gate electrode is one of polysilicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide; the outer surfaces of the left side and the right side of the upper surface of the gate electrode are in mutual contact with the insulating medium layer; the reconfigurable electrode insulating layer is made of an insulating dielectric material; the upper surface of the reconfigurable electrode insulating layer is in contact with the reconfigurable electrode; the thickness of the reconfigurable electrode insulating layer is larger than that of the reconfigurable tunneling insulating layer; the reconfigurable electrode is one of polysilicon, metal, alloy or metal silicide; the source electrode is one of polysilicon, metal, alloy or metal silicide; the source electrode is insulated and isolated from the reconfigurable charge storage layer and the reconfigurable electrode through the insulating medium layer; the leakage electrode is one of polysilicon, metal, alloy or metal silicide; the drain electrode is insulated and isolated from the reconfigurable charge storage layer and the reconfigurable electrode through the insulating medium layer.

Advantages and effects

1. Low on-resistance:

the transistor for the low-on-resistance reconfigurable computing chip and the manufacturing method thereof have the on-resistance equivalent to that of an N-type transistor or a P-type transistor based on a CMOS basic circuit. Compared with a reconfigurable transistor based on a source drain Schottky barrier, the transistor for the low-on-resistance reconfigurable computing chip provided by the invention has the advantages that when the transistor works in an N-type mode and a P-type mode, the on-resistance is far smaller than that of the reconfigurable transistor based on the source drain Schottky barrier.

2. Conductive type non-volatile reconfiguration:

the conduction type of the transistor for the low-on-resistance reconfigurable computing chip can be subjected to nonvolatile reconfiguration in a mode that positive charges or negative charges are written into the reconfigurable charge storage layer through the reconfigurable electrode pair.

Drawings

FIG. 1 is a top view of a transistor for a low on-resistance reconfigurable computing chip in accordance with the present invention;

FIG. 2 is a cross-sectional view of the present invention taken along the dashed line A of FIG. 1;

FIG. 3 is a cross-sectional view of the present invention taken along the line B of FIG. 1;

FIG. 4 is a cross-sectional view of the present invention taken along the dashed line C of FIG. 1;

FIG. 5 is a cross-sectional view of the present invention taken along the dashed line D in FIG. 1;

FIG. 6 is a top view of step one of the present invention;

FIG. 7 is a cross-sectional view along dotted line A of step one of the present invention;

FIG. 8 is a top view of step two of the present invention;

FIG. 9 is a cross-sectional view along dotted line A of step two of the present invention;

FIG. 10 is a cross-sectional view along dashed line B of step two of the present invention;

FIG. 11 is a cross-sectional view along dotted line C of step two of the present invention;

FIG. 12 is a cross-sectional view along dashed line D of step two of the present invention;

FIG. 13 is a cross-sectional view along dashed line E of step two of the present invention;

FIG. 14 is a top view of step three of the present invention;

FIG. 15 is a cross-sectional view along dotted line A of step three of the present invention;

FIG. 16 is a cross-sectional view taken along dotted line B of step three of the present invention;

FIG. 17 is a cross-sectional view along dotted line C of step three of the present invention;

FIG. 18 is a top view of step four of the present invention;

FIG. 19 is a cross-sectional view along dotted line A of step four of the present invention;

FIG. 20 is a cross-sectional view taken along dashed line B of step four of the present invention;

FIG. 21 is a cross-sectional view along dotted line C of step four of the present invention;

FIG. 22 is a top view of step five of the present invention;

FIG. 23 is a cross-sectional view taken along dotted line A of step five of the present invention;

FIG. 24 is a cross-sectional view taken along dashed line B of step five of the present invention;

FIG. 25 is a cross-sectional view taken along dashed line C of step five of the present invention;

FIG. 26 is a top view of step six of the present invention;

FIG. 27 is a cross-sectional view along dashed line A of step six of the present invention;

FIG. 28 is a cross-sectional view taken along dashed line B of step six of the present invention;

FIG. 29 is a cross-sectional view along dashed line C of step six of the present invention;

FIG. 30 is a top view of step seven of the present invention;

FIG. 31 is a cross-sectional view taken along dashed line A of step seven of the present invention;

FIG. 32 is a cross-sectional view taken along dashed line B of step seven of the present invention;

FIG. 33 is a cross-sectional view along dashed line C of step seven of the present invention;

FIG. 34 is a cross-sectional view taken along dashed line D of step seven of the present invention;

FIG. 35 is a cross-sectional view along dashed line E of step seven of the present invention;

FIG. 36 is a top view of step eight of the present invention;

FIG. 37 is a cross-sectional view taken along dashed line A of step eight of the present invention;

FIG. 38 is a cross-sectional view taken along dashed line B of step eight of the present invention;

FIG. 39 is a cross-sectional view along dashed line C of step eight of the present invention;

FIG. 40 is a cross-sectional view taken along dashed line D of step eight of the present invention;

FIG. 41 is a cross-sectional view along dashed line E of step eight of the present invention;

FIG. 42 is a top view of step nine of the present invention;

FIG. 43 is a cross-sectional view along dotted line A of step nine of the present invention;

FIG. 44 is a cross-sectional view taken along dashed line B of step nine of the present invention;

FIG. 45 is a cross-sectional view along dotted line C of step nine of the present invention;

FIG. 46 is a cross-sectional view taken along dashed line D of step nine of the present invention;

FIG. 47 is a cross-sectional view along dashed line E of step nine of the present invention;

FIG. 48 is a top view of step ten of the present invention;

FIG. 49 is a cross-sectional view along dotted line A of step ten of the present invention;

FIG. 50 is a cross-sectional view taken along dashed line B of step ten of the present invention;

FIG. 51 is a cross-sectional view along dashed line C of step ten of the present invention;

FIG. 52 is a top view of step eleven of the present invention;

FIG. 53 is a cross-sectional view along dashed line A of step eleven of the present invention;

FIG. 54 is a cross-sectional view taken along dashed line B of step eleven of the present invention;

FIG. 55 is a cross-sectional view along dashed line C of step eleven of the present invention;

reference numerals: 1. a substrate; 2. burying the oxide layer; 3. intrinsic silicon; 4. a negatively doped source region; 5. a positively doped source region; 6. a negatively doped drain region; 7. a positively doped drain region; 8. an insulating dielectric layer; 9. a reconfigurable tunneling insulating layer; 10. a gate electrode insulating layer; 11. a reconfigurable charge storage layer; 12. a gate electrode; 13. a reconfigurable electrode insulating layer; 14. a reconfigurable electrode; 15. a source electrode; 16. and a drain electrode.

Detailed Description

The invention is further described below with reference to the accompanying drawings:

examples

With reference to fig. 1-5, the transistor for the low on-resistance reconfigurable computing chip comprises a substrate 1, a buried oxide layer 2 is arranged above the substrate 1, the buried oxide layer 2 is an insulating material layer, and intrinsic silicon 3, a negatively doped source region 4, a positively doped source region 5, a negatively doped drain region 6, a positively doped drain region 7, an insulating medium layer 8, a reconfigurable tunneling insulating layer 9, a gate electrode insulating layer 10, a reconfigurable charge storage layer 11 and a gate electrode 12 are arranged above the buried oxide layer 2; the intrinsic silicon 3 is a semiconductor material, and the upper surface and the central portions of the front and rear side surfaces of the intrinsic silicon 3 are in contact with the gate electrode insulating layer 10; the left and right sides of the upper surface and the front and back side surfaces of the intrinsic silicon 3 are in contact with the reconfigurable tunneling insulating layer 9; the upper surface and the front and back side surfaces of the intrinsic silicon 3 between the gate electrode insulating layer 10 and the reconfigurable tunneling insulating layer 9 are in contact with the insulating dielectric layer 8; the negative doping source region 4 and the positive doping source region 5 are semiconductor regions doped with group V elements and group III elements, respectively; the negative doping source region 4 and the positive doping source region 5 are simultaneously positioned at the left side of the intrinsic silicon 3 and are in contact with the left surface of the intrinsic silicon 3; the front side surface of the negative doping source region 4 and the back side surface of the positive doping source region 5 are in contact with the insulating medium layer 8; the rear-side surface of the negatively doped source region 4 and the front-side surface of the positively doped source region 5 are in contact with each other; the left sides of the upper surfaces of the negative doping source region 4 and the positive doping source region 5 are mutually contacted with the source electrode 15 to form a reverse blocking type ohmic contact; the right sides of the upper surfaces of the negative doping source region 4 and the positive doping source region 5 are mutually contacted with the insulating medium layer 8; the negative doped drain region 6 and the positive doped drain region 7 are semiconductor regions doped with group V elements and group III elements, respectively; the negative doped drain region 6 and the positive doped drain region 7 are simultaneously positioned at the right side of the intrinsic silicon 3 and are in contact with the right side surface of the intrinsic silicon 3; the front side surface of the negative doped drain region 6 and the back side surface of the positive doped drain region 7 are in contact with the insulating medium layer 8; the rear side surface of the negatively doped drain region 6 and the front side surface of the positively doped drain region 7 are in contact with each other; the right sides of the upper surfaces of the negative doped drain region 6 and the positive doped drain region 7 are in contact with the drain electrode 16 to form a reverse blocking type ohmic contact; the left sides of the upper surfaces of the negative doped drain region 6 and the positive doped drain region 7 are in contact with the insulating medium layer 8; the insulating medium layer 8 is made of insulating medium materials; the reconfigurable tunneling insulating layer 9 is an insulating dielectric material with the thickness lower than 3 nanometers; the upper surface and the front and back side surfaces of the reconfigurable tunneling insulating layer 9 are in contact with the lower surfaces of the left side and the right side of the reconfigurable charge storage layer 11; the reconfigurable charge storage layer 11 is one of polycrystalline silicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide; the gate electrode insulating layer 10 is an insulating dielectric material; the upper surface and front and rear side surfaces of the gate electrode insulating layer 10 and the gate electrode 12 are in contact with each other; the upper surface of the reconfigurable charge storage layer 11 and the lower surface of the reconfigurable electrode insulating layer 13 are in contact with each other; the outer surface and the inner surface of the left side and the right side of the reconfigurable charge storage layer 11 are in contact with the insulating medium layer 8; the reconfigurable charge storage layer 11 is in an inverted U shape and is positioned above the reconfigurable tunneling insulating layer 9; the reconfigurable charge storage layer 11 is insulated and isolated from the outside through the insulating medium layer 8 and the reconfigurable tunneling insulating layer 9; the gate electrode 12 is one of polysilicon, silicon nitride, aluminum oxide, metal, alloy or metal silicide; the upper surface, the left outer surface and the right outer surface of the gate electrode 12 are mutually contacted with the insulating medium layer 8; the reconfigurable electrode insulating layer 13 is made of an insulating dielectric material; the upper surface of the reconfigurable electrode insulating layer 13 and the reconfigurable electrode 14 are in contact with each other; the thickness of the reconfigurable electrode insulating layer 13 is larger than that of the reconfigurable tunneling insulating layer 9; the reconfigurable electrode 14 is one of polysilicon, metal, alloy or metal silicide; the source electrode 15 is one of polysilicon, metal, alloy or metal silicide; the source electrode 15 is insulated and isolated from the reconfigurable charge storage layer 11 and the reconfigurable electrode 14 through the insulating medium layer 8; the drain electrode 16 is one of polysilicon, metal, alloy or metal silicide; the drain electrode 16 is insulated and isolated from the reconfigurable charge storage layer 11 and the reconfigurable electrode 14 through the insulating medium layer 8.

With reference to fig. 1 to 5, a method for using a transistor for a low on-resistance reconfigurable computing chip:

applying positive voltage to the reconfigurable electrode 14 relative to the source electrode 15 and the drain electrode 16, utilizing the reconfigurable tunneling insulating layer 9 to generate an insulating layer tunneling effect under high field intensity, writing negative charges into the reconfigurable charge storage layer 11, enabling the reconfigurable charge storage layer 11 to generate a negative electric field effect on the left and right ends of the intrinsic silicon 3, forming hole accumulation layers on the left and right ends of the intrinsic silicon 3, and completing P-type mode programming of the transistor for the low-on-resistance reconfigurable computing chip;

after the P-type mode programming of the transistor for the low-on-resistance reconfigurable computing chip is completed, a negative voltage is applied to the gate electrode 12, a hole channel is formed in the intrinsic silicon 3, so that electrons can flow out from the drain electrode 16, the right region of the intrinsic silicon 3 controlled by the reconfigurable charge storage layer 11, the central region of the intrinsic silicon 3 controlled by the gate electrode 12, the left region of the intrinsic silicon 3 controlled by the reconfigurable charge storage layer 11, the positively-doped source region 5 and the source electrode 15, and the transistor for the low-on-resistance reconfigurable computing chip is in a P-type conducting state; after the N-type mode programming of the transistor for the low on-resistance reconfigurable computing chip is completed, a positive voltage is applied to the gate electrode 12, so that the transistor for the low on-resistance reconfigurable computing chip is in a P-type cut-off state;

applying negative voltage to the reconfigurable electrode 14 relative to the source electrode 15 and the drain electrode 16, generating an insulating layer tunneling effect under high field intensity by using the reconfigurable tunneling insulating layer 9, writing positive charges into the reconfigurable charge storage layer 11, enabling the reconfigurable charge storage layer 11 to generate a positive electric field effect on the left and right ends of the intrinsic silicon 3, forming an electronic accumulation layer on the left and right ends of the intrinsic silicon 3, and completing N-type mode programming of the transistor for the low-on-resistance reconfigurable computing chip;

after the N-type mode programming of the transistor for the low-on-resistance reconfigurable computing chip is completed, an electron channel is formed in the intrinsic silicon 3 by applying a positive voltage to the gate electrode 12, so that electrons can flow out from the source electrode 15, the negative doped source region 4, the left region of the intrinsic silicon 3 controlled by the reconfigurable charge storage layer 11, the central region of the intrinsic silicon 3 controlled by the gate electrode 12, the right region of the intrinsic silicon 3 controlled by the reconfigurable charge storage layer 11 and the negative doped drain region 6, and finally the drain electrode 16, so that the transistor for the low-on-resistance reconfigurable computing chip is in an N-type conducting state; after the N-type mode programming of the transistor for the low on-resistance reconfigurable computing chip is finished, applying negative voltage to the gate electrode 12 to enable the transistor for the low on-resistance reconfigurable computing chip to be in an N-type cut-off state;

a method for manufacturing a transistor for a low on-resistance reconfigurable computing chip, comprising the following steps (not limited to the following steps) realized on an SOI wafer substrate:

the method comprises the following steps: with reference to fig. 6-7, providing an SOI wafer, wherein a substrate 1 is disposed at the bottom, a buried oxide layer 2 is disposed on the substrate, and a semiconductor thin film is disposed on the upper surface of the buried oxide layer 2, and initially forming intrinsic silicon 3 by photolithography, etching and deposition processes;

step two: with reference to fig. 8-13, a negatively doped source region 4, a positively doped source region 5, a negatively doped drain region 6 and a positively doped drain region 7 are formed, respectively, by an ion implantation process;

step three: with reference to fig. 14-17, an insulating dielectric layer is deposited on the basis of the second step by a deposition process, then planarization is performed until the intrinsic silicon 3 is exposed, an insulating dielectric layer 8 is preliminarily formed, and then the insulating dielectric layers at the central portions of the left and right sides of the front and rear surfaces of the intrinsic silicon 3 are etched by an etching process until the buried oxide layer 2 is exposed, so as to further form the insulating dielectric layer 8;

step four: with reference to fig. 18-21, depositing an insulating medium on the basis of the third step by a deposition process, and then performing planarization processing until the intrinsic silicon 3 is exposed, thereby preliminarily forming a reconfigurable tunneling insulating layer 9 and a gate electrode insulating layer 10;

step five: with reference to fig. 22-25, on the basis of the fourth step, a portion of the region formed in the fourth step, which is located in front of the reconfigurable tunneling insulating layer 9 formed in the front portion of the semiconductor thin film 3, is etched away by an etching process until the buried oxide layer 2 is exposed; etching off the front part area of the gate electrode insulating layer 10 at the part in front of the semiconductor film 3 formed in the fourth step until the buried oxide layer 2 is exposed; etching a part of the area formed in the fourth step and positioned behind the reconfigurable tunneling insulating layer 9 formed and positioned at the rear part of the semiconductor film 3 until the buried oxide layer 2 is exposed; etching off the partial area behind the gate electrode insulating layer 10 at the rear part of the semiconductor film 3 formed in the fourth step until the buried oxide layer 2 is exposed;

step six: with reference to fig. 26 to 29, a reconfigurable charge storage layer 11 and a gate electrode 12 are preliminarily formed by depositing one of metal, alloy, polysilicon, or metal silicide on the basis of the fifth step through a deposition process, and then performing planarization processing until the semiconductor thin film 3 is exposed;

step seven: with reference to fig. 30 to 35, depositing an insulating layer on the basis of the sixth step by a deposition process, etching away the central part and the central parts on the left and right sides of the insulating layer by an etching process until the semiconductor film 3 is exposed, depositing the insulating layer by the deposition process, and planarizing until the insulating dielectric layer 8 is exposed, thereby further forming a reconfigurable tunneling insulating layer 9 and a gate electrode insulating layer 10; etching the reconfigurable charge storage layer 11 preliminarily formed in the sixth step from the front area of the reconfigurable tunneling insulating layer 9 to the exposure step and the reconfigurable charge storage layer 11 preliminarily formed in the sixth step from the rear area of the reconfigurable tunneling insulating layer 9 to the exposure step by an etching process; etching away the region in front of the gate electrode insulating layer 10 to expose the gate electrode 12 preliminarily formed in the step six and the region below the gate electrode insulating layer 10 to expose the gate electrode 12 preliminarily formed in the step six; depositing one of metal, alloy, polycrystalline silicon or metal silicide by a deposition process, and flattening until the insulating medium layer 8 is exposed to further form a reconfigurable charge storage layer 11 and a gate electrode 12;

step eight: with reference to fig. 36-41, an insulating layer is deposited on the basis of step seven by a deposition process, after planarization, the insulating layer above the reconfigurable tunneling insulating layer 9, the gate electrode insulating layer 10, the reconfigurable charge storage layer 11 and the gate electrode 12 generated in step seven is etched by an etching process, an insulating dielectric layer 8 is further formed, one of metal, alloy, polysilicon or metal silicide is deposited by a deposition process, and the dielectric layer 8 is planarized until the insulating dielectric layer 8 is exposed, so that the reconfigurable charge storage layer 11 and the gate electrode 12 are further formed;

step nine: with reference to fig. 42 to 47, an insulating layer is deposited on the basis of step eight by a deposition process, and after planarization, the insulating layer located above the reconfigurable charge storage layer 11 generated in step eight is etched by an etching process to further form an insulating dielectric layer 8, and then one of metal, alloy, polysilicon or metal silicide is deposited by a deposition process and planarized until the insulating dielectric layer 8 is exposed, so as to further form the reconfigurable charge storage layer 11;

step ten: with reference to fig. 48 to 51, an insulating layer is deposited on the basis of the ninth step by a deposition process, after planarization, the insulating layer located above the reconfigurable charge storage layer 11 generated in the ninth step and between two side portions of the reconfigurable charge storage layer 11 is etched by an etching process to further form an insulating dielectric layer 8, then one of metal, alloy, polysilicon or metal silicide is deposited by a deposition process, and the insulating dielectric layer 8 is planarized until the insulating dielectric layer 8 is exposed, so that the reconfigurable charge storage layer 11 is further formed;

step eleven: with reference to fig. 52 to 55, depositing an insulating layer on the basis of the tenth step by a deposition process, etching off the insulating layer above the reconfigurable charge storage layer 11 generated in the tenth step by an etching process after planarization to further form an insulating dielectric layer 8, depositing the insulating layer by a deposition process, and planarizing until the insulating dielectric layer 8 is exposed to form a reconfigurable electrode insulating layer 13; depositing an insulating layer by a deposition process, etching the insulating layer above the reconfigurable electrode insulating layer 13 by an etching process after planarization to further form an insulating dielectric layer 8, depositing one of metal, alloy, polycrystalline silicon or metal silicide by the deposition process, and planarizing until the insulating dielectric layer 8 is exposed to form a reconfigurable electrode 14;

step twelve: with reference to fig. 1-5, on the basis of the eleventh step, the middle area of the left side of the insulating dielectric layer 8 is etched to expose the upper surfaces of the left side areas of the negatively doped source region 4 and the positively doped source region 5 by an etching process; etching off the middle part area of the right side of the insulating medium layer 8 until the upper surfaces of the right side part areas of the negative doped drain region 6 and the positive doped drain region 7 are exposed; then, one of metal, alloy or metal silicide is deposited by a deposition process, and then, planarization treatment is performed until the upper surface of the isolation insulating medium 8 is exposed, thereby forming the source electrode 15 and the drain electrode 16.