阅读说明：本技术 一种输入高电平自适应的输入驱动电路 (Input high level self-adaptive input drive circuit ) 是由 吴佳 李礼 吴叶楠 于 2021-08-31 设计创作，主要内容包括：本发明公开了一种输入高电平自适应的输入驱动电路,包括第一运算放大器、第二运算放大器及反相器；所述第一运算放大器与输入信号IN相连,所述第一运算放大器的输出电压通过电阻对电容进行充放电；所述电阻和电容连接于第一运算放大器与第二运算放大器之间；所述第二运算放大器的输出信号与输入信号IN反相,经过反相器之后再次反相,使输出信号OUT的相位与输入信号IN一致。本发明公开的输入高电平自适应的输入驱动电路,结构简单紧凑、成本低廉,其所支持的输入高电平电压可以实时动态改变,应用灵活性强,适应范围广。(The invention discloses an input high-level self-adaptive input driving circuit, which comprises a first operational amplifier, a second operational amplifier and a phase inverter, wherein the first operational amplifier is connected with the second operational amplifier; the first operational amplifier is connected with an input signal IN, and the output voltage of the first operational amplifier charges and discharges a capacitor through a resistor; the resistor and the capacitor are connected between the first operational amplifier and the second operational amplifier; the output signal of the second operational amplifier is inverted with respect to the input signal IN, and is inverted again after passing through the inverter, so that the phase of the output signal OUT coincides with the input signal IN. The input high-level self-adaptive input driving circuit disclosed by the invention has the advantages of simple and compact structure, low cost, capability of dynamically changing the supported input high-level voltage in real time, strong application flexibility and wide application range.)

1. An input high-level self-adaptive input driving circuit comprises a first operational amplifier, a second operational amplifier and an inverter; the circuit is characterized IN that the first operational amplifier is connected with an input signal IN, the output voltage of the first operational amplifier changes along with the input signal, and a capacitor is charged and discharged through a resistor; the capacitor is used for stabilizing voltage, and the voltage stabilized by the capacitor is used as a reference voltage by the second operational amplifier; the resistor and the capacitor are connected between the first operational amplifier and the second operational amplifier; the output signal of the second operational amplifier is inverted with respect to the input signal IN, and is inverted again after passing through the inverter, so that the phase of the output signal OUT coincides with the input signal IN.

2. The input high-level adaptive input drive circuit according to claim 1, wherein: the voltage stabilized by the capacitor is the average value of the high level and the low level of the input signal.

3. The input drive circuit according to claim 2, wherein: and a power supply voltage VDDIO of the first operational amplifier and the second operational amplifier is a maximum value of the input high level VH.

4. The input drive circuit according to claim 1, wherein: the inverter is composed of a PMOS transistor and an NMOS transistor.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an input high-level self-adaptive input driving circuit.

Background

For deep sub-micron integrated circuits, the high level of their input and output signals is often different from the high level of digital signals in their internal circuits. For example, the high level of a 0.18um technology integrated circuit input signal is typically 3.3V, but the high level of an internal digital signal is typically 1.8V. The low level of the input/output signal is generally equal to the low level of the signal inside the integrated circuit, and is 0V. Therefore, the input driving circuit of the integrated circuit needs to convert the high level of the input signal into the high level of the signal inside the integrated circuit to ensure that the circuit inside the integrated circuit can process the input data normally.

As shown in fig. 1, the schematic diagram of the structure of a conventional input driving circuit is equivalent to a series connection of two stages of inverters. That is, the power supply voltage VDDIO of the first stage inverter coincides with the input high level voltage, and the power supply voltage VDDCORE of the second stage inverter coincides with the high level voltage of the internal signal of the integrated circuit. Meanwhile, the sizes of the NMOS transistor and the PMOS transistor in the two-stage inverter are adjusted to adjust the overturning threshold voltage of the two-stage inverter, so that the conversion of high-level voltage of input and output signals and internal signals can be realized. However, in the conventional circuit, the input high-level voltage needs to be predetermined during design, so as to determine the size of each transistor, and after the integrated circuit is designed and produced, the size of each transistor cannot be changed, so that the input high-level voltage supported by the integrated circuit cannot be dynamically adjusted during use, which causes great limitation on the flexibility of application, and cannot meet the actual needs in numerous application scenarios.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the input high-level self-adaptive input driving circuit which has the advantages of simple and compact structure, low cost, wide application range and strong application flexibility.

In order to solve the technical problems, the invention adopts the following technical scheme:

an input high-level self-adaptive input driving circuit comprises a first operational amplifier, a second operational amplifier and an inverter; the first operational amplifier is connected with an input signal IN, the output voltage of the first operational amplifier changes along with the input signal, and the capacitor is charged and discharged through the resistor; the capacitor is used for stabilizing voltage, and the voltage stabilized by the capacitor is used as a reference voltage by the second operational amplifier; the resistor and the capacitor are connected between the first operational amplifier and the second operational amplifier; the output signal of the second operational amplifier is inverted with respect to the input signal IN, and is inverted again after passing through the inverter, so that the phase of the output signal OUT coincides with the input signal IN.

The voltage stabilizing effect of the capacitor can stabilize the voltage of the capacitor to be the average value (VH + VL)/2 of the high level and the low level of the input signal, and the average value is used as the reference voltage of the second operational amplifier.

Further, the input drive circuit of the present invention performs voltage setting according to the following rule:

(a) when the input voltage is greater than (VH + VL)/2, the second operational amplifier outputs a low-level voltage which is a fixed value GND;

(b) when the input voltage is less than (VH + VL)/2, the second operational amplifier outputs a high level voltage with a fixed value VDDIO.

As a further improvement of the invention: the inverter is composed of a PMOS transistor and an NMOS transistor.

As a further improvement of the invention: and a power supply voltage VDDIO of the first operational amplifier and the second operational amplifier is a maximum value of the input high level VH.

Compared with the prior art, the invention has the advantages that: the first operational amplifier and the following resistor-capacitor circuit can keep the + input of the second operational amplifier at about half of the input high-level voltage, so that the second operational amplifier outputs GND when IN inputs any high level and outputs VDDIO when IN inputs low level, thus the input of the last stage inverter is not VDDIO or is GND, and the input signal of the last stage inverter is changed from uncertain high-level voltage to fixed high-level signal VDDIO.

The input high-level self-adaptive input driving circuit disclosed by the invention has the advantages of simple and compact structure, low cost, capability of dynamically changing the supported input high-level voltage in real time, strong application flexibility and wide application range.

Drawings

Fig. 1 is a schematic diagram of a conventional driving circuit according to the prior art.

Fig. 2 is a schematic circuit diagram of a driving circuit according to an embodiment of the present invention.

In fig. 2: 1 a first operational amplifier, 2 a second operational amplifier, 3PMOS transistor, 4NMOS transistor, 5 resistor and 6 capacitor.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

The invention will be described in further detail below with reference to the drawings and specific examples.

As shown in fig. 2, the input high-level adaptive input driving circuit of the present invention includes a first operational amplifier 1, a second operational amplifier 2 and an inverter; the first operational amplifier 1 is connected with an input signal IN, the output voltage of the first operational amplifier 1 changes along with the input signal, and a capacitor 6 is charged and discharged through a resistor 5; the capacitor 6 is used for stabilizing voltage, and the voltage stabilized by the capacitor 6 is used as a reference voltage by the second operational amplifier 2; the resistor 5 and the capacitor 6 are connected between the first operational amplifier 1 and the second operational amplifier 2; the output signal of the second operational amplifier 2 is inverted with respect to the input signal IN, passes through the inverter, and is inverted again, so that the phase of the output signal OUT coincides with the input signal IN.

In a specific application example, since the probability of inputting the high level and the low level is almost the same, the voltage stabilizing effect of the capacitor 6 can stabilize the voltage of the capacitor 6 to be the average value (VH + VL)/2 of the high level and the low level of the input signal, and the average value is used as the reference voltage of the second operational amplifier 2.

In the specific application example, the invention further performs voltage setting according to the following rules:

(a) when the input voltage is greater than (VH + VL)/2, the second operational amplifier 2 outputs a low level voltage as a fixed value GND;

(b) when the input voltage is less than (VH + VL)/2, the second operational amplifier 2 outputs a high level voltage of VDDIO.

In a specific application example, the inverter is composed of a PMOS transistor 3 and an NMOS transistor 4.

In a specific application example, the fixed high-level voltage VDDIO output by the second operational amplifier 2 is converted into the high-level voltage VDDCORE of the internal signal of the integrated circuit by adjusting the sizes of the PMOS transistor 3 and the NMOS transistor 4 in the inverter, so that the conversion between the dynamic high-level voltage of the input signal and the high-level voltage of the internal signal of the integrated circuit is finally realized.

In a specific application example, the supply voltage VDDIO of the first operational amplifier 1 and the second operational amplifier 2 is the maximum value of the input high level VH.

In the specific application example, the power supply voltage VDDCORE is a high level voltage of the signal inside the integrated circuit where the input driving circuit is located.

In a specific application example, with reference to fig. 2, the detailed structure of the driving circuit of the present invention is:

the input port is an input signal IN and the output port is an output signal OUT.

The input port + of the first operational amplifier 1 is connected with an input signal IN and the input port-of the second operational amplifier 2, the input port-is connected with the output port of the first operational amplifier 1 and one end of the resistor 5, the output port is connected with the input port-of the first operational amplifier 1 and one end of the resistor 5, the power supply voltage is VDDIO, and the ground is GND.

The input port of the second operational amplifier 2 is connected with the input signal IN and the input port + of the first operational amplifier 1, the input port + is connected with the other end of the resistor 5 and one end of the capacitor 6, the output port is connected with the grid of the PMOS transistor 3 and the grid of the NMOS transistor 4, the power supply voltage is VDDIO, and the ground is GND.

One end of the resistor 5 is connected to the output port of the first operational amplifier 1 and the input port of the first operational amplifier 1, and the other end is connected to one end of the capacitor 6 and the input port + of the second operational amplifier 2.

One end of the capacitor 6 is connected to one end of the resistor 5 and the input port + of the second operational amplifier 2.

The PMOS transistor 3 has a drain connected to the drain of the NMOS transistor 4 and the output signal OUT, a gate connected to the output port of the second operational amplifier 2, and a source and bulk connected to the supply voltage VDDCORE.

The drain of the NMOS transistor 4 is connected to the drain of the PMOS transistor 3 and the output signal OUT, the gate is connected to the output port of the second operational amplifier 2, and the source is connected to the ground GND.

The working flow of the driving circuit in the specific application of the invention is as follows:

when the input signal changes randomly at any high level VH and low level VL, the output voltage of the first operational amplifier 1 changes following the input signal, and the capacitor 6 is charged and discharged through the resistor 5. Since the probability of inputting the high level and the low level is almost the same, the voltage stabilizing effect of the capacitor 6 stabilizes the voltage of the capacitor 6 to be the average value (VH + VL)/2 of the high level and the low level of the input signal, and uses the average value as the reference voltage of the second operational amplifier 2. When the input voltage is greater than (VH + VL)/2, the second operational amplifier 2 outputs a low level voltage as a fixed value GND; when the input voltage is smaller than (VH + VL)/2, the second operational amplifier 2 outputs a high level voltage of VDDIO. The output signal of the second operational amplifier 2 is inverted from the input signal IN, and is inverted again by the inverter constituted by the last PMOS transistor 3 and NMOS transistor 4, so that the phase of the output signal OUT coincides with the input signal IN. The fixed high-level voltage VDDIO output by the second operational amplifier 2 is converted into the high-level voltage VDDCORE of the internal signal of the integrated circuit by adjusting the sizes of the PMOS transistor 3 and the NMOS transistor 4, and finally the conversion between the dynamic high-level voltage of the input signal and the high-level voltage of the internal signal of the integrated circuit is realized.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.