Scope-based explicit data stream processor and related computer-readable medium and method

文档序号：197375 发布日期：2021-11-02 浏览：24次中文

阅读说明：本技术 基于范围的显式数据流处理器和有关的计算机可读介质和方法 (Scope-based explicit data stream processor and related computer-readable medium and method ) 是由 G·古普塔 M·S·麦克勒瓦伊内 R·W·史密斯 T·P·施派尔 D·T·哈珀三世于 2020-03-09 设计创作，主要内容包括：示例性的基于范围(reach)的显式数据流处理器以及有关的计算机可读介质和方法。基于范围的显式数据流处理器被配置为支持执行生产者指令,生产者指令是利用旨在消耗由生产者指令所生产的值的消费者指令的显式命名来编码的。基于范围的显式数据流处理器被配置为作为处理生产者指令的结果,将可用的生产值作为显式所命名的消费者指令的输入。基于范围的显式数据流处理器支持执行生产者指令,生产者指令基于使用生产者指令作为从生产者指令的相对参考点来显式地命名消费者指令。该基于范围的显式命名架构不需要指令被分组在指令块中,以支持用于消费者指令的显式命名的固定块参考点,并且因此不被限于仅在生产者指令的同一指令块内消费者指令的显式命名。(Exemplary scope-based (reach) explicit data stream processors and related computer-readable media and methods. The scope-based explicit data stream processor is configured to support execution of producer instructions encoded with an explicit naming of consumer instructions intended to consume values produced by the producer instructions. The scope-based explicit data stream processor is configured to take available production values as input to an explicitly named consumer instruction as a result of processing the producer instruction. The scope-based explicit data stream processor supports execution of producer instructions that are based on explicitly naming consumer instructions using the producer instructions as a relative reference point from the producer instructions. This range-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and is therefore not limited to explicit naming of consumer instructions only within the same instruction block of producer instructions.)

1. A processor configured to:

receiving a plurality of instructions in an instruction stream to be executed from an instruction memory, the plurality of instructions comprising a plurality of producer instructions and a plurality of consumer instructions;

dispatching a consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the consumer instruction being available;

executing a producer instruction of the plurality of producer instructions to generate a production value, the producer instruction configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance from the producer instruction in the instruction stream;

determining whether the executed producer instruction includes an explicit consumer name; and

in response to determining that the executed producer instruction includes an explicit consumer name, writing the production value of the executed producer instruction to the at least one operand of the consumer instruction identified as being located a distance from the producer instruction in the instruction stream by the consumer target distance value of the executed producer instruction.

2. The processor of claim 1, further configured to:

dispatch a second consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the second consumer instruction being available;

determining whether the executed producer instruction includes a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and an associated second consumer operand value, the second consumer instruction distance representing a second relative instruction distance from the producer instruction in the instruction stream; and

in response to determining that the executed producer instruction includes a second explicit consumer name, writing the production value of the executed producer instruction to at least one operand of the second consumer instruction identified as being located a second distance from the producer instruction in the instruction stream by the second consumer target distance value of the executed producer instruction.

3. The processor of claim 1, configured to:

dispatching the consumer instruction including a conditional consumer instruction to be executed in response to a predicate of the consumer instruction being available;

executing the producer instruction of the plurality of producer instructions to generate the production value, the producer instruction configured to include the at least one explicit consumer name, each explicit consumer name including the consumer target distance value and the associated consumer operand value, the consumer target distance value representing the relative instruction distance to the producer instruction in the instruction stream, the associated consumer operand value including a consumer predicate value;

in response to determining that the executed producer instruction includes an explicit consumer name, writing the production value of the executed producer instruction to the predicate of the conditional consumer instruction in instruction processing circuitry, the conditional consumer instruction identified as being located at a distance from the producer instruction in the instruction stream by the consumer target distance value of the executed producer instruction.

4. The processor of claim 1, comprising:

an instruction processing circuit configured to receive the plurality of instructions in the instruction stream to be executed from the instruction memory, the plurality of instructions including the plurality of producer instructions and the plurality of consumer instructions;

the instruction processor circuit comprises:

a production value storage circuit configured to store a production value associated with at least one operand of a received consumer instruction of the plurality of consumer instructions;

a dispatch circuit configured to: dispatch the consumer instruction to be executed to an execution circuit in response to the production value for the at least one operand of the consumer instruction being available in the production value storage circuit;

the execution circuitry configured to execute the producer instruction of the plurality of producer instructions to generate the production value;

a write circuit configured to:

determining whether the executed producer instruction includes an explicit consumer target distance value; and

in response to determining that the executed producer instruction includes an explicit consumer target distance value, writing the producer value of the executed producer instruction associated with the at least one operand of a consumer instruction identified as being located at the distance from the producer instruction in the instruction stream by the consumer target distance value of the executed producer instruction to the producer value storage circuitry.

5. The processor of claim 4, wherein the instruction processing circuit further comprises a decoder circuit configured to:

decoding the received producer instruction into a decoded producer instruction; and

decoding the received consumer instruction into a decoded consumer instruction; and is

Wherein:

the production value storage circuitry is configured to store the production value associated with at least one operand of the decoded consumer instruction;

the dispatch circuitry is configured to dispatch the decoded consumer instruction to be executed to execution circuitry in response to the production value associated with the at least one operand of the consumer instruction being available in the production value storage circuitry;

the execution circuitry is configured to execute the decoded producer instruction to generate the production value, the decoded producer instruction including the explicit consumer target distance value representing the relative instruction distance from the producer instruction in the instruction stream and the associated consumer operand value; and is

The write circuitry is configured to, in response to determining that the executed decoded producer instruction includes the explicit consumer target distance value, write the produced value of the executed decoded producer instruction associated with at least one operand of the decoded consumer instruction to the produced value storage circuitry, the decoded consumer instruction identified as being located at the distance from the producer instruction in the instruction stream indicated by the explicit consumer target distance value of the executed producer instruction.

6. The processor of claim 4, wherein:

the instruction processing circuit is further configured to map the at least one operand of the consumer instruction to a physical register; and is

The instruction processing circuit is configured to, in response to determining that the executed producer instruction does not include the explicit consumer target distance value, write the production value for the executed producer instruction to the physical register mapped to the at least one operand of the consumer instruction.

7. The processor of claim 6, wherein the instruction processing circuitry further comprises register access circuitry configured to:

accessing the physical register mapped to the at least one operand of the consumer instruction to retrieve the production value of the executed producer instruction; and

providing the retrieved production value as the at least one operand of the consumer instruction.

8. The processor of claim 6, further comprising:

a physical register file comprising a plurality of physical registers; and

a register map table comprising a plurality of map entries, each of the map entries configured to store at least one address pointer to an address of a physical register in the physical register file;

wherein:

the instruction processing circuitry is configured to map the at least one operand to a mapping entry in the register map table, the mapping entry being mapped to a physical register of the plurality of physical registers in the physical register file; and is

In response to determining that the executed producer instruction does not include the explicit consumer target distance value, writing the producer value for the executed producer instruction to a logical register mapped to the mapping entry in the register mapping table, the mapping entry mapped to the at least one operand of the consumer instruction.

9. The processor of claim 4, further comprising: the instruction memory configured to store the plurality of instructions.

10. A method of providing a production value from a producer instruction executed by a processor as input to a consumer instruction based on an explicit naming of the consumer instruction, comprising:

executing a producer instruction of the plurality of producer instructions to generate a production value, the producer instruction configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance representing a relative instruction distance from the producer instruction in the instruction stream;

determining whether the executed producer instruction includes an explicit consumer name;

dispatch a consumer instruction of the plurality of consumer instructions to be executed in response to the at least one operand of the consumer instruction being stored.

11. The method of claim 10, further comprising:

dispatch a second consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the second consumer instruction being available;

12. The method of claim 10, comprising:

dispatching the consumer instruction including a conditional consumer instruction to be executed in response to a predicate of the consumer instruction being available;

in response to determining that the executed producer instruction includes an explicit consumer name, writing the production value of the executed producer instruction to the predicate of the conditional consumer instruction in instruction processing circuitry, the conditional consumer instruction identified as being located at a distance from the producer instruction in the instruction stream by the consumer target distance value of the executed producer instruction.

13. The method of claim 12, further comprising:

mapping the at least one operand of the consumer instruction to a physical register; and

in response to determining that the executed producer instruction does not include an explicit consumer target distance value, writing the produced value of the executed producer instruction to the physical register mapped to the at least one operand of the consumer instruction.

14. The method of claim 13, further comprising:

accessing the physical register mapped to the at least one operand of the consumer instruction to retrieve the production value of the executed producer instruction; and

providing the retrieved production value as the at least one operand of the consumer instruction.

15. A non-transitory computer-readable medium having stored thereon a program of instructions, the program of instructions comprising a plurality of computer-executable instructions for execution by a processor, the plurality of computer-executable instructions comprising:

a producer instruction comprising an instruction type and an explicit consumer name, the explicit consumer name comprising a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance in an instruction stream from the producer instruction; and

a consumer instruction comprising an instruction type and an operand, the consumer instruction located at an instruction distance from the producer instruction in the instruction program by the consumer target distance value of the producer instruction, and the associated consumer operand value of the producer instruction mapped to the operand of the consumer instruction.

Technical Field

The technology of the present disclosure relates to executing instructions by a Central Processing Unit (CPU) processor, and more particularly to a CPU processor that supports explicit data flow communication of production values from producer instructions to dependent consumer instruction(s).

Background

Microprocessors (also known as "processors") perform computational tasks on various applications. A conventional microprocessor includes a Central Processing Unit (CPU) that includes one or more processor cores (also referred to as "CPU cores") that execute software instructions. The software instructions instruct the CPU to perform operations based on the data. The CPU performs operations according to the instructions to generate a result, i.e., a production value. The production value may then be provided as output to the I/O device, or another consumer instruction executed by the CPU as an input value may be available (i.e., communicated). Thus, the consumer instruction depends on the production value produced by the "producer" instruction as the input value for the consumer instruction for execution. These producer and consumer instructions are also collectively referred to as "dependent instructions".

Traditionally, communication between dependent instructions has been done implicitly using the General Purpose Register (GPR) namespace as a rendezvous point. This communication is referred to as "implicit" because the producer instruction that produces (i.e., writes) a value into the GPR does not know which consumer instruction(s) will consume (i.e., read) the produced value. This communication method may have limitations. As a limitation, the GPR namespace has a limited size because the names of consumer instructions are encoded as instructions of a limited length. Also, the number of GPRs is less than the number of values produced by a computation, so that multiple production values must be communicated using the same name of the producer instruction-i.e., aliasing occurs within the producer and consumer instruction sets. Further, since producer instructions do not reference consumer instructions for their production values, there is no direct way to inform a consumer that a value it will consume has been produced. These problems have been addressed in different ways in modern CPU implementations, but the costs and tradeoffs associated with solutions vary.

An alternative method of communicating between dependent instructions is to explicitly name the consumer instruction, which consumes the production value in the producer instruction. This is referred to as "explicit" communication. A CPU built on an explicit communication model has been referred to as an explicit data flow graphics execution (EDGE) CPU. Explicit communication solves the problem of informing the production value to the consumer instruction related to implicit communication. Since the producer instruction directly encodes the name of the consumer instruction in the explicit communication model, the consumer is easily notified when the producer instruction generates its production value to provide the input value of the consumer instruction. One problem that may still exist in explicit communication is the size allocated to encode the consumer name in the producer instruction. The number of bits allocated to encode the consumer name in the producer instruction must be sufficient to name the possible consumer instructions required based on the design. Providing an instruction format that allows for a larger bit encoding size of the consumer instruction name provides greater flexibility in explicit naming of consumer instructions, but also consumes a larger amount of memory space for storing instructions. Conventional EDGE processors have addressed the size of instruction names by partitioning the fully computed data stream graph into multiple fragments (sometimes referred to as instruction blocks), where explicit consumer naming is based on the beginning of an instruction block. EDGE processors are designed to employ an execution model that explicitly communicates production values to consumer instructions within the same block of a local namespace, such that the maximum number of instructions in a block is determined and limited by the size of the name that can be encoded in the instruction.

Thus, while EDGE processors have the advantage of reduced complexity relative to the implicit communication model, EDGE processors have the disadvantage of being limited in terms of explicitly conveying production values to consumer instructions in the same instruction block. Further, because the consumer name is only valid within a given instruction block, there is a problem in communicating the production value inside the instruction block across block boundaries. Previous EDGE CPUs used implicit communication (via memory or GPR namespaces) to communicate production values externally across instruction block boundaries. Although inter-block communication is less frequent than intra-block communication for reasonable block sizes, the use of implicit communication diminishes the advantages of explicit communication for dependent instructions. Constraining the instruction blocks to have a maximum size also places a burden on the programmer or compiler, who must decide which instructions are best suited to place in each instruction block based on the communication pattern and associated costs between dependent instructions.

Disclosure of Invention

Exemplary aspects disclosed herein include range (reach) -based explicit data stream processors and related computer-readable media and methods. The scope-based explicit data stream processor is configured to support execution of producer instructions encoded with an explicit naming of consumer instructions intended to consume values produced by the producer instructions. The scope-based explicit data stream processor is configured to provide or make available as input to an explicitly named consumer instruction as a result of processing the encoded producer instruction. In exemplary aspects disclosed herein, a range-based explicit data stream processor supports executing producer instructions that explicitly name consumer instructions based on naming consumer instructions using the producer instructions as a reference point and with respect to the reference point. The name assigned to a consumer instruction by a producer instruction is referred to as a target distance. The maximum target distance allowed by a range-based explicit data stream processor is referred to as the "range" of the processor. The scope of the processor defines the maximum set of consumer instructions that can be explicitly named by producer instructions. In this manner, by way of example, such range-based explicit naming does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is limited to explicitly naming consumer instructions only within instruction blocks of producer instructions. Thus, removing the architectural limitations of instruction blocks in a data stream processor may allow the data stream processor to be designed to support explicit data stream communication over larger computing graphics that are not limited by instruction block size. Explicit consumer naming based on scopes may also have the advantage of requiring less consumer-coded namespaces ("scope namespaces"), because consumers name places relative to producer instructions, rather than fixed reference places that may be more frequently distant from consumer instructions.

In other exemplary aspects disclosed herein, the target distance of a consumer instruction named by a producer instruction is encoded as a target distance value in a range namespace of the producer instruction. The bit size selected for the range namespace defines the maximum target distance or range of the consumer instruction set with which producer instructions can explicitly communicate directly. The bit size of a range namespace for a particular embodiment is a design decision determined by a desired tradeoff between the size of the instruction memory required to store a given number of instructions and the desired range namespace. The scope-based explicit data stream processor may also support the use of intermediate consumer instruction(s) named by producer instructions for indirect naming of consumer instructions if the consumer instruction is out of range of the producer instructions. In this regard, the intermediate consumer instruction(s) may name another consumer instruction(s) that may name the final prospective consumer instruction to provide the production value to the final prospective consumer instruction. Further, scope-based explicit producer/consumer communication does not preclude the ability of a scope-based explicit data stream processor to support implicit producer/consumer communication if the target distance is greater than the scope value and, for example, the programmer or compiler does not deem intermediate consumer instructions to be needed.

In this regard, in one exemplary aspect, a processor is provided. The processor is configured to receive from the instruction memory a plurality of instructions in an instruction stream to be executed, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions. The processor is further configured to dispatch a consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the consumer instruction being available. The processor is further configured to execute a producer instruction of the plurality of producer instructions to generate a production value, the producer instruction configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance representing a relative instruction distance from the producer instruction in the instruction stream. The processor is further configured to determine whether the executed producer instruction includes an explicit consumer name. In response to determining that the executed producer instruction includes an explicit consumer name, the processor is further configured to write a production value of the executed producer instruction to at least one operand of a consumer instruction identified as being located at a distance from the producer instruction in the instruction stream by a consumer target distance value of the executed producer instruction.

In another exemplary aspect, a method of providing a production value from a producer instruction executed by a processor as input to a consumer instruction based on explicit naming of the consumer instruction is provided. The method includes receiving from an instruction memory a plurality of instructions in an instruction stream to be executed, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions. The method also includes executing a producer instruction of the plurality of producer instructions to generate a production value, the producer instruction configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance from the producer instruction in the instruction stream. The method also includes determining whether the executed producer instruction includes an explicit consumer name. In response to determining that the executed producer instruction includes an explicit consumer name, the method further includes writing a production value of the executed producer instruction to at least one operand of a consumer instruction identified as being located a distance from the producer instruction in the instruction stream by a consumer target distance value of the executed producer instruction. The method also includes dispatching a consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the consumer instruction being stored.

In another exemplary aspect, a non-transitory computer-readable medium having stored thereon a program of instructions including a plurality of computer-executable instructions for execution by a processor is provided. The plurality of computer-executable instructions comprises: a producer instruction comprising an instruction type and an explicit consumer name, the explicit consumer name comprising a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance from the producer instruction in the instruction stream. The plurality of computer-executable instructions includes a consumer instruction including an instruction type and an operand, the consumer instruction being located at an instruction distance from a producer instruction in the program of instructions by a consumer target distance value of the producer instruction, and an associated consumer operand value of the producer instruction being mapped to the operand of the consumer instruction.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Drawings

The accompanying drawings incorporated in and forming a part of the specification illustrate several aspects of the present disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is an exemplary list of computer instructions to illustrate the possibility that a scope-based explicit data stream processor supports scope-based explicit consumer naming for consumer instruction(s) in the scope four (4) producer instructions;

FIG. 2A illustrates an exemplary producer instruction that is coded using an instruction data format that includes a range-based explicit consumer namespace for encoding one or more range-based explicit consumer instructions identified as consuming values produced by the producer instruction;

FIG. 2B illustrates an exemplary instruction data format for the producer instruction in FIG. 2A;

FIG. 3A is an exemplary instruction stream of computer instructions encoded with scope-based explicit consumer naming and configured for processing by a scope-based explicit data stream processor, wherein the instruction list includes a branch instruction that creates a write-before-write (WAW) hazard, and includes a WAW instruction following the branch instruction to address the WAW hazard;

FIG. 3B illustrates the exemplary instruction flow of FIG. 3A compared to other instruction flows that allow a processor to perform the same operations based on implicit consumer naming and explicit consumer naming in an instruction block architecture;

FIG. 4 is a schematic diagram of an exemplary processor-based system that includes a range-based data stream processor configured to support execution of producer instructions encoded with range-based explicit consumer naming to provide production values from the executed producer instructions for consumption by consumer instructions identified by range-based explicit consumer naming;

FIG. 5 is a flow diagram illustrating an exemplary process for a scope-based explicit data stream processor, such as the scope-based explicit data stream processor in FIG. 4, communicating production values from executed producer instructions to be consumed by consumer instructions identified by scope-based explicit consumer instruction naming in the executed producer instructions;

FIG. 6A is an exemplary instruction stream of computer instructions encoded with scope-based explicit consumer naming and configured for processing by a scope-based explicit data stream processor, wherein the instruction list includes WAW hazards due to branch instructions and does not include intermediate WAW instructions that address the WAW hazards;

FIG. 6B is an exemplary instruction flow of the computer instructions of FIG. 6A, wherein the instruction flow addresses the WAW hazard by concluding that an instruction creating the WAW hazard based on a branch not taken;

FIG. 7 is an exemplary instruction stream of computer instructions encoded with scope-based explicit consumers/names and configured to be processed by a scope-based explicit data stream processor, wherein the instruction list includes branch instructions encoded to invalidate production values for the scope-based explicit data stream processor when a branch is taken to address a WAW hazard; and

FIG. 8 is a block diagram of an exemplary processor-based system that includes a range-based explicit data stream processor (including but not limited to the range-based data stream processor of FIG. 4) and that is configured to support execution of producer instructions encoded with range-based explicit naming of consumer instructions intended to consume values produced by the producer instructions.

Detailed Description

Example aspects disclosed herein include scope-based explicit data stream processors and related computer-readable media and methods. A range-based explicit data stream processor is configured to support execution of producer instructions encoded with an explicit naming of consumer instructions intended to consume values produced by the producer instructions. The scope-based explicit data stream processor is configured to provide or make available as input to an explicitly named consumer instruction as a result of processing the encoded producer instruction. In exemplary aspects disclosed herein, a range-based explicit data stream processor supports executing producer instructions that explicitly name consumer instructions based on using the producer instructions as a reference point and naming the consumer instructions relative to the reference point. The name assigned by the producer instruction to the consumer instruction is referred to as the target distance. The maximum target distance allowed by a range-based explicit data stream processor is referred to as the "range" of the processor. The scope of the processor defines the maximum set of consumer instructions that can be explicitly named by producer instructions. In this way, by way of example, this range-based explicit naming does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is limited to explicitly naming consumer instructions only within instruction blocks of producer instructions. Thus, removing the architectural limitations of instruction blocks in a data stream processor may allow the data stream processor to be designed to support explicit data stream communication over larger computing graphics that are not limited by instruction block size. Scope-based explicit consumer naming may also have the advantage of requiring less consumer-coded namespace ("scope namespace") because consumers name locations relative to producer instructions, rather than fixed reference locations that may be more frequently remote from consumer instructions.

In this regard, FIG. 1 is an exemplary instruction stream 100 extracted from a program of instructions stored in a computer memory, including a series of computer instructions I0 through I6 to be executed by a processor to illustrate an example of an explicitly named scope-based explicit consumer communication model of expected consumer instructions in producer instructions. A producer instruction is an instruction that, when executed by a processor, generates a production value according to the instruction type and operand(s) of the producer instruction. The production value may then be provided as an output value to an I/O device or made available (i.e., communicated) as an input value in a specified operand by another consumer instruction in an instruction stream executed in the processor. Thus, consumer instructions that use (i.e., consume) a production value generated by executing a producer instruction are producer instruction dependent. Dependent instructions are used in both in-order and out-of-order processors. For example, if instruction I2 in the instruction stream 100 in FIG. 1 consumed the production value generated by executing instruction I0 in the processor, instruction I2 would be the consumer instruction of producer instruction I0, thus creating a producer-consumer dependency between instructions I0 and I2. Communication of production values between dependent instructions may be accomplished implicitly in an implicit communication model using a General Purpose Register (GPR) namespace as a rendezvous point. However, due to the limited size of the GPR namespace, and because the producer instructions have no direct way to inform the consumer instructions that their production values have been generated, the implicit communication model may have limitations.

In this regard, as discussed in more detail below, the explicit consumer communication model based on ranges disclosed herein for use by a processor in communicating production values from producer instructions to consumer instructions during execution is an explicit consumer communication model based on "ranges". In this model, the processor is configured to process instructions utilizing a supported instruction format that includes the ability of producer instructions to explicitly name (i.e., encode) the expected dependent consumer instruction(s) within the producer instruction. The explicit consumer naming provides a notification recognized by a processor supporting a scope-based explicit consumer communication model during execution to pass production values from a producer instruction to a named target consumer instruction for consumption. In an explicit data flow communication model, methods are needed to encode the expected location of consumer instructions in producer instructions. In examples of scope-based explicit consumer communication models disclosed herein, explicit naming of consumer instructions in producer instructions is based on encoding "target distance" values in the producer instructions. The "target distance" value is based on indicating the expected location of the consumer instruction in the instruction stream using the location of the producer instruction in the instruction stream as a relative reference point. In other words, the "target distance" value defines the distance between the intended consumer instruction and the producer instruction in its instruction stream. This is illustrated by way of example in the instruction stream 100 in fig. 1. For example, if in the Instruction Set Architecture (ISA) of a range-based explicit data stream processor configured to process instruction stream 100, the "range" (i.e., the maximum target distance) is set to four (4), this means that any of instructions I0 through I6 in instruction stream 100 are able to explicitly name consumer instructions within four (4) instruction places of producer instructions in instruction stream 100. For example, the instruction I0, which is a producer instruction, may name any of the instructions I1 through I4 as a consumer instruction having a maximum target distance of four (4). Similarly, as shown in FIG. 1, instructions I1 and I2, which are producer instructions, may designate any of instructions I2 through I5 and instructions I3 through I6, respectively, as consumer instructions having a maximum target distance of four (4). However, for example, in this example, instruction I0 cannot directly target instruction I5 because I5 is located five (5) instruction positions from instruction I0, beyond the maximum target distance of four (4). Depending on the ISA to be explicitly named in the producer instruction, the target consumer instruction must also be located at a distance equal to or less than the maximum target distance. However, by naming one of the intermediate instructions I1-I4 as the consumer, and then the intermediate instruction names instruction I5 as the final consumer, instruction I0 may indirectly target instruction I5. Otherwise, as discussed in more detail below, intermediate consumer/producer instructions or implicit data stream communication may be employed.

In this way, by way of example, the range-based explicit consumer communication model does not require instructions to be grouped in instruction blocks that support explicitly named fixed block reference points for consumer instructions, and thus is limited to producer instructions that explicitly name consumer instructions only within their same instruction block. Thus, removing the architectural limitations of instruction blocks in a data stream processor may allow the data stream processor to be designed to support explicit data stream communication over larger computing graphics that are not limited by instruction block size. Each producer instruction in the scope-based explicit consumer communication model can have a private set of consumer names, which allows an unlimited number of consumers to be named (i.e., reached) in the instruction stream, and thus allows computational graphics over the entire instruction stream, if desired. However, the allocated bit in the supported range namespace will control the maximum target distance that can be encoded in the producer instruction and processed by a compatible processor. The bit size of a range namespace is a design decision determined by a desired tradeoff between the instruction memory size required to store a given number of instructions and the desired range namespace. Regardless, scope-based explicit consumer naming has the advantage of requiring less consumer-encoded namespaces ("scope namespaces") compared to the block-atom execution model, because consumer naming is relative to producer instructions, rather than fixed references that may be more frequently distant from consumer instructions.

FIG. 2A illustrates an exemplary range-based explicit consumer named instruction format 200 ("instruction format 200") for producer instructions 202, which includes a range-based explicit consumer namespace for encoding one or more consumer instructions according to an exemplary range-based explicit named Instruction Set Architecture (ISA). FIG. 2B illustrates an example of an ADD producer instruction 204 encoded with the instruction format 200 of the producer instruction 202 in FIG. 2A to explicitly name consumers based on scope. A processor compatible with the scope-based explicit consumer communication model and instruction format 200 in fig. 2A communicates the production values resulting from execution of the producer instructions 202 to the named consumer instructions. In this example, as shown in FIG. 2A, instruction format 200 has instruction type INST. For example, an instruction type of the ADD instruction type is shown in FIG. 2B as ADD producer instruction 204. Further, as shown in FIG. 2A, the instruction format 200 also includes an optional operand OP that provides an input operand for the producer instruction 202. For example, the operand in the ADD producer instruction 204 in FIG. 2B is register R1. It is noted that operands may not be needed if, as the consumer of its production value, a previous producer instruction in the instruction stream targets ADD producer instruction 204.

As also shown in the example in FIG. 2A, instruction format 200 also includes a consumer namespace 206 to annotate one or more target consumers of producer instructions 200. In the example of fig. 2B, two named consumers 208(1), 208(2) are provided, identified by the symbol pair < + TD,'t' > respectively, where "TD" is the target distance and't' is one of the sets {0,1, …, N, P }. In this example, + TD indicates a relative target distance from producer instruction 202, where a consumer instruction for producer instruction 202 is located in the instruction stream. 't' indicates the operand of the named consumer instruction named for the processor by the producer instruction 202 to pass its production value. For example, a't' value of '0' means operand 0 of a consumer instruction, '1' means operand '1' of the consumer instruction, 'N' means operand 'N' of the consumer instruction to represent any other number of operands in the instruction format 200 that may be possible, and if the consumer instruction is a predicate instruction, 'P' means the predicate of the consumer instruction. Thus, the interpretation of the consumer namespace format < + TD,'t' > is that the production value from producer instruction 200 should be delivered to the consumer instruction 'TD' distance position forward from the producer instruction in the instruction stream, and the production value is used as input't' to the consumer instruction.

Thus, for example, as shown by ADD producer instruction 204 in FIG. 2B, the first named consumer is provided as < +3:0>, meaning that the production value from executing ADD producer instruction 204 will be communicated as operand 0 to the consumer instruction at a forward distance of three (3) instructions from producer instruction 204. As also shown by ADD producer instruction 204 in FIG. 2B, the second named consumer is provided as < +8:1>, which means that the production value from executing ADD producer instruction 204 will be communicated as operand 1 to the consumer instruction at a forward distance of eight (8) instructions from the producer instruction. If the maximum target distance is eight (8), three (3) bits may be provided in instruction format 200 to encode target distance + TD.

To further illustrate the scope-based explicit consumer communication model, FIG. 3A is provided to illustrate an exemplary instruction flow 300 of computer instructions I0 through I6 that are configured to be executed by a scope-based explicit data flow processor to perform scope-based explicit communication of production values to named consumer instructions. As shown in FIG. 3A, instruction I0 is an ADD instruction type, including the named consumer instruction at a distance '3' from the forward target of instruction I0 to receive the production value in operand 0. Thus, the consumer instruction of instruction I0 is instruction I3. Test if equal to 0 instruction (TEQZ.B), instruction I1 is a conditional branch instruction, with the conditional branch location of instruction I5 if the condition is true. Because the conditional branch instruction I1 is located between the producer instruction I0 and the expected consumer instruction I3, the conditional branch instruction I1 will execute before the consumer instruction I3. The conditional branch instruction I1 in this example is less than the named consumer target distance value of '3' from the producer instruction I0. The third instruction (for the target distance value '3') after instruction I0 is instruction I3 only if the conditional branch in instruction I1 evaluates to not true, and therefore the branch is not taken. If the branch was not taken from the execution of instruction I1, instruction I2 is executed, which names operand 1 of instruction I3 as the consumer of the production value from instruction I2, so that instruction I3 adds the produced results from instruction I0 and instruction I2 and stores the result in register R6. However, if the branch was taken in the conditional branch instruction I1, the third instruction after instruction I0 would be instruction I6, which is the instruction taken by the branch that is in the flow path taken for the branch of the conditional branch instruction I1. If the branch in the conditional branch instruction I1 is taken, this creates a write-before-write (WAW) hazard because the intent of the instruction stream 300 is to have the instruction I3 consume the results produced by the execution of the instruction I0. This WAW hazard is the result of the scope-based explicit consumer communication model naming the expected consumer instructions using relative target distance values based on the location of the producer instructions in the instruction stream. If the consumer name is at a relatively fixed location in the instruction stream 300 (such as, for example, the beginning of an instruction block), the instruction I0 may specifically name instruction I3 as its consumer to avoid WAW hazards. However, as previously described, the scope-based explicit consumer communication model may have the advantage of supporting scope-based explicit data stream communication on larger computing graphics that are not limited by instruction block size and require less scope namespace.

Thus, in this example, to prevent the production value from being erroneously delivered to the consumer instruction I6 when a branch is taken from execution of the conditional branch instruction I1 that creates a WAW hazard, instruction I5 is provided to perform a WAW operation in the data flow path 302 taken from the branch of execution of instruction I1 in the instruction stream 300, which instruction stream 300 also specifies instruction I6 as its consumer. The instruction I5 is considered to be a WAW instruction located between the instruction I6 and the consumer instruction I3 taken by the branch in the instruction stream 300. In this way, if the branch in the conditional branch instruction I1 is not taken to avoid the instruction I6 consuming unintended results from the instruction I0, the production value from the instruction I0 is overwritten by the producer instruction I5. A programmer or compiler that generates instructions according to a scope-based explicit consumer communication model may be configured to identify such a WAW hazard and prevent erroneous delivery of production values to the consumer instruction I6 when a branch is taken from execution of the conditional branch instruction I1 by employing another producer instruction (e.g., instruction I5 in fig. 3A) in the hazard flow path to perform a write-before-write (WAW) operation. The additional producer instruction I5 names the operands (e.g., operand 0) of an unexpected consumer instruction (e.g., instruction I6 in FIG. 3A) and a producer instruction that creates a WAW hazard (e.g., instruction I0 in FIG. 3A). This has the effect of causing the overwriting of the unexpected production value to be consumed by the unexpected consumer instruction.

For comparison purposes, FIG. 3B illustrates the exemplary instruction stream 300 of FIG. 3A as compared to two other similar instruction streams 302, 304. The instruction stream 302 is encoded using an implicit consumer communication model. The instruction stream 304 is encoded using an explicit consumer communication model that uses encoding locations based on the start of instruction blocks, respectively. The implicit consumer communication model based instruction stream 302 includes instructions I10 through I16. These instructions I10 through I16 are of the same instruction type as the instructions I0 through I6 in the instruction stream 300 and are encoded to cause the processor to generate the same results, but the instruction stream 302 uses register names to perform implicit consumer naming in producer instructions. The instruction stream 304 includes instructions I20 through I26. These instructions I20 through I26 are of the same instruction type as the instructions I0 through I6 in the instruction stream 300 and are encoded to cause the processor to generate the same results, but the instruction stream 304 uses explicit naming based on the absolute instruction location relative to the start of the instruction block to name the consumer in the producer instruction.

FIG. 4 is a schematic diagram of a processor-based system 400 including an exemplary scope-based explicit data stream processor 402 ("processor 402") configured to support a scope-based explicit consumer communication model. The processor 402 includes an instruction processing circuit 404 configured to process instructions to be executed. As an example, the processor 402 may be an in-order or out-of-order processor (OoP). The instructions 406 are fetched from the instruction memory 410 by an instruction fetch circuit 408 provided in the instruction processing circuit 404And (4) extracting. By way of example, the instruction memory 410 may be provided in or as part of a system memory in the processor-based system 400. An instruction cache 412 may also be provided in the processor 402 to cache instructions 406 fetched from the instruction memory 410 to reduce latency in the instruction fetch circuitry 408. The instruction fetch circuitry 408 in this example is configured to provide the instruction 406 as a fetched instruction 406F to one or more instruction pipelines I before the fetched instruction 406F to be executed reaches the execution circuitry 414₀To I_NAs an instruction stream 411 to be pre-processed in the instruction processing circuit 404. The fetched instructions 406F in the instruction stream 411 include producer instructions and consumer instructions that consume a production value as a result of the instruction processing circuit 404 executing the producer instructions. Instruction pipeline I₀To I_NProvided across different processing circuits or stages of instruction processing circuit 404 to pre-process and process fetched instructions 406F in a series of steps that may be executed concurrently to increase throughput prior to execution of fetched instructions 406F in execution circuit 414.

Control flow prediction circuitry 416 (e.g., branch prediction circuitry) is also provided in the instruction processing circuitry 404 in the processor 402 in fig. 4 to speculate or predict a target address of the instruction 406F fetched for control flow (such as a conditional branch instruction). The prediction of the target address by the control flow prediction circuit 416 is used by the instruction fetch circuit 408 to determine the next fetched instruction 406F to fetch based on the predicted target address. The instruction processing circuit 404 also includes an instruction decode circuit 418 configured to decode the fetched instructions 406F fetched by the instruction fetch circuit 408 into decoded instructions 406D to determine the instruction type and required action, which may also be used to determine in which instruction pipeline I the decoded instructions 406D should be placed₀To I_NIn (1). The decoded instruction 406D is then placed in the instruction pipeline I₀To I_NAnd is then provided to rename circuitry 420 in instruction processing circuitry 404. The rename circuitry 420 is configured to determine whether to decode the instruction 406DThere are any register names that need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The renaming circuitry 420 is configured to call a Register Map Table (RMT)422 to rename logical source register operands and/or write destination register operands of the decoded instruction 406D to available physical registers 424(1) through 424(X) (P) in a Physical Register File (PRF)426₀、P₁、…、P_x). Register Mapping Table (RMT)422 contains a plurality of mapping entries, each mapped to a corresponding logical register R₀To R_p(i.e., associated therewith). The map entries are configured to store information in the form of address pointers to physical registers 424(1) through 424(X) in a Physical Register File (PRF) 426. Each physical register 424(1) through 424(X) in the Physical Register File (PRF)424 contains data entries configured to store data for source and/or destination register operands of the decoded instruction 406D.

Instruction processing circuitry 404 in processor 402 in figure 4 also includes register access circuitry 428 prior to dispatch circuitry 430. Register access circuitry 428 is configured to map to logical registers R in a Register Map Table (RMT)422 of source register operands of decoded instruction 405D based on₀To R_pAccess physical registers 424(1) through 424(X) in a Physical Register File (PRF)426 to retrieve a production value from an executed instruction 406E in the execution circuitry 414. Register access circuitry 428 is also configured to provide the production value retrieved from executed decoded instruction 406E as a source register operand of decoded instruction 406D to be executed. Furthermore, in the instruction processing circuit 404, a dispatch circuit 430 is provided in the instruction pipeline I₀To I_NAnd is configured to dispatch the decoded instruction 406D to be executed to the execution circuitry 414 when all source register operands for the decoded instruction 406D are available. For example, the dispatch circuitry 430 is responsible for ensuring that the necessary values for the operands of the decoded consumer instruction 406D are available before dispatching the decoded consumer instruction 406D to the execution circuitry 414 for execution. Operation of decoded instruction 406DThe operand may include an immediate value, a value stored in memory, and a production value from other decoded instructions 406D, which will be considered a producer instruction of a consumer instruction.

The execution circuitry 414 is configured to execute the decoded instruction 406D received from the dispatch circuitry 430. The decoded instruction 406D that generates the production value to be consumed by the consumer instruction in the instruction processing circuit 404 is considered a producer instruction. As discussed above, in the range-based explicit consumer communication model supported by the processor 402 in fig. 4, the decoded producer instruction 406D may name a consumer instruction, and in this case will include an explicit consumer name encoded by a consumer target distance value TD + representing the relative instruction distance in the instruction stream 411 from the decoded producer instruction 406D, and an associated consumer operand value't'. The execution circuitry 414 is configured to determine whether the executed producer instruction 406D includes an explicit consumer name. If so, write circuitry 432 in instruction processing circuitry 404 is configured to write a production value generated by the executed producer instruction 406D to an operand of a consumer instruction 406D in instruction processing circuitry 404, the consumer instruction 406D identified as being located at a distance from the producer instruction 406D in the instruction stream 411 by a consumer target distance value TD + of the executed producer instruction 406D. In this example, the instruction processing circuitry 404 includes a production value storage circuitry 434, the production value storage circuitry 434 configured to receive and store production values from the write circuitry 432 that are generated by the execution circuitry 414 by executing the producer instruction 406D of the named consumer instruction 406D. The production value storage circuitry 434 is configured to make the produced result available to the dispatch circuitry 430 so that a production value may be provided and made available for the named consumer instruction 406D to be executed.

It is noted that producer instructions 406D may also include more than one explicitly named consumer instruction 406D, in which case write circuitry 432 may store produced results associated with more than one consumer instruction in a production value storage circuitry 434 to be provided to dispatch circuitry 430. Also note that as discussed above, the scope-based explicit consumer communication model supported by the processor 402 in FIG. 4 supports providing the produced results from the executed producer instructions 406D as predicates of the conditional consumer instructions 406D, such as conditional branch instructions. In this example, the producer instruction 406D may include an explicit consumer name for the expected conditional consumer instruction 406D, which includes a consumer target distance value TD + and a consumer predicate value that is an operand value't'. The write circuitry 432 may store the produced results as predicates associated with the named conditional consumer instruction 406D in the production value storage circuitry 434 to be provided to the dispatch circuitry 430 in preparation for dispatching the conditional consumer instruction 406D to be executed.

If the decoded instruction being executed does not explicitly name the consumer instruction 406D in the instruction stream 411, the write circuit 432 may write the produced result to the physical register P in the physical register file 426₀To P_XAnd/or memory called in decoded instruction 406D. If the desired consumer instruction 406D for producer instruction 406D is farther from producer instruction 406D in instruction stream 411 than the maximum consumer target distance value that may be encoded in producer instruction 406D, write circuitry may write the produced result to physical register P in physical register file 426₀To P_XTo provide implicit communication of the produced result to the consumer instruction 406D waiting to be dispatched to the execution circuitry 414 for execution.

FIG. 5 is a flow diagram illustrating an exemplary process 500 for a range-based explicit data stream processor, such as range-based explicit data stream processor 402 in FIG. 4, to communicate production values from executed producer instructions to be consumed by consumer instructions identified by range-based explicit consumer instruction naming in the executed producer instructions. By way of example, process 500 in FIG. 5 will be discussed in conjunction with the operation of processor 402 in FIG. 4.

In this regard, instruction processing circuit 404 receives from instruction memory 410 a plurality of instructions 406 in an instruction stream 411 to be executed (block 502 in fig. 5). Instruction fetch circuitry 408 in processor 402 is configured to fetch instructions 406 from instruction memory 410 and/or instruction cache 412 if instructions 406 are first fetched or prefetched into instruction cache 412. The instructions may include a plurality of producer instructions and a plurality of consumer instructions. The execution circuitry 414 executes the producer instruction 406D for the consumer instruction 406D to generate a production value, the producer instruction configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value (block 504 in fig. 5), the consumer target distance value representing a relative instruction distance from the producer instruction in the instruction stream. The execution circuitry 414 determines whether the executed producer instruction 406D includes an explicit consumer name (block 506 in fig. 5). In response to determining that the executed producer instruction 406D includes an explicit consumer name, the write circuit 432 stores the production value of the executed producer instruction 406D in the production value storage circuit 434 to at least one operand ('t') of the consumer instruction 406D, the consumer instruction 406D identified as being located at a distance from the producer instruction 406D in the instruction stream 411 by a consumer target distance value (TD +) of the executed producer instruction (block 508 in fig. 5). Responsive to at least one operand't' of the consumer instruction 406D being available in the production value storage circuitry 434, the dispatch circuitry 430 dispatches the consumer instruction 406D to be executed to the execution circuitry 414 (block 510 in fig. 5).

As discussed above in the example instruction flow 300 in FIG. 3A, explicit consumer naming based on ranges may create a WAW hazard when a conditional branch instruction is located between a producer instruction and its intended target instruction such that the relative target distance from the producer instruction may change based on whether the branch is taken or not taken. As discussed above in fig. 3A, one way to address this hazard is to provide producer instructions in the path taken by the branch, e.g., write or rewrite the produced result if the intended named consumer in the earlier producer instruction is in a path that is not taken. An example of this is shown in FIG. 3A as WAW instruction I5. However, there are other ways to construct an instruction stream that can address the WAW hazard.

In this regard, FIG. 6A is an exemplary instruction stream 600 of computer instructions I0 through I11 encoded with range-based explicit consumer instruction naming and configured for processing by a range-based data stream processor, such as processor 402 in FIG. 4. In this example instruction stream 600, there is a WAW hazard due to the conditional branch instruction I6. If the condition in the conditional branch instruction I6 is resolved as a taken branch, instruction I5 creates a WAW hazard with the producer instruction I3. The producer instruction I3 names instruction I5 as a consumer, where instruction I5 then names the consumer instruction with a target distance of '+ 2'. Instruction I6 is a conditional branch instruction after instruction I5. Thus, if a branch is taken in the conditional branch instruction I6, the production value from the execution of instruction I5 (based on consuming the production value from instruction I3) is communicated to the consumer instruction I9 instead of the expected consumer instruction I7. Thus, the WAW hazard would erroneously provide the production value from instruction I5 to the consumer instruction I9 instead of instruction I7, which is not the behavior expected by the programmer in this example.

To address such a WAW hazard in the instruction stream 600 in FIG. 6A, FIG. 6B is an alternative exemplary instruction stream 602 having instructions I0 through I12, which when executed by a range-based explicit data stream processor (such as the processor 402 in FIG. 4) performs the same intended operations of the instruction stream 600 in FIG. 6A. The instructions I0-I4 are the same between the instruction stream 602 in FIG. 6B and the instruction stream 600 in FIG. 6A. Also, the instructions I7 through I12 in the instruction stream 602 of FIG. 6B are the same instruction type as the instructions I6 through I11 in the instruction stream 600 of FIG. 6A, with the same expected operands and consumed values. To address the WAW hazard in the instruction stream 600 of FIG. 6A, the instruction stream 602 of FIG. 6B includes an additional conditional branch instruction I5 between the contents of instruction I4 and I6 in the instruction stream 600 of FIG. 6A. Also, the instruction I6 in fig. 6B (based on the instruction I5 in the instruction stream 600 in fig. 6A) is changed to the predicate instruction I6 (subtract-SUB). The predicate instruction I6 is located between the producer instruction I3 and the conditional branch instruction I7. The conditional branch instruction I5 (having the same predicate as the conditional branch instruction I7), which is a predicate producing instruction, is inserted before the predicted instruction I6 so that the predicate instruction I6 only generates a predicate producing value when the condition of the inserted conditional branch instruction I5 is resolved as not taken. The conditional branch instruction I5, which is a conditional branch instruction, is inserted at a target distance from the named consumer instruction in the producer instruction I3. In this way, the instructions in the instruction stream 602 in fig. 6A are arranged for production values from the producer instruction I2 to be valid only for the not taken flow path of the conditional branch instruction I7 to avoid the WAW hazard created by the conditional branch instruction I7.

FIG. 7 is another exemplary instruction stream 700 of computer instructions encoded with scope-based explicit consumer instruction naming and configured for processing by a scope-based data stream processor, wherein WAW hazards are addressed. As discussed below, the WAW hazard is addressed by providing instructions and encoding such that if a branch from the addressed conditional branch instruction is taken, the production value is not communicated to the unintended consumer instruction. In this regard, as shown in FIG. 7, instruction I2 is a producer instruction that indicates a target distance of '3' from instruction I2 based on a consumer designation < +3,0> designating instruction I5 as a consumer instruction. However, the instruction I4 between the producer instruction I2 and the expected consumer instruction I5 is a conditional branch instruction. In this example, the WAW hazard is addressed by providing an encoding mechanism to support invalid operands included in conditional branch instructions. An invalid operand is included in a special invalid conditional branch instruction I4, which conditional branch instruction I4 is configured to instruct the processor to invalidate a production value generated from execution of the producer instruction I2 if the conditional branch instruction I4 is resolved as a taken branch. In this way, when a branch is taken from the conditional branch instruction I4, the production value from instruction I3 is not conveyed to an unintended consumer instruction in the taken data flow path of the instruction stream 300. For example, a particular invalid conditional branch instruction may be annotated by the uniqueness or variation of the opcode of the similar conditional branch instruction.

FIG. 8 is a block diagram of an exemplary processor-based system 800, including a range-based explicit data stream processor 802 ("processor 802") configured to support execution of producer instructions encoded with range-based explicit naming of consumer instructions intended to consume values produced by producer instructions. For example, processor 802 in FIG. 8 may be processor 402 in FIG. 4. The processor-based system 800 may be one or more circuits included in an electronic board, such as a Printed Circuit Board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a Personal Digital Assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. Processor 802 represents one or more general-purpose processing circuits such as a microprocessor, central processing unit, or the like. More specifically, the processor 802 may be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for conveying production values resulting from execution of producer instructions. The processor 802 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 802 includes an instruction cache 804 and instruction processing circuitry 810 for temporary, fast-access memory storage of instructions. Instructions fetched or prefetched from memory, such as system memory 808, via system bus 806 are stored in instruction cache 804. Instruction processing circuitry 810 is configured to process instructions fetched into instruction cache 804 and process the instructions for execution. Instruction processing circuit 810 is compatible with the scope-based explicit consumer communication model and instruction encoding, such that instruction processing circuit 810 supports execution of producer instructions encoded with scope-based explicit naming of consumer instructions, such that these producer values are communicated as input values to named consumer instructions for their execution.

The processor 802 and the system memory 808 are coupled to the system bus 806 and may interconnect peripheral devices included in the processor-based system 800. As is well known, the processor 802 communicates with these other devices by exchanging address, control, and data information over the system bus 806. For example, processor 802 may communicate a bus transaction request to memory controller 812 in system memory 808 as an example of a slave device. Although not illustrated in fig. 8, a plurality of system buses 806 may be provided, each constituting a different fabric. In this example, the memory controller 812 is configured to provide memory access requests to the memory array 814 in the system memory 808. The memory array includes an array of memory bit cells for storing data. By way of non-limiting example, the system memory 808 may be Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) (such as Synchronous DRAM (SDRAM), etc.), and static memory (e.g., flash memory, Static Random Access Memory (SRAM), etc.).

Other devices may be connected to the system bus 806. As illustrated in fig. 8, these devices may include, by way of example, system memory 808, one or more input device(s) 816, one or more output device(s) 818, modem 824, and one or more display controller 820. Input device(s) 816 may include any type of input device, including but not limited to input keys, switches, speech processors, etc. Output device(s) 818 may include any type of output device including, but not limited to, audio, video, other visual indicators, and the like. The modem 824 may be any device configured to allow data to be exchanged with the network 826. Network 826 may be any type of network including, but not limited to, a wired or wireless network, a private or public network, a Local Area Network (LAN), a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), BLUETOOTH^TMNetworks and the internet. The modem 824 may be configured to support any type of communications protocol desired. The processor 802 may also be configured to access the display controller(s) 820 over the system bus 806 to control information sent to the one or more displays 822. Display(s) 822 may include any type of display including, but not limited to, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), a plasma display, and the like.

The processor-based system 800 in FIG. 8 may include an instruction set 828, which instruction set 828 may be encoded with a scope-based explicit consumer naming model for execution by the processor 802 for any application required by the instruction. The instructions 828 may be stored in the system memory 808, the processor 802, and/or the instruction cache 804 as examples of the non-transitory computer-readable medium 830. The instructions 828 may also reside, completely or at least partially, within the system memory 808 and/or within the processor 802 during execution thereof. The instructions 828 may also be transmitted or received over a network 826 via the modem 824, such that the network 826 includes a computer-readable medium 830.

While the computer-readable storage medium 830 is shown in an exemplary embodiment to be a single medium, the term "computer-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the processing device and that cause the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term "computer readable medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions, which may be used to perform the steps using a general-purpose or special-purpose processor programmed with the instructions. Alternatively, the steps may be performed by a combination of hardware and software.

Embodiments disclosed herein may be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) having stored thereon instructions that may be used to program a computer system (or other electronic devices) to perform a process according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), and so forth.

Unless specifically stated otherwise, and as is apparent from the preceding discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing," "computing," "calculating," "determining," "displaying," or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the embodiments described herein.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or combinations of both. As an example, the components of the distributed antenna systems described herein may be used in any circuit, hardware component, Integrated Circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, the controller may be a processor. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The embodiments disclosed herein may be implemented in hardware and instructions stored in hardware, and may reside, for example, in RAM, flash memory, ROM, electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It is also noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described may be performed in many different sequences other than those illustrated. Further, operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more of the operational steps discussed in the exemplary embodiments may be combined. Those of skill in the art would further appreciate that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Unless expressly stated otherwise, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Thus, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that any particular order be inferred.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and their equivalents.

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Scope-based explicit data stream processor and related computer-readable medium and method

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