阅读说明：本技术 双mcu隔离驱动mos管的电路 (Circuit for isolating and driving MOS (Metal oxide semiconductor) transistor by double MCUs (micro control units) ) 是由 张�杰 孟宪策 杨亿 张淼 马天宇 于 2021-06-04 设计创作，主要内容包括：本发明公开了一种双MCU隔离驱动MOS管的电路。包括控制驱动模块M1、推挽输出电路M2、二极管信号隔离模块M3、MOS关断快速放电模块M4、低边MOS管驱动电机模块M5；两个MCU都能控制同一个低边MOS管来驱动电机；二极管信号隔离模块M3使得单个MCU发生短路或开路故障,其不会影响另一个MCU对模块M5的控制。存在MOS管关断快速放电模块M4为MOS管栅极G端与源极S端的寄生电容提供一条就近泄放电荷的路径,使得MOS管能快速关断并且降低开关损耗。本发明解决了双MCU控制同一个低边MOS管存在双MCU之间控制信号相互干扰问题,还解决了因MOS管寄生电容放电路径过长导致MOS管关断时间较长,开关损耗大的问题。(The invention discloses a circuit for driving an MOS (metal oxide semiconductor) transistor by double MCU (micro control unit) isolation. The device comprises a control drive module M1, a push-pull output circuit M2, a diode signal isolation module M3, an MOS turn-off quick discharge module M4 and a low-side MOS tube drive motor module M5; the two MCUs can control the same low-side MOS tube to drive the motor; the diode signal isolation module M3 allows a single MCU to develop a short circuit or open circuit fault that does not affect the control of module M5 by another MCU. The MOS tube turn-off fast discharge module M4 provides a path for discharging charge nearby for parasitic capacitance of the gate G and the source S of the MOS tube, so that the MOS tube can be turned off fast and switching loss is reduced. The invention solves the problem that the mutual interference of control signals between the double MCUs exists when the double MCUs control the same low-side MOS tube, and also solves the problems of longer MOS tube turn-off time and large switching loss caused by overlong parasitic capacitance discharge path of the MOS tube.)

1. The utility model provides a circuit of drive MOS pipe is kept apart to two MCU which characterized in that:

the device mainly comprises five parts, namely a control driving module M1 consisting of double MCUs, a push-pull output circuit M2, a diode signal isolation module M3, an MOS turn-off quick discharge module M4 and a low-side MOS tube driving motor module M5;

the control driving module M1 comprises an MCU1 and an MCU2, wherein a control port GPIO1 of the MCU1 is connected to a gate G of a MOS transistor Q8 in the push-pull output circuit M2, a control port GPIO2 of the MCU2 is connected to a gate G of a MOS transistor Q9 in the push-pull output circuit M2, and the MCU1 is in communication connection with the MCU 2; the push-pull output circuit M2 comprises MOS tubes Q4-Q9, wherein the drain D of the MOS tube Q4 is connected to a power supply VBAT1, the source S of the MOS tube Q4 is respectively connected to the drain D of the MOS tube Q5 and the anode A of a diode D4 of a diode signal isolation module M3, the source S of the MOS tube Q5 is grounded, the drain D of the MOS tube Q8 is respectively connected to the gates g of the MOS tube Q4 and the MOS tube Q5, and the drain D of the MOS tube Q8 is connected to the power supply VBAT1 through a resistor R6; the drain D of the MOS transistor Q6 is connected to the power source VBAT1, the source S of the MOS transistor Q6 is connected to the drain D of the MOS transistor Q7 and the anode a of the diode D6 of the diode signal isolation module M3, the source S of the MOS transistor Q7 is grounded, the drain D of the MOS transistor Q9 is connected to the gate g of the MOS transistor Q6 and the gate g of the MOS transistor Q7, and the drain D of the MOS transistor Q9 is connected to the power source VBAT1 through the resistor R7;

the diode signal isolation module M3 includes a diode D4 and a diode D6, wherein the cathode C of the diode D4 and the diode D6 are both connected between the resistor R1 and the resistor R2 of the MOS turn-off fast discharge module M4; the MOS turn-off quick discharge module M4 comprises resistors R1-R5 and triodes Q1 and Q2; a resistor R4, a diode D3, a resistor R1 and a resistor R2 are sequentially connected in series between a base b and a collector c of a triode Q1, a resistor R2 is connected between the base b and an emitter e of a triode Q1, a resistor R5 is connected between the collector c and the emitter e of the triode Q2, a base b of a triode Q2 is connected with a collector c of the triode Q1, a resistor R4 and the diode D3 are led out and connected with the collector c of a triode Q2, the triode Q1 and the emitter e of the triode Q2 are grounded, and the collector c of the triode Q2 is connected with the control end of the motor MG of the low-side MOS tube driving motor module M5;

the low-side MOS tube driving motor module M5 comprises a motor MG and a MOS tube Q3, wherein the source end s of the MOS tube Q3 is grounded, the drain electrode d of the MOS tube Q3 is connected with the No. 2 pin of the motor MG, and the No. 1 pin of the motor MG is connected with a power supply VBAT 2.

2. The circuit of claim 1, wherein the double-MCU isolation driving MOS transistor comprises: the diode D4, the diode D6 and the diode D3 are Schottky diodes.

3. The circuit of claim 1, wherein the double-MCU isolation driving MOS transistor comprises: the MOS transistors Q4 and Q6 are PMOS transistors, the MOS transistors Q5, Q7, Q8 and Q9 are NMOS transistors, the triodes Q1 and Q2 are NPN type transistors, and the MOS transistor Q3 is a power NMOS transistor.

4. The circuit of claim 1, wherein the double-MCU isolation driving MOS transistor comprises: the motor MG is a direct current brush motor.

5. The circuit of claim 1, wherein the double-MCU isolation driving MOS transistor comprises: the control port GPIO1 of the MCU1 and the control port GPIO2 of the MCU2 both drive and output a high level of 5V and a low level of 0V, and the voltages of the power VBAT1 and the power VBAT2 are + 12V.

6. The circuit of claim 1, wherein the double-MCU isolation driving MOS transistor comprises: the layout of the MOS turn-off quick discharge module M4 is arranged close to the low-side MOS tube driving motor module M5.

Technical Field

The invention belongs to a driving circuit for a vehicle-mounted motor in the field of automotive electronics, and particularly relates to a circuit for driving an MOS (metal oxide semiconductor) tube by isolating double MCUs (micro control units).

Background

A common motor driving circuit hardware framework adopts a single MCU to send out a control signal, and then controls the on and off of a power MOS tube to control a vehicle-mounted motor. However, as the requirements of vehicle-mounted electronics on functional safety are continuously increased, when a single MCU fails to control the operation state of the vehicle-mounted motor due to the fact that the single MCU is exposed to the hardware architecture, a hazard may occur.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides a circuit for driving an MOS tube by double-MCU isolation, which solves the problem that control signals between double MCUs interfere with each other when the double MCUs control the same low-side MOS tube in a vehicle-mounted motor, and also solves the problems of long MOS tube turn-off time and large switching loss caused by overlong parasitic capacitance discharge path of the MOS tube.

The technical scheme adopted by the invention is as follows:

the circuit structure of the invention can drive the motor by controlling the same low-side MOS tube through two MCUs. The diode signal isolation module M3 allows a single MCU to develop a short circuit or open circuit fault that does not affect the control of module M5 by another MCU. The MOS tube turn-off fast discharge module M4 provides a path for discharging charge nearby for parasitic capacitance of the gate G and the source S of the MOS tube, so that the MOS tube can be turned off fast and switching loss is reduced.

When the system normally operates, the MCU1 is used as a main control unit, and the MCU2 is used as a monitoring unit. The MCU2 monitors the running state of the MCU1 through the SPI protocol, and at the moment, the MCU1 controls the running state of the motor. When the system is abnormal, the MCU2 monitors the data abnormality, the RST pin of the MCU2 outputs a high potential to reset the MCU1, and the MCU2 is used as a main control unit to control the operation of the motor. The double MCUs are isolated by the diodes, and mutual interference of driving signals of the two MCUs is effectively prevented. Meanwhile, a path for discharging charge nearby is designed for a parasitic capacitor between the grid source GS of the power NMOS tube on the circuit hardware architecture, so that the MOS tube can be quickly turned off, and the switching loss is reduced.

The invention has the beneficial effects that:

the invention realizes that two MCUs drive the same low-side MOS tube, and solves the problem of harm caused by single-point failure of an independent MCU. The simultaneous presence of the MOS off fast discharge module M4 reduces the risk of MOS transistor damage.

Drawings

FIG. 1 is a circuit diagram of a dual MCU isolation driving MOS transistor according to the present invention;

Detailed Description

The invention is further described below with reference to the accompanying drawings:

as shown in fig. 1, the driving circuit mainly comprises five parts, namely a control driving module M1 composed of two MCUs, a push-pull output circuit M2, a diode signal isolation module M3, a MOS turn-off fast discharge module M4, and a low-side MOS transistor driving motor module M5.

The control driving module M1 includes an MCU1 and an MCU2, wherein a control port GPIO1 of the MCU1 is connected to a gate G of an MOS transistor Q8 in the push-pull output circuit M2, a control port GPIO2 of the MCU2 is connected to a gate G of an MOS transistor Q9 in the push-pull output circuit M2, the MCU1 is in communication connection with the MCU2, a communication mode between the MCU1 and the MCU2 adopts an SPI protocol (serial peripheral interface), the MCU2 is connected to the MCU1 through an RST pin, and the MCU2 resets the MCU1 through the RST pin;

the push-pull output circuit M2 comprises MOS tubes Q4-Q9, wherein the drain D of the MOS tube Q4 is connected to a power supply VBAT1, the source S of the MOS tube Q4 is respectively connected to the drain D of the MOS tube Q5 and the anode A of a diode D4 of a diode signal isolation module M3, the source S of the MOS tube Q5 is grounded, the drain D of the MOS tube Q8 is respectively connected to the gates g of the MOS tube Q4 and the MOS tube Q5, and the drain D of the MOS tube Q8 is connected to the power supply VBAT1 through a resistor R6; the drain D of the MOS transistor Q6 is connected to the power source VBAT1, the source S of the MOS transistor Q6 is connected to the drain D of the MOS transistor Q7 and the anode a of the diode D6 of the diode signal isolation module M3, the source S of the MOS transistor Q7 is grounded, the drain D of the MOS transistor Q9 is connected to the gate g of the MOS transistor Q6 and the gate g of the MOS transistor Q7, and the drain D of the MOS transistor Q9 is connected to the power source VBAT1 through the resistor R7.

The diode signal isolation module M3 includes a diode D4 and a diode D6, wherein the cathode C of the diode D4 and the diode D6 are both connected between the resistor R1 and the resistor R2 of the MOS turn-off fast discharge module M4, i.e., point E in fig. 1; the MOS turn-off quick discharge module M4 comprises resistors R1-R5 and triodes Q1 and Q2; a resistor R4, a diode D3, a resistor R1 and a resistor R2 are sequentially connected in series between a base b and a collector C of a triode Q1, an anode A of a diode D3 is connected with a resistor R1, a cathode C is connected with a resistor R4, the resistor R2 is connected between a base b and an emitter e of a triode Q1, a resistor R5 is connected between a collector C and an emitter e of a triode Q2, a base b of the triode Q2 is connected with a collector C of a triode Q1, the resistor R4 is led out from the diode D3 and is connected with a collector C of a triode Q2, the triode Q1 and the emitter e of the triode Q2 are grounded, and a collector C of a triode Q2 is connected with a control end of a motor MG of a low-side MOS tube driving motor module M5;

specifically, two ends of the resistors R1-R5 are divided into a pin 1 and a pin 2, the pin 2 of the resistor R1 is connected to the anode a of the diode D3, and the cathode C of the diode D3 is connected to the pin 2 of the resistor R4, the collector C of the triode Q2, the pin 2 of the resistor R5, and the gate g of the MOS transistor Q3, and is connected to the point D. Pin 1 of the resistor R2 is connected with pin 2 of the resistor R3 and pin b of the base of the triode Q1, and the collector c of the triode Q1 is connected with pin 1 of the resistor R4 and the base b of the triode Q2 to be connected with a point F. The emitter e of transistor Q2 is grounded and the emitter e of transistor Q1 is grounded. Pin 1 of resistor R3 is connected to ground, and pin 1 of resistor R5 is connected to ground.

The low-side MOS tube driving motor module M5 comprises a motor MG and a MOS tube Q3, wherein the source end s of the MOS tube Q3 is grounded, the drain electrode d of the MOS tube Q3 is connected with the No. 2 pin of the motor MG, and the No. 1 pin of the motor MG is connected with a power supply VBAT 2.

The control port GPIO1 of the MCU1 and the control port GPIO2 of the MCU2 both drive and output 5V at a high level and 0V at a low level, and the voltage of the power supply VBAT1 and the power supply VBAT2 is +12V, and the vehicle-mounted storage battery supplies power.

In the wiring layout, the MOS off fast discharge module M4 device is placed next to the low side MOS transistor drive motor module M5.

When the system normally operates, the MCU1 is used as a main control unit, and the MCU2 is used as a monitoring unit. The MCU2 monitors the running status of the MCU1 via the SPI protocol (serial peripheral interface), when the MCU1 sends abnormal data, the MCU2 will act as a master control unit, and the MCU2 resets the MCU1 via the RST pin.

When the reset pin of the MCU2 outputs a high (+5V) level, the MCU1 enters a reset state.

As shown in fig. 1, the specific working process of the present invention is as follows:

when the system works normally, the MCU1 is a main control unit, the MCU2 is a monitoring unit, and the MCU2 confirms that the MCU1 is in a normal operation state through data transmitted by the SPI protocol.

The MCU1 drives the motor MG to operate:

the GPIO1 of the MCU1 outputs a voltage of 5V, and at this time, the NMOS transistor Q8 in the push-pull output module M2 is turned on, the potential at the Y point is 0V, the PMOS transistor Q4 is turned on, and the NMOS transistor Q5 is turned off. The potential at point a of the diode D4 is VBAT1(+12V), and the voltage at point a is applied to the junction E between pin 1 of the resistor R1 and pin 2 of the resistor R2 through the diode D4.

The voltage at E is divided into two paths, one path of which is divided by resistors R2 and R3 to turn on the transistor Q1 (Vbe >0.7V), and the potential at F is pulled down to ground, thereby turning off the transistor Q2 (Vbe < 0.7V).

The other path of voltage is loaded to the position D through the resistor R1 and the diode D3, the potential of the point D is VBAT1(+12V) because the triode Q2 is cut off, the VGS voltage of the power MOS tube Q3 is VBAT1(+12V) and is larger than the threshold voltage 3V, the MOS tube Q3 is conducted, the pin No. 2 of the motor MG is grounded, and the motor is enabled to operate.

The MCU1 controls to stop the motor MG to run:

the GPIO1 of the MCU1 outputs a voltage of 0V, the NMOS transistor Q8 is turned off, the potential at the Y point is VBAT1(+12V), the PMOS transistor Q4 in the push-pull output module M2 is turned off, and the NMOS transistor Q5 is turned on, so that the potential at the a point of the diode D4 is 0V, and the potential at the a point is loaded to the intersection of the pin No. 1 of the resistor R1 and the pin No. 2 of the resistor R2 through the diode D4 and is 0V. At this time, the triode Q1 is cut off (Vbe <0), the parasitic capacitance discharge path between the gate source GS of the power MOS transistor Q3 is divided into two paths, one path discharges charges through the resistor R5, the other path discharges charges through the diode D3 in the reverse direction, so that charges at the point D can only reach the point F through the resistor R4, and the triode Q1 is cut off when the GPIO1 drives and outputs 0V voltage, so that the triode Q2 is turned on (Vbe >0.7V) to turn on the triode Q2 to be grounded, thereby accelerating the discharge of parasitic capacitance charges of the power MOS transistor Q3. Through the two paths, the MOS tube Q3 can be quickly switched off, and the switching loss is reduced.

When the system does not work normally, the MCU2 monitors the data transmitted by the MCU1 through the SPI protocol to be abnormal. At this time, the MCU2 will act as a master and the MCU2 resets the MCU1 via the RST pin. Due to the existence of the diode signal isolation module M3, a short circuit or open circuit failure of the MCU1 does not affect the control signal logic voltage of the MCU 2. The control logic of the MCU2 for the motor MG is identical to that of the MCU1 for the motor MG mentioned above.

Other embodiments of the present invention than the preferred embodiments described above, and those skilled in the art can make various changes and modifications according to the present invention without departing from the spirit of the present invention, should fall within the scope of the present invention defined in the claims.

It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.