阅读说明：本技术 用于带内载波聚合的接收器前端架构 (Receiver front-end architecture for in-band carrier aggregation ) 是由 G·拉简德兰 G·S·萨霍塔 R·库马 于 2015-09-30 设计创作，主要内容包括：公开了一种用于带内载波聚合的接收器前端架构。在示例性实施例中,一种装置包括第一晶体管,第一晶体管具有接收输入信号的栅极端子、输出放大信号的漏极端子、以及通过源极退化电感器连接至信号地的源极端子。该装置还包括第二晶体管,第二晶体管具有连接至第一晶体管的漏极端子的源极端子和连接至第一负载的漏极端子。该装置还包括第三晶体管,第三晶体管具有连接至第一晶体管的漏极端子的栅极端子、连接至第二负载的漏极端子和连接至信号地的源极端子。(A receiver front end architecture for in-band carrier aggregation is disclosed. In an example embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, a drain terminal to output an amplified signal, and a source terminal connected to a signal ground through a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to the second load, and a source terminal connected to signal ground.)

1. An electronic device, comprising:

a first transistor having a gate terminal configured to receive an input signal, a drain terminal configured to output an amplified signal, and a source terminal connected to a signal ground through a source degeneration inductor;

a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first signal path; and

a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second signal path, and a source terminal connected to the signal ground,

wherein the drain terminal of the third transistor is selectively connected to the first signal path through a switch.

2. The electronic device of claim 1, further comprising: a fourth transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first signal path, the fourth transistor configured to conduct the same or a different amount of current than the second transistor.

3. The electronic device of claim 2, the fourth transistor selectively enabled or biased by a control signal for DC coupling to control current to a first load connected to the first signal path.

4. The electronic device of claim 1, further comprising one or more additional transistors having one or more gate terminals respectively connected to the drain terminals of the first transistors, one or more drain terminals respectively connected to one or more signal paths, and one or more source terminals connected to the signal ground.

5. The electronic device of claim 4, the one or more drain terminals selectively connected to the one or more signal paths through one or more switches.

6. The electronic device of claim 5, the one or more switches selectively enabled by one or more control signals.

7. The electronic device of claim 4, the drain terminal of the one or more additional transistors selectively connected to the first signal path through one or more switches.

8. The electronic device of claim 7, the one or more switches selectively enabled by one or more control signals.

9. The electronic device of claim 1, the second transistor selectively enabled or biased for DC coupling by a control signal.

10. The electronic device of claim 1, the drain terminal of the third transistor selectively connected to the second signal path through a switch.

11. The electronic device of claim 10, the switch selectively enabled or biased for DC coupling by a control signal.

12. The electronic device of claim 4, wherein the first signal path connects the drain terminal of the second transistor to a first load, the second signal path connects the drain terminal of the third transistor to a second load, and the one or more signal paths respectively connect the drain terminals of the one or more additional transistors to one or more loads.

13. The electronic device of claim 4, wherein the first signal path comprises a primary signal path, and the second signal path and one or more signal paths comprise carrier aggregation signal paths.

14. The electronic device of claim 1, the switch selectively enabled by a control signal.

15. The electronic device of claim 1, further comprising a controller to generate control signals to selectively enable the second and third transistors or to bias the second and third transistors for DC coupling.

16. The electronic device of claim 1, configured to perform configurable amplification and routing of carrier aggregated signals in a receiver.

17. The electronic device of claim 1, formed on an integrated circuit.

18. The electronic device of claim 1, further comprising an additional transistor having a gate terminal connected to the drain terminal of the third transistor, a drain terminal connected to an additional signal path, and a source terminal connected to the signal ground.

19. The electronic device of claim 18, the drain terminal of the further transistor selectively connected to the first signal path through a switch.

20. The electronic device of claim 19, the switch selectively enabled by a control signal.

21. The electronic device of claim 18, wherein the further transistor is one of a plurality of further transistors, each transistor of the plurality of further transistors having a gate terminal, a source terminal, and a drain terminal, wherein the plurality of further transistors form a chain such that the gate terminals of the plurality of transistors are coupled to a drain terminal of a respective preceding transistor, wherein the drain terminals of the plurality of transistors are coupled to a respective signal path, and wherein the source terminals of the plurality of transistors are connected to the signal ground.

22. The electronic device of claim 21, wherein the first signal path comprises a primary signal path, and the second and respective signal paths comprise carrier aggregated signal paths.

23. An electronic device, comprising:

means for generating a control signal that controls how a signal is amplified and routed to one or more signal paths, the signal being output from a first transistor having a source terminal connected by a source degeneration inductor to signal ground;

means for selectively connecting the signal to a first signal path based on the control signal; and

means for connecting the signal to a second signal path comprising a transistor receiving the signal at a gate terminal and having a source terminal connected to the signal ground.

24. The electronic device of claim 23, further comprising: second means for selectively connecting the signal to the first signal path based on the control signal, the second means for selectively connecting the signal to the first signal path configured to conduct the same or a different amount of current than the means for selectively connecting the signal to the first signal path.

25. The electronic device of claim 23, further comprising: means for connecting the signal to one or more further signal paths comprising one or more further transistors connected to receive the signal at one or more further gate terminals and having one or more further source terminals connected to the signal ground.

26. The electronic device of claim 25, further comprising: means for selectively connecting the one or more further signal paths to the first signal path based on the control signal.

27. The electronic device of claim 25, further comprising: means for selectively connecting the second signal path to a load based on the control signal, and means for selectively connecting the one or more further signal paths to one or more loads, respectively.

28. The electronic device of claim 23, further comprising: means for connecting the second signal path to a third signal path comprising a transistor having a gate terminal connected to the second signal path and a source terminal connected to the signal ground.

29. The electronic device of claim 23, wherein the first signal path comprises a primary signal path and the second signal path comprises a carrier aggregation signal path.

30. A method for operating an electronic device, comprising:

generating a control signal that controls how a signal is amplified and routed to one or more signal paths, the signal being output from a first transistor having a source terminal connected by a source degeneration inductor to signal ground;

selectively connecting the signal to a first signal path based on the control signal; and

the signal is connected to a second signal path through a transistor that receives the signal at a gate terminal and has a source terminal connected to the signal ground.

Technical Field

The present disclosure relates generally to electronics, and more particularly to configurable routing of radio frequency signals in wireless devices.

Background

A wireless device (e.g., a cellular telephone or smartphone) in a wireless communication system may transmit and receive data for two-way communication. For example, the wireless device may be in an operating Frequency Division Duplex (FDD) system or a Time Division Duplex (TDD) system. A wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may modulate a Radio Frequency (RF) carrier signal with data to obtain a modulated RF signal, amplify and filter the modulated RF signal to obtain an amplified RF signal having the proper output power level, and transmit the amplified RF signal via the antenna to the base station. For data reception, the receiver may obtain a received RF signal via the antenna and may amplify, filter, and process the received RF signal to recover the data transmitted by the base station.

Wireless devices may support operation over a wide frequency range. For example, a wireless device may operate in a Carrier Aggregation (CA) communication system, where the device includes a front end that receives multiple Downlink (DL) carrier signals over a wide frequency range. The front end operates to amplify the received carrier signals and route them to the appropriate demodulator for demodulation. Unfortunately, conventional front ends may utilize multiple amplifiers, each with a degeneration (degeneration) inductor. The large size of these inductors means that conventional front-ends utilize significant circuit area. Furthermore, if amplifiers used to amplify multiple carrier signals are spread across multiple chips, it may be difficult to compensate for various gain and circuit routing losses that may arise.

It is therefore desirable to have a front-end architecture in a carrier aggregation receiver that provides efficient amplification and routing of received signals. The front-end should operate to maintain excellent linearity, provide compensation for gain and routing losses, and reduce or minimize circuit area requirements relative to conventional front-ends.

Drawings

Fig. 1 illustrates an exemplary embodiment of a front end architecture for use in a wireless device communicating within a wireless system.

Fig. 2 illustrates three exemplary band groups in which an exemplary embodiment of the front-end architecture illustrated in fig. 1 may operate.

Fig. 3 illustrates a receiver including an exemplary embodiment of a front-end architecture that provides configurable RF signal amplification and routing.

Fig. 4 shows a detailed exemplary embodiment of the front-end architecture shown in fig. 3.

Fig. 5 shows a detailed alternative exemplary embodiment of the front end architecture shown in fig. 3.

FIG. 6 illustrates an exemplary embodiment of a controller for use with the front end architecture shown in FIG. 4.

Fig. 7 illustrates exemplary operations performed by an exemplary embodiment of a front end architecture to provide RF signal amplification and routing in a receiver front end.

Fig. 8 illustrates an exemplary embodiment of a table showing control signal settings for various signal amplification and routing configurations for use with the front end architectures shown in fig. 4 and 5.

Fig. 9 illustrates an exemplary embodiment of an apparatus for RF signal amplification and routing in a carrier aggregation receiver.

Detailed Description

The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure may be practiced. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to one skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary design presented herein.

A novel receiver front end architecture is disclosed herein that provides configurable RF signal amplification and routing in a device to demodulate multiple carrier signals over a wide frequency range covering multiple band groups. The receiver front-end architecture is suitable for use in various types of electronic devices, such as wireless communication devices.

Fig. 1 illustrates an exemplary embodiment of a front end architecture 112 for use in a wireless device 110 communicating within a wireless system 120. The wireless system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a global system for mobile communications (GSM) system, a Wireless Local Area Network (WLAN) system, or some other wireless system. A CDMA system may implement wideband CDMA (wcdma), CDMA 1X, evolution-data optimized (EVDO), time division synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, fig. 1 shows a wireless system 120 that includes two base stations 130 and 132 and a system controller 140. In general, wireless system 120 may include any number of base stations and any set of network entities.

Wireless device 110 may also be referred to as a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. The wireless device 110 may be a cellular phone, a smart phone, a tablet, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop, a smartbook, a netbook, a cordless phone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. Wireless device 110 may communicate with devices in wireless system 120. Wireless device 110 may also receive signals from a broadcast station (e.g., broadcast station 134), or from satellites in one or more Global Navigation Satellite Systems (GNSS), such as satellite 150. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11. In an exemplary embodiment, wireless device 110 includes a receiver Front End (FE) architecture 112 to provide RF carrier signal amplification and routing when receiving multiple carriers in a carrier aggregation communication system. FE 112 is designed to utilize fewer amplifier degeneration inductors relative to conventional front end designs to reduce circuit area requirements and provide better compensation for gain/routing losses.

Fig. 2 illustrates three exemplary band groups in which the exemplary embodiment of FE 112 illustrated in fig. 1 may operate. Wireless device 110 may operate in a low frequency band (LB) covering frequencies below 1000 megahertz (MHz), a mid frequency band (MB) covering frequencies from 1000MHz to 2300MHz, and/or a high frequency band (HB) covering frequencies above 2300 MHz. For example, as shown in fig. 2, the low frequency band may cover 698 to 960MHz, the middle frequency band may cover 1475 to 2170MHz, and the high frequency band may cover 2300 to 2690MHz and 3400 to 3800 MHz. The low, intermediate, and high frequency bands refer to three groups (or band groups) of frequency bands, each band group including a plurality of frequency bands (or simply, "frequency bands"). Each band may cover up to 200 MHz. LTE release 11 supports 35 bands, which are referred to as LTE/UMTS bands and are listed in 3GPP TS 36.101.

In general, any number of band groups may be defined. Each band group may cover any range of frequencies that may or may not match any of the frequency ranges shown in fig. 2. Each band group may also include any number of bands. In various exemplary embodiments, FEs 112 are adapted to receive, amplify and demodulate carrier signals in any of the frequency bands in which device 110 may operate.

Fig. 3 shows a receiver 300 including an exemplary embodiment of a front-end architecture that provides configurable RF signal path amplification and routing. For example, the receiver 300 is suitable for use in amplifying and routing received carrier signals in a carrier aggregation communication system. Receiver 300 includes receive antenna 302, matching circuit 304, Signal Amplification and Routing Circuit (SARC)306, controller 308, primary load circuit 310, first carrier aggregation ("CA 1") load circuit 312, one or more additional carrier aggregation load circuits (not shown), and nth carrier aggregation ("CAn") load circuit 314. In an exemplary embodiment, each load circuit 310 and 314 includes a separate demodulation circuit.

During operation, RF signals are received by receive antenna 302. For example, the RF signal may include any one of the bands or groups of bands illustrated in fig. 2. The received RF signals are routed by the SARC 306 to any combination of output loads 310 and 314 in accordance with control signals 316 provided to the SARC 306 from the controller 308. In an exemplary embodiment, the control signal 316 is set to a first logic voltage level for a first signal path routing configuration and the control signal 316 is set to a second logic voltage level for a second signal path routing configuration.

Although not illustrated in fig. 3, the controller 308 may be dynamically programmed by a baseband processor within the wireless device. For example, the baseband processor provides configuration parameters 318 to the controller 308 to program the operation of the controller 308. In an exemplary embodiment, a baseband processor included in the wireless device will use the controller 308 to alter the signal routing of the received RF signals depending on the carrier aggregation mode in which the wireless device is operating.

Fig. 4 illustrates a detailed exemplary embodiment of the SARC 306 used in the front-end architecture shown in fig. 3. The SARC 306 includes a first common-source amplifier 402, the first common-source amplifier 402 including a transistor (T1), the transistor (T1) having a gate terminal 404 that receives an input signal 406 through an inductor 448, a source terminal 408 connected with a source degeneration inductor 410 that is further connected to signal ground, and a drain terminal 412 that outputs an amplified version of the input signal. Thus, the first common-source amplifier 402 is implemented using transistor T1 and source degeneration inductor L1.

The SARC 306 also includes a first cascode amplifier 414, the first cascode amplifier 414 including a transistor (T3), the transistor (T3) having a source terminal 416 connected to the drain terminal 412, and a drain terminal 418 connected to the main load 420 through the main signal path. The first cascode amplifier 414 also includes a gate terminal 422 selectively connected to a voltage level (vbc) through a switch 424. Thus, the first cascode amplifier 414 is implemented using the transistor T3. The switch 424 receives a control signal Sa from the controller 308, which controls the switch 424 to selectively input a zero voltage level or a vbc voltage level to the gate terminal 422. In an exemplary embodiment, the vbc voltage level is typically 1.2 volts. In another exemplary embodiment, the vbc voltage level is set to bias any of the transistor devices to any desired bias setting or for DC coupling.

The SARC 306 further includes a second common-source amplifier 426, the second common-source amplifier 426 including a transistor (T2)₁) Transistor (T2)₁) Having a gate terminal 428 connected to drain terminal 412 and a drain terminal 430 connected to source terminal 458 of switch 432 through the CA1 signal path. Switch 432 includes a transistor (T5)₁) And has a drain terminal 456 connected to the second load 434. Thus, the second common-source amplifier 426 uses the transistor T2₁Is implemented. It should be noted that unlike the first common-source amplifier 402 using the source degeneration inductor 410, the second common-source amplifier 426 is configured without a source degeneration inductor. Thus, the transistor T2₁Is directly connected to signal ground. Switch 432 includes a gate terminal 460 selectively connected to a voltage level vbc through a switch 462.

The SARC 306 further includes a second cascode amplifier 436, a second cascodeThe gate amplifier 436 includes a transistor (T3 '), a transistor (T3') having a source terminal 438 connected to the first drain terminal 412, and a drain terminal 440 connected to the drain terminal 418 of the transistor T3 and to the drain terminal 450 of the switch 442. The second cascode amplifier 436 has a gate terminal 446 selectively connected to a voltage level vbc through a switch 444. Thus, the second cascode amplifier 436 is implemented using the transistor T3'. In an exemplary embodiment, the first cascode amplifier 414 is configured to conduct more current than the second cascode amplifier 436, which is accomplished by appropriate sizing of the transistors T3 and T3' to achieve the desired current conducting characteristics. The switch 442 includes a transistor (T4)₁) Transistor (T4)₁) Includes a source terminal 452, the source terminal 452 being connected to the CA1 signal path and thereby to transistor T2₁Drain terminal 430 and transistor T5₁Source terminal 458. Switch 442 includes a gate terminal 464 selectively connected to a voltage level vbc through switch 454. In an exemplary embodiment, the transistor T3 is divided into transistors (T3+ T3 ') so that in the carrier aggregation mode, the transistor T3' may be turned off to increase the impedance seen at the drain of the transistor T1. This increases the gain at the drain of the transistor T1, which is input to the transistor (T2 n). This helps to reduce the noise contribution from the transistor (T2 n).

In addition to amplifying and routing received RF signals to the primary load 420 and the CA1 loads 434, the SARC 306 may be configured to amplify and route received RF signals to any number of additional CA loads. The following is a description of a configuration in which SARC 306 amplifies the received RF signal and routes it to the nth CA load. It should be noted that a similar circuit structure may be used to amplify and route a received RF signal to any number of CA loads between the first CA load and the nth CA load.

The SARC 306 includes an nth common-source amplifier 466, the nth common-source amplifier 466 including a transistor (T2)_n) Transistor (T2)_n) Has a gate terminal 468 connected to the drain terminal 412, and passes through CA_nThe signal path is connected to the drain terminal 47 of the source terminal 472 of the switch 4740. Switch 474 includes a transistor (T5)_n) And has a drain terminal 476 connected to an nth load 478. Thus, the nth common-source amplifier 466 uses the transistor T2_nIs implemented. It should be noted that additional common-source amplifiers up to and including the nth common-source amplifier 466 do not utilize a source degeneration inductor as the first common-source amplifier 402 using the degeneration inductor 410. Switch 474 includes a gate terminal 480 that is selectively connected to a voltage level (vbc) through a switch 482.

The SARC 306 includes a switch 484, the switch 484 including a transistor (T4)_n) Transistor (T4)_n) Has a source terminal 486, the source terminal 486 is connected to CA_nThe signal path and thus to the drain terminal 470 and the source terminal 472. A drain terminal 488 of the switch 484 is connected to the drain terminal 418. The gate terminal 490 of the switch 484 is selectively connected to the voltage level vbc through the switch 492.

During operation, the controller 308 generates a plurality of control signals. In an exemplary embodiment, each control signal is a logic low voltage level or a logic high voltage level. The control signal "Sa" output from controller 308 is coupled to switch 424 and controls the voltage level at the gate terminal 422 of transistor T3. When the control signal "Sa" is a logic low voltage level, a zero volt signal is input to the gate terminal 422 and the first cascode amplifier 414 is turned off. As a result, the input signal 406 is not coupled to the drain terminal 418 through the transistor T3. Alternatively, when the control signal "Sa" is a logic high voltage level, the vbc voltage level is input to the gate terminal 422 and the first cascode amplifier 414 is turned on. As a result, the input signal 406 is coupled to the drain terminal 418 through the transistor T3. The signal at the drain terminal 418 is then passed through the main signal path to the main load 420. At the primary load 420, the signal is coupled through a transformer to a demodulator that demodulates the signal based on the selected local oscillator signal to generate a primary baseband (BB) signal.

The control signal "Sb" generated by the controller 308 is coupled to control the switch 444, which controls the voltage level at the gate terminal 446 of the transistor T3'. When the control signal "Sb" is a logic low voltage level, the switch 444 inputs zero volts into the gate terminal 446 and the second cascode amplifier 436 is turned off so that the amplified input signal at terminal 412 is not coupled to the drain terminal 440 of the transistor T3'. Alternatively, when the control signal "Sb" is a logic high voltage level, the switch 444 inputs vbc volts to the gate terminal 446, so that the second cascode amplifier 436 is turned on. As a result, the amplified input signal at terminal 412 is coupled to the drain terminal 440 of transistor T3' and to the main signal path.

The control signal "s (n)" is generated by the controller 308. Signal S1 is coupled to control switch 454 associated with the CA1 signal path. The control signal s (n) is further coupled to control further corresponding switches associated with further signal paths. For example, the signal S_nIs coupled to control and CA_nThe signal path associated with switch 492. Thus, the control signal s (n) controls the voltage level at the gate terminal of the corresponding transistor T4(n) in the CA signal path. For example, when control signal "S1" is a logic low voltage level, switch 442 is turned off (i.e., open circuit) and there is no connection between the CA1 signal path and the main signal path. Alternatively, when control signal "S1" is a logic high voltage level, switch 442 is turned on (i.e., closed) and a connection between the CA1 signal path and the main signal path is established. This operation of the s (n) control signal is the same for any further CA signal paths that may be utilized. For example, if the control signal S_nIs a logic high voltage level, switch 484 is turned on (i.e., closed) and CA_nA connection between the signal path and the main signal path is established.

The control signal "se (n)" is generated by the controller 308. Control signal se (n) is coupled to control the switches to determine the input voltage to the gate terminals of the switches connecting the CA signal paths to their associated output loads. For example, control signal SE1 is coupled to control switch 462 to determine the voltage level input to gate terminal 460 of switch 432. When the control signal "SE 1" is a logic low voltage level, zero volts is input to the gate terminal 460 to turn off the switch 432 (e.g., open) and the path between the CA1 signal path and the output load 434 is opened. Alternatively, when the control signal "SE 1" is a logic high voltage level, vbc volts is input to the gate terminal 460 of switch 432 (e.g., closed circuit) and the path between the CA1 signal path and the output load 434 is opened. Control signal se (n) operates to control the other corresponding switches in any further CA signal paths in a similar manner.

First mode of operation-primary load only

It may be advantageous to couple the input signal 406 only to the main output load 420 when performing carrier aggregation. To couple the input signal 406 only to the main load 420, one or both of the first and second cascode amplifiers 414 and 436 are turned on by operation of the Sa and Sb control signals. Further, control signal se (n) is set such that zero volts is input to the gate terminals of the associated (T5(n)) switches, thereby opening those switches to prevent coupling of input signal 406 to other CA loads. Turning on one or the other of the first and second cascode amplifiers 414 and 436 will set the selected gain level. Turning on both the first cascode amplifier 414 and the second cascode amplifier 436 maximizes the gain applied to the input signal 406 before the input signal 406 is coupled to the main load 420.

Second mode of operation-primary load and one or more CA loads

It may be advantageous to couple the input signal 406 to the main output load 420 and one or more CA loads when performing carrier aggregation. For example, the main load operates to demodulate the first carrier signal and the one or more further CA loads operate to demodulate one or more further carrier signals. To couple the input signal 406 to the main load 420, at least one of the first cascode amplifier 414 and the second cascode amplifier 436 is turned on by operation of the Sa and Sb control signals. To couple the input signal to one or more CA loads, control signal se (n) is set such that vbc volts is input to the gate terminals of the associated (T5(n)) switches, thereby closing those switches to allow coupling of input signal 406 to the associated CA loads. Turning on both the first cascode amplifier 414 and the second cascode amplifier 436 maximizes the gain applied to the input signal 406 before the input signal 406 is coupled to the main load 420.

Third mode of operation-first load connected to main load

It may be advantageous to couple the first output load 434 to the main output load 420 when performing carrier aggregation. To couple the first output load 434 to the main output load 420, the control signals S1 and SE1 are set such that both the first switch 432 and the second switch 442 are closed. In the event that either the first switch 432 or the second switch 442 is opened, the first output load 434 will be disconnected from the main output load 420. Decoupling the input signal from the main output load 420 may be advantageous when coupling the first output load 434 to the main output load 420. To prevent coupling of the input signal to the main output load 420, the first and second cascode amplifiers 414 and 436 are turned off.

Fig. 4 further illustrates how the switch 474 and the switch 484 may be operated in a similar manner to couple the nth output load 478 to the main output load 420. Thus, with the exemplary embodiment illustrated in fig. 4, SARC 306 may amplify and route signals to and between N output loads. As described above, the amplification and routing of signals is dynamically controlled by the controller 308 for each path.

In routing the RF input signal to the CA load, the output of transistor T1 is used by transistor T2(n) to generate current signals that are coupled to the CA (n) output for in-carrier aggregation mode. The voltage gain at the drain of transistor T1 will be "Q _ match (gm _ T1/gm _ T3)" for common source LNA topologies. For a common-source amplifier, the Q of the input network is defined by the ratio of the reactive impedance to the resistive impedance.

The SARC 306 shown in fig. 4 provides good linearity for each Carrier Aggregation (CA) path. The linearity for each carrier aggregation path is close to that of the primary path. The linearity of each carrier aggregation path is set by the current and voltage gain of transistor T3 and the current and voltage gain of transistor T2. The first cascode amplifier is adjusted depending on whether operating in a carrier aggregation mode or a non-carrier aggregation mode to reduce noise contribution and improve linearity during operation. It should also be noted that the front-end architecture shown in fig. 4 may be implemented on one or more integrated circuits. For example, in an exemplary embodiment, components on one side of circuit boundary 494 may be implemented in a first integrated circuit and components on an opposite side of circuit boundary 494 may be implemented in a second integrated circuit. Thus, the illustrative embodiments may be implemented in any number of integrated circuits.

Fig. 5 illustrates a detailed alternative exemplary embodiment of the front end architecture illustrated in fig. 3 including a SARC 502. The SARC 502 includes the same circuit components as the SARC 306 shown in fig. 4, but connected in a different configuration. In the SARC 502, the gate terminal 468 of the third common-source amplifier 466 is coupled to the first CA1 path at terminal 506 through signal line 504. Thus, the third common-source amplifier 466 receives its input from the output of the second common-source amplifier 426. As a further extension, a subsequent common-source amplifier associated with another CA signal path may be connected to the CA2 signal path at terminal 508. By linking the outputs of the common-source amplifiers in this manner, any number of CA signal paths may be generated. It should also be noted that the second common-source amplifier 426 and the third common-source amplifier 466 are also configured without degeneration inductors, which reduces the circuit area requirements of the SARC 502.

Fig. 6 illustrates an exemplary embodiment of a controller 600 for use with the front end architecture shown in fig. 4. In an exemplary embodiment, the controller 600 is suitable for use as the controller 308 shown in fig. 4 or fig. 5. Controller 600 includes a processor 602, a memory 604, a primary control signal generator 606, and a secondary control signal generator 608, all coupled to communicate via a bus 610.

The processor 602 includes at least one of: a CPU, processor, gate array, hardware logic, discrete circuitry, memory elements, and/or hardware executing software. The processor 602 is operative to control other functional elements of the controller 600 using a bus 610. The processor 602 is also configured to communicate with other entities at the wireless device using a communication line 612. For example, processor 602 may receive instructions, control information, configuration information, data, measurements, or other information via communication lines 612.

The memory 604 comprises any suitable memory or storage device that allows instructions and/or data associated with the operation of the controller 600 to be stored, retrieved and maintained. In an exemplary embodiment, the memory 604 stores algorithmic instructions that may be executed by the memory 602 to perform the functions of signal amplification and routing described herein.

The main control signal generator 606 includes hardware such as amplifiers, buffers, registers, gates, analog-to-digital converters, digital-to-analog converters, or any other suitable hardware or discrete components and/or hardware operative to execute software that generates the main control signals Sa and Sb. In the exemplary embodiment, processor 602 is operative to determine a configuration of SARC 306 based on configuration parameters received via signal line 612. The processor then controls main control signal generator 606 using bus 610 to generate and output Sa and Sb control signals to achieve the desired configuration. In an exemplary embodiment, the Sa and Sb control signals are set to enable, disable, or bias any of the transistor devices to which they are coupled. For example, the Sa and Sb control signals may be operable to bias the transistor devices to any desired bias setting or for DC coupling.

The secondary control signal generator 608 includes hardware, such as amplifiers, buffers, registers, gates, analog-to-digital converters, digital-to-analog converters, or any other suitable hardware or discrete components and/or hardware operative to execute software that generates the secondary control signals s (n) and se (n). In the exemplary embodiment, processor 602 is operative to determine a configuration of SARC 306 based on configuration parameters received via signal line 612. The processor then controls the secondary control signal generator 608 to generate the S (n) and SE (n) control lines to achieve the desired configuration. In an exemplary embodiment, the S (n) and SE (n) control signals are set to enable, disable, or bias any of the transistor devices to which they are coupled. For example, the s (n) and se (n) control signals may be operable to bias the transistor devices to any desired bias setting or for DC coupling.

In the exemplary embodiment, processor 602 executes code stored in memory 604 to control primary control signal generator 606 and secondary control signal generator 608 to generate control signals to obtain a desired signal routing configuration.

It should be noted that the controller 600 represents only one embodiment and that other embodiments are possible. For example, the controller 600 may be implemented in discrete logic that eliminates the need for a processor or memory device. In another embodiment, the functions and/or implementations of the controller 600 are incorporated or integrated into a baseband processor or other entity at the wireless device.

Fig. 7 illustrates exemplary operations 700 for RF signal amplification and routing in a receiver front end. For example, in an exemplary embodiment, the SARC 306 and controller 308 shown in fig. 4 are configured to perform operation 700 to obtain desired RF signal amplification and routing in the receiver front-end. In the exemplary embodiment, controller 308 is controller 600 and processor 602 executes instructions stored in memory 604 to control the components of controller 600 to control SARC 306 to perform the operations described below.

At block 702, configuration parameters are received. For example, the configuration parameters are received by the processor 602 from an entity at the wireless device over the communication line 612. The configuration parameters describe how the received RF signal will be amplified and routed to the primary load and the carrier aggregation load in the receiver. In the exemplary embodiment, processor 602 is operative to store configuration parameters in memory 604.

At block 704, an RF signal is received. For example, an RF signal is received by antenna 302 and passed through matching circuit 304 before flowing on input line 406 shown in fig. 4.

At block 706, the received RF signal is amplified. In an exemplary embodiment, the received RF signal is input to the first common source amplifier 402. The first common-source amplifier 402 includes a degeneration inductor 410. An amplified version of the received RF signal appears at the drain terminal 412. Thus, the received RF signal is amplified by a common source amplifier with source degeneration to generate an amplified version of the received RF signal.

At block 708, an amplified version of the received RF signal is selectively connected to the primary load based on the configuration parameter. In the exemplary embodiment, processor 602 processes the configuration parameters to determine the control signal settings needed to achieve the desired configuration. Processor 602 communicates the control signal settings to main control signal generator 606 using bus 610. Main control signal generator 606 is operative to generate and output Sa and Sb control signals to achieve the desired signal amplification and routing to the main loads identified by the configuration parameters. For example, if the Sa control signal is logic high (1) and the Sb control signal is logic low (0), amplifier 414 provides cascode amplification to amplify the signal at terminal 412 to generate an amplified output signal at terminal 418, which is input to the main load. In various exemplary embodiments, main control signal generator 606 generates control signals Sa and Sb provided in table 800 as shown in fig. 8 to selectively connect the amplified RF signal to the main load.

At block 710, an amplified version of a received RF signal is selectively connected to one or more CA loads based on a configuration parameter. In the exemplary embodiment, processor 602 processes the configuration parameters to determine the control signal settings needed to achieve the desired configuration. Processor 602 communicates the control signal settings to secondary control signal generator 608 using bus 610. Secondary control signal generator 608 is operative to generate and output s (n) and se (n) control signals to obtain desired signal amplification and routing to one or more CA loads identified by configuration parameters. For example, if the SE1 control signal is a logic high (1), switch 432 is enabled to input the amplified signal at terminal 430 to the first CA load 434. As a result, the received RF signal is amplified and routed to the selected CA load based on the se (n) control signal to achieve the desired signal amplification and routing configuration. The further common-source amplifier (T2(n)) (e.g., amplifiers 426-466) do not include (or are configured without) a source degeneration inductor when amplifying and routing the received RF signal to the selected CA load, which results in a reduced circuit area when compared to conventional systems.

Accordingly, SARC 306 and controller 308 are configured to perform the operations described above. It should be noted that operation 700 is exemplary and that minor changes, modifications, rearrangements, and other changes to operation 700 are within the scope of the exemplary embodiments.

Fig. 8 illustrates an exemplary embodiment of a table 800, the table 800 illustrating control signal settings for various amplification and routing configurations used with the front end architecture shown in fig. 4. Table 800 includes configuration information 802, control signal Sa settings 804, control signal Sb settings 806, control signal S1 settings 808, and control signal SE1 settings 810. For clarity, table 800 only shows the signal settings for the S1 and SE1 signals. It should be noted that similar settings may be used for the control signals s (n) and se (n) to connect further loads to the input signal or the main load. In various exemplary embodiments, the controller 600 is operative to generate and output the illustrated control signals to obtain the selected configuration.

In one mode of operation, where the input signal is routed only to the primary load, control signal SA is set to a logic high voltage, control signal SB is set to a logic high voltage, control signal S1 is set to a logic low voltage, and control signal SE1 is set to a logic low voltage.

In another mode of operation to route the input signal to the main load and the first load (CA1), control signal SA is set to a logic low voltage, control signal SB is set to a logic low voltage, control signal S1 is set to a logic low voltage, and control signal SE1 is set to a logic high voltage.

In yet another mode of operation to route the first load signal to the primary load, control signal SA is set to a logic low voltage, control signal SB is set to a logic low voltage, control signal S1 is set to a logic high voltage, and control signal SE1 is set to a logic low voltage.

Fig. 9 shows an RF signal for use in a carrier aggregation receiverAn exemplary embodiment of an apparatus 900 for signal amplification and routing. In an exemplary embodiment, the apparatus 900 is suitable for use as the SARC 306 shown in fig. 4. The apparatus 900 includes a first component 902 for generating control signals that control how a signal is to be amplified and routed to one or more loads, the signal being output from a first transistor having a source terminal connected to signal ground through a source degeneration inductor, which in an exemplary embodiment includes the controller 600 shown in fig. 6 and the amplifier 402 shown in fig. 4. The apparatus 900 further includes a second component 904 for selectively connecting a signal to a first load through a first signal path based on a control signal, which in an exemplary embodiment includes transistors T3 and T3' shown in fig. 4. The apparatus 900 further includes a third component 906 for selectively connecting a signal to a second load based on a control signal, the component including a transistor receiving the signal and having a source terminal connected to signal ground, which in the exemplary embodiment includes a transistor T2₁。

The exemplary embodiments of Signal Amplifiers and Routing Circuits (SARCs) described herein may be implemented on ICs, analog ICs, RFICs, mixed signal ICs, ASICs, Printed Circuit Boards (PCBs), electronic devices, and the like. SARCs can also be fabricated using various IC process technologies such as Complementary Metal Oxide Semiconductor (CMOS), N-channel mos (nmos), P-channel mos (pmos), Bipolar Junction Transistor (BJT), bipolar coms (bicmos), silicon germanium (SiGe), gallium arsenide (GaAs), Heterojunction Bipolar Transistor (HBT), High Electron Mobility Transistor (HEMT), Silicon On Insulator (SOI), and the like.

The apparatus implementing the Signal Amplifier and Routing Circuit (SARC) described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC, such as an RF receiver (RFR) or RF transmitter/receiver (RTR), (iv) an ASIC, such as a Mobile Station Modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, a cellular telephone, a wireless device, a handset, or a mobile unit, (vii), and so forth.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.