阅读说明：本技术 锁相环电路及其控制方法 (Phase-locked loop circuit and control method thereof ) 是由 叶棪 梁成 于 2021-07-27 设计创作，主要内容包括：公开了一种锁相环电路及其控制方法。通过在校准阶段,获取与多个期望的频率控制字信号对应的多个压控振荡器电容阵列控制信号和相应的多个电荷泵电流控制信号,在锁相阶段根据校准阶段获取的数据,确定与目标频率控制字信号对应的目标压控振荡器电容阵列控制信号和目标电荷泵电流控制信号来控制锁相环电路实现锁相。由此,可以根据预先获取的数据直接确定最佳子频带,可以减少锁相时间和电路功耗。(A phase-locked loop circuit and a control method thereof are disclosed. The phase-locked loop circuit is controlled to realize phase locking by acquiring a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a plurality of corresponding charge pump current control signals in a calibration stage and determining a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal in a phase-locked stage according to data acquired in the calibration stage. Therefore, the optimal sub-frequency band can be directly determined according to the pre-acquired data, and the phase locking time and the circuit power consumption can be reduced.)

1. A method for controlling a phase-locked loop circuit, the method comprising:

in the calibration stage, acquiring a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a corresponding plurality of charge pump current control signals, wherein each frequency control word signal is used for representing the ratio of the expected locking frequency to the frequency of a reference signal; and

in the phase locking stage, a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are read to control the phase-locked loop circuit to realize phase locking.

2. The control method of claim 1, wherein the voltage controlled oscillator in the phase locked loop circuit controls the output frequency signal to achieve phase lock by an analog control signal and a digital control signal.

3. The control method of claim 2, wherein the vco capacitor array control signal is used as the digital control signal to control a total capacitance value accessed by a capacitor array in the vco to change the frequency signal output by the vco.

4. The control method according to claim 2, wherein in the calibration phase, the analog control signal is a bias voltage generated by a bias voltage generating circuit; in the phase-locked phase, the analog control signal is an output signal of a charge pump in the phase-locked loop circuit.

5. The control method according to claim 1, characterized by further comprising:

in the calibration phase, storing a first corresponding relationship between the plurality of frequency control word signals and the plurality of voltage controlled oscillator capacitor array control signals, and a second corresponding relationship between the plurality of voltage controlled oscillator capacitor array control signals and the plurality of charge pump current control signals.

6. The control method according to claim 5, characterized in that the method further comprises:

and in the phase locking stage, searching a corresponding voltage-controlled oscillator capacitor array control signal in the first corresponding relation according to the target frequency control word signal, and determining the voltage-controlled oscillator capacitor array control signal as the target voltage-controlled oscillator capacitor array control signal.

7. The control method according to claim 5, characterized in that the method further comprises:

and in the phase locking stage, searching a corresponding charge pump current control signal in a second corresponding relation according to the target voltage-controlled oscillator capacitor array control signal, and determining the charge pump current control signal as the target charge pump current control signal.

8. The method of claim 4, wherein obtaining a plurality of voltage controlled oscillator capacitor array control signals corresponding to a plurality of desired frequency control word signals comprises:

determining the theoretical minimum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical minimum value of the frequency control word signal;

determining the theoretical maximum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical maximum value of the frequency control word signal; and

and acquiring voltage-controlled oscillator capacitor array control signals corresponding to other frequency control word signals in a first interval, wherein the first interval is an interval between a theoretical minimum value and a theoretical maximum value of a predetermined frequency control word signal, and the interval between the theoretical minimum value and the theoretical maximum value of the voltage-controlled oscillator capacitor array control signals is a second interval.

9. The method of claim 8, wherein determining the theoretical minimum of the vco capacitor array control signal based on the theoretical minimum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical minimum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical minimum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical minimum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

10. The method of claim 8, wherein determining the theoretical maximum of the vco capacitor array control signal based on the theoretical maximum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical maximum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical maximum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical maximum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

11. The control method according to claim 9 or 10, wherein estimating the conversion gain in the execution step includes:

and calculating the conversion gain according to the difference between the digital frequency signals in the current execution step and the digital frequency signals in the last execution step and the difference between the voltage-controlled oscillator capacitor array control signals in the current execution step and the last execution step.

12. The control method according to claim 9 or 10, wherein the second error is a product of a ratio of the first error to the conversion gain and a frequency of the reference signal.

13. The control method according to claim 9 or 10, characterized in that the predetermined condition is satisfied: the absolute value of the second error is less than 1.

14. The method of claim 9 or 10, wherein adjusting the vco capacitor array control signal according to the first error comprises:

and superposing the voltage-controlled oscillator capacitor array control signal and the second error to be used as a voltage-controlled oscillator capacitor array control signal in the next execution step until the preset condition is met.

15. The method of claim 8, wherein obtaining vco capacitor array control signals corresponding to other frequency control word signals in the first interval comprises:

selecting a frequency control word signal within said first interval;

outputting corresponding frequency signals according to the first bias voltage generated by the bias voltage generating circuit and each voltage-controlled oscillator capacitor array control signal in the second interval;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring the selected frequency control word signal and a first error of each digital frequency signal; and

and determining the voltage-controlled oscillator capacitor array control signal corresponding to the minimum first error as the voltage-controlled oscillator capacitor array control signal corresponding to the selected frequency control word signal and storing the voltage-controlled oscillator capacitor array control signal.

16. The control method of claim 8, wherein obtaining charge pump current control signals corresponding to a plurality of desired frequency control word signals comprises:

selecting a voltage-controlled oscillator capacitor array control signal in the second interval;

outputting a corresponding second frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and a second bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding second digital frequency signal according to the reference signal;

outputting a corresponding frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and the third bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding third digital frequency signal according to the reference signal;

determining corresponding conversion gain according to the second digital frequency signal and the third digital frequency signal corresponding to the selected voltage-controlled oscillator capacitor array control signal; and

and determining and storing the charge pump current control signal corresponding to the selected voltage-controlled oscillator capacitor array control signal according to the conversion gain.

17. The method of claim 16, wherein the conversion gain is a product of a ratio of a difference between the second and third digital frequency signals and a difference between the second and third bias voltages and a frequency of the reference signal corresponding to the selected vco capacitive array control signal.

18. The method of claim 16, wherein the charge pump current control signal is used to compensate for a change in loop bandwidth due to a change in conversion gain of the vco under different vco capacitor array control signals, such that the loop bandwidth is constant.

19. The control method according to claim 2, characterized in that the method further comprises:

performing frequency division processing on the frequency signal output by the voltage-controlled oscillator to obtain a frequency division signal;

outputting a charge pump control signal according to the frequency divided signal and the reference signal, such that a charge pump outputs the analog control signal according to the target charge pump current control signal and the charge pump control signal; and

filtering an analog control signal of an output of the charge pump.

20. The control method according to claim 2, characterized in that the method further comprises:

adjusting and outputting the target voltage-controlled oscillator capacitor array control signal according to the analog control signal; and

and outputting the adjusted control signal of the capacitor array of the voltage-controlled oscillator to the voltage-controlled oscillator.

21. The method of claim 20, wherein the adjusting the target vco capacitor array control signal according to the analog control signal comprises:

comparing the analog control signal output by the charge pump with a first threshold and a second threshold respectively, wherein the first threshold is smaller than the second threshold;

in response to the analog control signal being less than a first threshold, adjusting the target voltage controlled oscillator capacitor array control signal in a predetermined direction; and

in response to the analog control signal being greater than a second threshold, adjusting the target voltage controlled oscillator capacitive array control signal in a direction opposite the predetermined direction.

22. The control method according to claim 21, wherein the first threshold is a second bias voltage output by a bias voltage generation circuit, and the second threshold is a third bias voltage output by the bias voltage generation circuit.

23. A phase-locked loop circuit, comprising:

a charge pump;

a voltage controlled oscillator; and

a computation storage circuit configured to obtain, during a calibration phase, a plurality of voltage controlled oscillator capacitive array control signals and a corresponding plurality of charge pump current control signals corresponding to a plurality of desired frequency control word signals, wherein each frequency control word signal is used to characterize a ratio of a desired lock frequency to a frequency of a reference signal; in the phase locking stage, a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are read to control the voltage-controlled oscillator and the charge pump to realize phase locking.

24. The phase-locked loop circuit of claim 23, wherein the voltage-controlled oscillator controls the output frequency signal to achieve phase lock under analog and digital control signals.

25. The phase-locked loop circuit of claim 24, wherein the vco capacitor array control signal is used as the digital control signal to control a total capacitance value accessed by a capacitor array in the vco to change the frequency signal output by the vco.

26. The phase-locked loop circuit of claim 24, further comprising:

a bias voltage generation circuit configured to generate a bias voltage as an analog control signal of the voltage controlled oscillator in the calibration phase;

wherein, in the phase-locked phase, the output signal of the charge pump is used as the analog control signal of the voltage-controlled oscillator.

27. The phase-locked loop circuit of claim 23, wherein the computation storage circuit is configured to store, during the calibration phase, a first correspondence of the plurality of frequency control word signals to the plurality of voltage-controlled oscillator capacitor array control signals and a second correspondence of the plurality of voltage-controlled oscillator capacitor array control signals to the plurality of charge pump current control signals.

28. The phase-locked loop circuit of claim 27, wherein the computation storage circuit is configured to look up a corresponding vco capacitor array control signal in the first mapping relationship according to the target frequency control word signal during the phase-locking phase, and determine the corresponding vco capacitor array control signal as the target vco capacitor array control signal.

29. The phase-locked loop circuit of claim 27, wherein the calculation storage circuit is further configured to look up a corresponding charge pump current control signal in a second correspondence from the target vco capacitor array control signal during the phase-locking phase and determine the corresponding charge pump current control signal as the target charge pump current control signal.

30. The phase-locked loop circuit of claim 26, wherein the computation storage circuit is configured to obtain a plurality of voltage-controlled oscillator capacitive array control signals corresponding to a plurality of desired frequency control word signals by:

determining the theoretical minimum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical minimum value of the frequency control word signal;

determining the theoretical maximum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical maximum value of the frequency control word signal; and

and acquiring voltage-controlled oscillator capacitor array control signals corresponding to other frequency control word signals in a first interval, wherein the first interval is an interval between a theoretical minimum value and a theoretical maximum value of a predetermined frequency control word signal, and the interval between the theoretical minimum value and the theoretical maximum value of the voltage-controlled oscillator capacitor array control signals is a second interval.

31. The phase-locked loop circuit of claim 30, further comprising:

a frequency-to-digital converter configured to convert the frequency signal output by the voltage-controlled oscillator into a frequency-to-digital signal according to a reference signal in the calibration phase.

32. The phase-locked loop circuit of claim 31, wherein the calculation storage circuit is configured to determine the theoretical minimum of the vco capacitor array control signal by:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

receiving a digital frequency signal acquired by the frequency-to-digital converter according to a frequency signal output by a voltage-controlled oscillator, wherein the voltage-controlled oscillator outputs the frequency signal according to a first bias voltage generated by the bias voltage generating circuit and a capacitor array control signal of the voltage-controlled oscillator;

acquiring a first error according to the difference value between the theoretical minimum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical minimum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical minimum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

33. The phase-locked loop circuit of claim 31, wherein the calculation storage circuit is configured to determine the theoretical maximum of the vco capacitor array control signal by:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

receiving a digital frequency signal acquired by the frequency-to-digital converter according to a frequency signal output by a voltage-controlled oscillator, wherein the voltage-controlled oscillator outputs the frequency signal according to a first bias voltage generated by the bias voltage generating circuit and a capacitor array control signal of the voltage-controlled oscillator;

acquiring a first error according to the difference value between the theoretical maximum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical maximum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical maximum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

34. The phase-locked loop circuit of claim 24, further comprising:

a frequency divider configured to perform frequency division processing on a frequency signal output by the voltage-controlled oscillator to obtain a frequency-divided signal;

a phase frequency detector configured to output a charge pump control signal according to the frequency divided signal and the reference signal, so that a charge pump outputs the analog control signal according to the target charge pump current control signal and the charge pump control signal; and

a filtering circuit configured to filter an analog control signal of an output of the charge pump.

35. The phase-locked loop circuit of claim 34, further comprising:

and the locking monitoring circuit is configured to output the target voltage-controlled oscillator capacitor array control signal after being adjusted according to the analog control signal output by the charge pump.

36. The phase-locked loop circuit of claim 35, further comprising:

the selection circuit is configured to output a target voltage-controlled oscillator capacitor array control signal output by the calculation storage circuit to the voltage-controlled oscillator in a calibration stage and provide a digital control signal for the voltage-controlled oscillator; and outputting the target voltage-controlled oscillator capacitor array control signal adjusted by the lock monitoring circuit to the voltage-controlled oscillator in a phase locking stage, and providing a digital control signal for the voltage-controlled oscillator.

Technical Field

The invention relates to the technical field of power electronics, in particular to a phase-locked loop circuit and a control method thereof.

Background

In a PLL (Phase Locked Loop) circuit, in order to suppress Phase noise generated inside a VCO (voltage-controlled oscillator), a gain KVCO of the VCO is generally implemented by increasing the number of VCO sub-bands in designing. In this way, the number of sub-bands of the VCO is increased, and the number of times of comparison is increased in the conventional method of successively comparing the frequency error of each sub-band to select the optimum sub-band, which results in a long locking time and large power consumption of the circuit.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a phase-locked loop circuit and a control method thereof, so as to reduce phase-locking time and circuit power consumption.

In a first aspect, an embodiment of the present invention provides a method for controlling a phase-locked loop circuit, where the method includes:

in the calibration stage, acquiring a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a corresponding plurality of charge pump current control signals, wherein each frequency control word signal is used for representing the ratio of the expected locking frequency to the frequency of a reference signal; and

in the phase locking stage, a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are read to control the phase-locked loop circuit to realize phase locking.

In some embodiments, a voltage controlled oscillator in the phase locked loop circuit controls the output frequency signal by an analog control signal and a digital control signal to achieve phase locking.

In some embodiments, the vco capacitor array control signal is used as the digital control signal to control a total capacitance value accessed by a capacitor array in the vco to change the frequency signal output by the vco.

In some embodiments, during the calibration phase, the analog control signal is a bias voltage generated by a bias voltage generation circuit; in the phase-locked phase, the analog control signal is an output signal of a charge pump in the phase-locked loop circuit.

In some embodiments, the method further comprises:

in the calibration phase, storing a first corresponding relationship between the plurality of frequency control word signals and the plurality of voltage controlled oscillator capacitor array control signals, and a second corresponding relationship between the plurality of voltage controlled oscillator capacitor array control signals and the plurality of charge pump current control signals.

In some embodiments, the method further comprises:

and in the phase locking stage, searching a corresponding voltage-controlled oscillator capacitor array control signal in the first corresponding relation according to the target frequency control word signal, and determining the voltage-controlled oscillator capacitor array control signal as the target voltage-controlled oscillator capacitor array control signal.

In some embodiments, the method further comprises:

and in the phase locking stage, searching a corresponding charge pump current control signal in a second corresponding relation according to the target voltage-controlled oscillator capacitor array control signal, and determining the charge pump current control signal as the target charge pump current control signal.

In some embodiments, obtaining a plurality of voltage controlled oscillator capacitive array control signals corresponding to a plurality of desired frequency control word signals comprises:

determining the theoretical minimum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical minimum value of the frequency control word signal;

determining the theoretical maximum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical maximum value of the frequency control word signal; and

and acquiring voltage-controlled oscillator capacitor array control signals corresponding to other frequency control word signals in a first interval, wherein the first interval is an interval between a theoretical minimum value and a theoretical maximum value of a predetermined frequency control word signal, and the interval between the theoretical minimum value and the theoretical maximum value of the voltage-controlled oscillator capacitor array control signals is a second interval.

In some embodiments, the determining the theoretical minimum of the vco capacitor array control signal according to the theoretical minimum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical minimum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical minimum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical minimum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, the determining the theoretical maximum of the vco capacitor array control signal based on the theoretical maximum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical maximum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical maximum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical maximum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, estimating the conversion gain in the performing step comprises:

and calculating the conversion gain according to the difference between the digital frequency signals in the current execution step and the digital frequency signals in the last execution step and the difference between the voltage-controlled oscillator capacitor array control signals in the current execution step and the last execution step.

In some embodiments, the second error is a product of a ratio of the first error to the conversion gain and a frequency of the reference signal.

In some embodiments, the predetermined condition is satisfied: the absolute value of the second error is less than 1.

In some embodiments, adjusting the vco capacitive array control signal according to the first error comprises:

and superposing the voltage-controlled oscillator capacitor array control signal and the second error to be used as a voltage-controlled oscillator capacitor array control signal in the next execution step until the preset condition is met.

In some embodiments, obtaining the vco capacitor array control signals corresponding to the other frequency control word signals in the first interval comprises:

selecting a frequency control word signal within said first interval;

outputting corresponding frequency signals according to the first bias voltage generated by the bias voltage generating circuit and each voltage-controlled oscillator capacitor array control signal in the second interval;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring the selected frequency control word signal and a first error of each digital frequency signal; and

and determining the voltage-controlled oscillator capacitor array control signal corresponding to the minimum first error as the voltage-controlled oscillator capacitor array control signal corresponding to the selected frequency control word signal and storing the voltage-controlled oscillator capacitor array control signal.

In some embodiments, obtaining the charge pump current control signals corresponding to the plurality of desired frequency control word signals comprises:

selecting a voltage-controlled oscillator capacitor array control signal in the second interval;

outputting a corresponding second frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and a second bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding second digital frequency signal according to the reference signal;

outputting a corresponding frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and the third bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding third digital frequency signal according to the reference signal;

determining corresponding conversion gain according to the second digital frequency signal and the third digital frequency signal corresponding to the selected voltage-controlled oscillator capacitor array control signal; and

and determining and storing the charge pump current control signal corresponding to the selected voltage-controlled oscillator capacitor array control signal according to the conversion gain.

In some embodiments, the conversion gain is a product of a ratio of a difference between the second and third digital frequency signals corresponding to the selected vco capacitive array control signal to a difference between the second and third bias voltages and a frequency of the reference signal.

In some embodiments, the charge pump current control signal is used to compensate for variations in loop bandwidth due to variations in conversion gain of the voltage controlled oscillator under different voltage controlled oscillator capacitor array control signals, such that the loop bandwidth is constant.

In some embodiments, the method further comprises:

performing frequency division processing on the frequency signal output by the voltage-controlled oscillator to obtain a frequency division signal;

outputting a charge pump control signal according to the frequency divided signal and the reference signal, such that a charge pump outputs the analog control signal according to the target charge pump current control signal and the charge pump control signal; and

filtering an analog control signal of an output of the charge pump.

In some embodiments, the method further comprises:

adjusting and outputting the target voltage-controlled oscillator capacitor array control signal according to the analog control signal; and

and outputting the adjusted control signal of the capacitor array of the voltage-controlled oscillator to the voltage-controlled oscillator.

In some embodiments, the adjusting the output of the target vco capacitor array control signal according to the analog control signal includes:

comparing the analog control signal output by the charge pump with a first threshold and a second threshold respectively, wherein the first threshold is smaller than the second threshold;

in response to the analog control signal being less than a first threshold, adjusting the target voltage controlled oscillator capacitor array control signal in a predetermined direction; and

in response to the analog control signal being greater than a second threshold, adjusting the target voltage controlled oscillator capacitive array control signal in a direction opposite the predetermined direction.

In some embodiments, the first threshold is a second bias voltage output by the bias voltage generation circuit, and the second threshold is a third bias voltage output by the bias voltage generation circuit.

In a second aspect, an embodiment of the present invention provides a phase-locked loop circuit, where the phase-locked loop circuit includes:

a charge pump;

a voltage controlled oscillator; and

a computation storage circuit configured to obtain, during a calibration phase, a plurality of voltage controlled oscillator capacitive array control signals and a corresponding plurality of charge pump current control signals corresponding to a plurality of desired frequency control word signals, wherein each frequency control word signal is used to characterize a ratio of a desired lock frequency to a frequency of a reference signal; in the phase locking stage, a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are read to control the voltage-controlled oscillator and the charge pump to realize phase locking.

In some embodiments, the voltage controlled oscillator controls the output frequency signal to achieve phase lock under both an analog control signal and a digital control signal.

In some embodiments, the vco capacitor array control signal is used as the digital control signal to control a total capacitance value accessed by a capacitor array in the vco to change the frequency signal output by the vco.

In some embodiments, the phase-locked loop circuit further comprises:

a bias voltage generation circuit configured to generate a bias voltage as an analog control signal of the voltage controlled oscillator in the calibration phase;

wherein, in the phase-locked phase, the output signal of the charge pump is used as the analog control signal of the voltage-controlled oscillator.

In some embodiments, the calculation storage circuitry is configured to store, during the calibration phase, a first correspondence of the plurality of frequency control word signals to the plurality of voltage controlled oscillator capacitor array control signals and a second correspondence of the plurality of voltage controlled oscillator capacitor array control signals to the plurality of charge pump current control signals.

In some embodiments, the calculation storage circuit is configured to, during the phase locking phase, look up a corresponding vco capacitor array control signal in the first correspondence according to the target frequency control word signal and determine it as the target vco capacitor array control signal.

In some embodiments, the calculation storage circuit is configured to, during the phase-locking phase, look up a corresponding charge pump current control signal in a second correspondence according to the target vco capacitor array control signal and determine it as the target charge pump current control signal.

In some embodiments, the computation storage circuitry is configured to obtain a plurality of voltage controlled oscillator capacitive array control signals corresponding to a plurality of desired frequency control word signals by:

determining the theoretical minimum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical minimum value of the frequency control word signal;

determining the theoretical maximum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical maximum value of the frequency control word signal; and

and acquiring voltage-controlled oscillator capacitor array control signals corresponding to other frequency control word signals in a first interval, wherein the first interval is an interval between a theoretical minimum value and a theoretical maximum value of a predetermined frequency control word signal, and the interval between the theoretical minimum value and the theoretical maximum value of the voltage-controlled oscillator capacitor array control signals is a second interval.

In some embodiments, the phase-locked loop circuit further comprises:

a frequency-to-digital converter configured to convert the frequency signal output by the voltage-controlled oscillator into a frequency-to-digital signal according to a reference signal in the calibration phase.

In some embodiments, the calculation storage circuit is configured to determine the theoretical minimum of the vco capacitive array control signal by:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

receiving a digital frequency signal acquired by the frequency-to-digital converter according to a frequency signal output by a voltage-controlled oscillator, wherein the voltage-controlled oscillator outputs the frequency signal according to a first bias voltage generated by the bias voltage generating circuit and a capacitor array control signal of the voltage-controlled oscillator;

acquiring a first error according to the difference value between the theoretical minimum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical minimum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical minimum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, the calculation storage circuit is configured to determine the theoretical maximum of the vco capacitive array control signal by:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

receiving a digital frequency signal acquired by the frequency-to-digital converter according to a frequency signal output by a voltage-controlled oscillator, wherein the voltage-controlled oscillator outputs the frequency signal according to a first bias voltage generated by the bias voltage generating circuit and a capacitor array control signal of the voltage-controlled oscillator;

acquiring a first error according to the difference value between the theoretical maximum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical maximum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical maximum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, the phase-locked loop circuit further comprises:

a frequency divider configured to perform frequency division processing on a frequency signal output by the voltage-controlled oscillator to obtain a frequency-divided signal;

a phase frequency detector configured to output a charge pump control signal according to the frequency divided signal and the reference signal, so that a charge pump outputs the analog control signal according to the target charge pump current control signal and the charge pump control signal; and

a filtering circuit configured to filter an analog control signal of an output of the charge pump.

In some embodiments, the phase-locked loop circuit further comprises:

and the locking monitoring circuit is configured to output the target voltage-controlled oscillator capacitor array control signal after being adjusted according to the analog control signal output by the charge pump.

In some embodiments, the phase-locked loop circuit further comprises:

the selection circuit is configured to output a target voltage-controlled oscillator capacitor array control signal output by the calculation storage circuit to the voltage-controlled oscillator in a calibration stage and provide a digital control signal for the voltage-controlled oscillator; and outputting the target voltage-controlled oscillator capacitor array control signal adjusted by the lock monitoring circuit to the voltage-controlled oscillator in a phase locking stage, and providing a digital control signal for the voltage-controlled oscillator.

According to the technical scheme of the embodiment of the invention, a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a plurality of corresponding charge pump current control signals are obtained in a calibration stage, and a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are determined to control a phase-locked loop circuit to realize phase locking according to data obtained in the calibration stage in a phase-locked stage. Therefore, the optimal sub-frequency band can be directly determined according to the pre-acquired data, and the phase locking time and the circuit power consumption can be reduced.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a phase-locked loop circuit of an embodiment of the present invention;

FIG. 2 is a schematic diagram of an equivalent circuit of a phase locked loop circuit of an embodiment of the present invention;

FIG. 3 is a flow chart of determining a second interval according to an embodiment of the present invention;

FIG. 4 is a flow chart of determining a first correspondence in an embodiment of the present invention;

FIG. 5 is a flowchart of determining a second correspondence according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another equivalent circuit of a phase locked loop circuit of an embodiment of the present invention;

FIG. 7 is a flow chart of the phase lock phase of an embodiment of the present invention;

fig. 8 is a flowchart of a control method of an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 1 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the invention. As shown in fig. 1, a phase-locked loop circuit according to an embodiment of the present invention includes a calculation storage circuit 1, a voltage-controlled oscillator 2, a bias voltage generation circuit 3, a lock monitoring circuit 4, a modulator 5, a frequency divider 6, a filter circuit 7, a charge pump 8, a phase frequency detector 9, a frequency-to-digital converter 10, a selection circuit 11, and a first switch K1 and a second switch K2.

In the present embodiment, the phase-locked loop circuit operates in different stages by controlling the first switch K1 and the second switch K2 to be turned on and off. The method can be divided into a calibration phase and a phase locking phase. In the calibration phase, the phase-locked loop circuit finds a voltage-controlled oscillator capacitor array control signal for controlling a capacitor array in the voltage-controlled oscillator corresponding to each desired frequency control word signal, and a charge pump current control signal for characterizing a desired value of the charge pump current corresponding to each desired frequency control word signal, wherein the frequency control word signal is a ratio of a desired locking frequency to a reference signal frequency. In the phase locking stage, the total capacitance value accessed by the capacitor array in the voltage-controlled oscillator is controlled by directly reading the voltage-controlled oscillator capacitor array control signal corresponding to the target frequency control word signal, and the output signal of the charge pump is adjusted by reading the charge pump current control signal, so that the phase locking can be realized when the control voltage of the voltage-controlled oscillator is in the working range. By the mode, the locking time of the phase-locked loop circuit in the actual locking process can be reduced. The phase-locked loop circuit is further described below with reference to the workflow of each stage.

Further, the phase-locked loop circuit operates in the calibration phase by controlling the first switch K1 to be turned on and the second switch K2 to be turned off, and at this time, the equivalent circuit of the phase-locked loop circuit is as shown in fig. 2.

In the present embodiment, the bias voltage generating circuit 3 may generate at least three voltages, which are a low voltage VL, a high voltage VH and a middle voltage VM, wherein the middle voltage VH is a middle value of the low voltage VL and the high voltage VH. Specifically, VM is VDD/2, where VDD is a supply voltage of the bias voltage generation circuit 3. The present embodiment names the middle voltage VM, the low voltage VL, and the high voltage VH as a first bias voltage, a second bias voltage, and a third bias voltage, respectively.

In this embodiment, the voltage-controlled oscillator 2 includes an analog signal receiving terminal and a digital signal receiving terminal, receives the analog control signal through the analog signal receiving terminal, receives the digital control signal through the digital signal receiving terminal, and outputs a corresponding frequency signal VOUT, which is also an output signal of the phase-locked loop circuit, according to the analog control signal and the digital control signal.

The analog control signal is used to provide a control voltage for the voltage-controlled oscillator 2, so as to change the frequency output by the voltage-controlled oscillator 2, and the digital control signal is used to control the total capacitance value accessed by the capacitor array in the voltage-controlled oscillator 2, so as to adjust the frequency range output by the voltage-controlled oscillator 2, that is, the frequency signal VOUT output by the voltage-controlled oscillator 2 is controlled by the analog control signal and the digital control signal at the same time, where the digital control signal is a control signal of the capacitor array of the voltage-controlled oscillator, and the analog control signal is a voltage control signal of the voltage-controlled oscillator.

Further, in the calibration stage shown in fig. 2, the analog control signal received by the analog signal receiving terminal is the output signal of the bias voltage generating circuit 3, and the digital signal receiving terminal is connected to the output terminal of the selecting circuit 11 for receiving the digital control signal output by the selecting circuit 11.

In this embodiment, the selection circuit 11 includes an enable terminal for receiving the enable signal EN, a first input terminal connected to the output terminal of the calculation storage circuit 1 for receiving the vco capacitor array control signal cb output by the calculation storage circuit 1, and a second input terminal. The second input terminal is used for receiving the vco capacitor array control signal cb' output by the lock monitor circuit 4. The selection circuit 11 selects one of the signals cb and cb' to be output to the voltage-controlled oscillator 2, so as to change a total capacitance value accessed by a capacitor array in the voltage-controlled oscillator 2, that is, a capacitor array control signal of the voltage-controlled oscillator is the digital control signal. For example, when the enable signal EN is in the first state, the vco capacitor array control signal cb is selected to be output to the vco 2, as shown in fig. 2.

In some embodiments, when the first state is high, that is, the enable signal EN is high, the vco capacitor array control signal cb is selected to be output to the vco 2.

In the present embodiment, the calculation storage circuit 1 receives the reference signal ref, the frequency control word signal FCW, and the digital frequency signal DOUT output by the frequency-to-digital converter 10, and outputs the vco array control signal cb according to the reference signal ref, the frequency control word signal FCW, and the digital frequency signal DOUT. The frequency control word signal FCW is used to represent the ratio (expressed in binary) of the desired locking frequency to the frequency of the reference signal ref, and the digital frequency signal DOUT is the ratio (expressed in binary) of the frequency signal VOUT output by the current phase-locked loop circuit to the frequency of the reference signal ref. It should be understood that the frequency control word signal FCW and the digital frequency signal DOUT may each include an integer portion and a fractional portion.

In the present embodiment, the frequency-to-digital converter 10 receives the frequency signal VOUT and the reference signal ref output by the voltage-controlled oscillator 2, calculates the digital frequency signal DOUT according to the frequency signal VOUT and the reference signal ref, and outputs the digital frequency signal DOUT to the calculation and storage circuit 1.

Furthermore, the calibration stage can be divided into two stages, and in the first stage, the phase-locked loop circuit acquires a voltage-controlled oscillator capacitor array control signal cb corresponding to each frequency control word signal FCW; in the second stage, the phase-locked loop circuit obtains a charge pump current control signal ICP corresponding to each vco capacitor array control signal cb, wherein the charge pump current control signal ICP is used for compensating for a change of a loop bandwidth caused by a change of a gain Kvco of the vco 2 under different vco capacitor array control signals cb, so that the loop bandwidth is constant.

Further, in the first stage, the pll circuit may first obtain the capacitor array characterizing the vcoThe second interval of the value range of the column control signal cb, that is, the FCW is found first_minAnd FCW_maxThe corresponding theoretical minimum and maximum of cb. The working flow of the phase-locked loop circuit is shown in fig. 3, and with reference to fig. 2 and 3, the theoretical minimum value of the vco capacitor array control signal cb can be obtained through steps S101 and S103 to S111, and the theoretical maximum value of the vco capacitor array control signal cb can be obtained through steps S102 to S111, so that a second interval can be obtained, where the second interval is an interval between the theoretical minimum value and the theoretical maximum value of the vco capacitor array control signal cb.

Specifically, the step of acquiring the theoretical minimum value of the vco capacitor array control signal cb by the phase-locked loop circuit specifically includes the following steps:

step S101: let FCW be FCW_min。

The calculation storage circuit 1 acquires a first interval between the theoretical minimum value and the theoretical maximum value of the frequency control word signal FCW. More specifically, the theoretical minimum and maximum values of the frequency control word signal FCW are determined according to the desired locking frequency range, which is determined by the actual application scenario, and the frequency ranges are different in different application scenarios. For example, the desired lock-in frequency range may be denoted as F_min-F_max，F_minFor the minimum frequency desired to lock in the application scenario, F_maxObtaining F for the maximum frequency expected to be locked in the application scene_minTheoretical minimum value FCW of corresponding frequency control word signal_minObtaining F_maxTheoretical maximum value FCW of corresponding frequency control word signal_maxWherein the frequency control word signal is indicative of a ratio of the desired lock frequency F to the frequency of the reference signal ref. Thus, the first interval is FCW_min-FCW_max。

Step S103: the value of cb is set.

At the first execution, the value of cb may be set to an initial value. Specifically, depending on the circuit configuration of the voltage-controlled oscillator 2, there is an effective range of the value of cb, and any cb within the effective range can effectively control the voltage-controlled oscillator 2. The initial value may be any value within a valid range. Preferably, the initial value is half of the effective maximum value, so that when the initial value is adjusted, the number of adjustments is not made too many in both the direction of positive adjustment and the direction of negative adjustment. For example, assuming that the bit value of the capacitor array is 5, the range of cb is 32, and the initial value may be 16.

Step S104: EN is 1, K2 is off, and K1 is on.

Setting EN to 1, that is, EN is high level, so that the signal selectively output by the selection circuit 11 is the vco capacitor array control signal cb output by the calculation storage circuit 1, and in fig. 2, the numbers 0 and 1 in the selection circuit 11 represent different pins.

K2 is turned off and K1 is turned on, so that the phase locked loop circuit operates in the mode shown in FIG. 2.

Step S105: the bias voltage generating circuit outputs VM.

The voltage output by the bias voltage generating circuit 3 is VM.

It should be understood that, the steps S101 and S103 to S105 are actually configurations of circuits, and the execution order is not distinguished, and the steps may be executed sequentially or simultaneously.

Step S106: a digital frequency signal DOUT is determined.

The calculation storage circuit 1 outputs the initial value of the vco capacitor array control signal cb to the vco 2, so that the vco 2 outputs a corresponding frequency signal VOUT according to the first bias voltage VM and the initial value of the vco capacitor array control signal cb, and the frequency digitizer 10 converts the frequency signal VOUT into a corresponding digital frequency signal DOUT according to the reference signal ref.

Further, the reference signal ref is a clock signal, and the frequency and the period of the clock signal ref are known, so that the period number of the frequency signal VOUT within a predetermined number of periods of the reference signal can be counted to obtain DOUT. For example, assuming that the number of cycles of the frequency signal VOUT is M in N cycles of the reference signal through statistics, the digital frequency signal DOUT is equal to M/N, and thus the digital frequency signal DOUT can be determined.

Step S107: a first error err is calculated.

Calculating a frequency control word signal FCW_minThe difference with the digital frequency signal DOUT is taken as the first error err, i.e. the first error err is FCW_min-DOUT。

Step S108: the conversion gain KVCO is estimated.

Wherein, the specific estimation formula is as follows:

wherein KVCO is the conversion gain, DOUT₁For the value of the digital frequency signal during the last calculation, DOUT₂As a value of the digital frequency signal during this calculation, cb₁For the last calculation of the value of the VCO capacitor array control signal, cb₂Fref is the frequency of the reference signal ref, which is the value of the VCO capacitor array control signal in the calculation process.

Further, the conversion gain is used for representing the frequency change value corresponding to the frequency signal VOUT when the vco capacitor array control signal cb changes by one unit (here, 1).

At the first calculation, since there is no previous cb₁And DOUT₁The conversion gain may be set to a preset value.

Step S109: calculating a second error cb_err。

Calculating a second error cb based on the conversion gain KVCO and the first error err_errWherein the second error cb_errRepresenting the error between the current cb value and the cb value of the target. The specific calculation formula is as follows:

where err is the first error, Fref is the frequency of the reference signal, and KVCO is the conversion gain.

Step S110: it is detected whether the absolute value of the second error is smaller than 1.

Detecting the absolute value abs (cb) of the second error_err) Whether less than 1.

Step S111: absolute value abs (cb) responsive to the second error_err) Less than 1, storing the current cb value as cb_min。

Absolute value abs (cb) responsive to the second error_err) If not less than 1, the process returns to step S103 to adjust the cb value, and the new cb value is the original cb value plus cb_errThen, the execution of steps S104 to S110 is continued until the absolute value abs (cb) of the second error_err) If it is less than 1, the process proceeds to step S111, where the current cb value is stored as cb_min。

Similarly, the FCW is applied_minReplacement by FCW_maxThereafter (i.e., performing step S102), cb may be obtained at step S111_max。

Thus, a second interval cb is obtained_min-cb_maxThe interval in between.

In some embodiments, the cb obtained above may also be used_minAnd cb_maxFurther expanded to obtain a second interval of greater extent, e.g. the second interval may be (cb)_min-1，cb_max+1)。

Further, the phase-locked loop circuit obtains the vco capacitor array control signal cb corresponding to the other frequency control word signals FCW in the first interval, so as to obtain each frequency control word signal FCW in the first interval and the vco capacitor array control signal cb corresponding to the frequency control word signal FCW. Specifically, the process of the phase-locked loop circuit acquiring the vco capacitor array control signal cb corresponding to the other frequency control word signal FCW in the first interval is shown in fig. 4, and includes the following steps:

step S201: select a divide FCW within a first interval_minAnd FCW_maxAn outer FCW.

Assume a first interval FCW_min-FCW_maxThe frequency control word comprises n frequency control word signals which are FCW from small to large₁、FCW₂、……、FCW_nWherein FCW₁Is equal to FCW_min，FCW_nIs equal to FCW_maxSelecting a frequency control word signal FCW within said first interval according to a predetermined order_iWhere i is 2, … …, n-1, where n is greater than 1. It should be understood that the spacing between FCWs is application specific, e.g., different frequency channels for different transceivers, and the value of n is determined. In the embodiment shown in fig. 4, a frequency control word signal FCW is selected in the first interval in descending order_iThat is, when the first execution is performed, the selected frequency control word signal is FCW₂。

Step S202: selecting a divide cb in the second interval_minAnd cb_maxAnd the other cb.

And selecting a voltage-controlled oscillator capacitor array control signal cb in the second interval.

Suppose that the second section cb_min-cb_maxM voltage-controlled oscillator capacitor array control signals cb are included in the circuit, and the cb is respectively the largest from the smallest₁、cb₂、……、cb_mWherein cb is₁Is equal to cb_min，cb_mIs equal to cb_max. Selecting a voltage controlled oscillator capacitor array control signal cb in the second interval according to a predetermined sequence_jWherein j is 2, … …, m-1, wherein m is greater than 1. In the embodiment shown in fig. 4, one vco capacitor array control signal cb is selected in the second interval in descending order_jThat is, when the first execution is performed, the selected VCO capacitor array control signal cb is cb₂。

Step S203: the first error is calculated and stored.

Obtaining a selected VCO capacitor array control signal cb_jCorresponding digital frequency signal DOUT_jWherein the voltage-controlled oscillator 2 is controlled according to the selected voltage-controlled oscillator capacitor array control signal cb_jGenerates a corresponding frequency signal VOUT with the first bias voltage VM_jThe frequency-to-digital converter 10 is used for converting the frequency signal VOUT into the frequency signal VOUT_jOutputting the corresponding digital frequency signal DOUT_j. Obtaining a selected frequency control word signal FCW_iAnd said digital frequency signal DOUT_jIs taken as the first error err_i,j. The specific calculation process is as steps S106-S107 in fig. 3, which is not described again in this embodiment of the present invention.

Step S204: detecting if cb equals cb_max。

Detecting whether cb at this time is equal to cb_maxIf yes, the process proceeds to step S205.

Detecting whether cb at this time is equal to cb_maxIf not, return to step S202 to select the next cb until cb equals cb_maxThen, the process proceeds to step S205.

Step S205: detecting whether FCW is equal to FCW_max。

Checking whether the FCW at this time is equal to the FCW_maxIf yes, the process proceeds to step S206.

Checking whether the FCW at this time is equal to the FCW_maxIf not, return to step S201, select the next FCW until the FCW equals the FCW_maxThen, the process proceeds to step S206. It should be understood that the order of step S204 and step S205 may be interchanged.

Step S206: a first correspondence is determined.

The control word signal FCW at each frequency can be obtained through the above steps S201 to S205_iAnd respective VCO capacitor array control signals cb_jFirst error err of_i,jFor each frequency control word signal FCW_iDetermining the voltage controlled oscillator capacitor array control signal corresponding to the absolute value of the smallest first error as the selected frequency control word signal FCW_iAnd storing the corresponding voltage-controlled oscillator capacitor array control signal.

Further, as known to those skilled in the art, the loop bandwidth of the pll circuit is determined by the charge pump current I _ cp in the charge pump 8, the conversion gain KVCO and the frequency control word signal FCW, and in order to make the loop bandwidth of the pll circuit constant under different vco capacitor array control signals cb, I _ cp × KVCO/FCW needs to be made constant, so that the charge pump current needs to be compensated to satisfy the condition. In the second stage, the phase-locked loop circuit obtains the charge pump current control signal ICP corresponding to each vco capacitor array control signal cb, where the charge pump current control signal ICP represents a desired current value of the charge pump current I _ cp in the charge pump 8, that is, the charge pump 8 adjusts the charge pump current I _ cp to be equal to the charge pump current control signal ICP according to the charge pump current control signal ICP. Specifically, the process of the phase-locked loop circuit acquiring the charge pump current control signal ICP corresponding to the vco capacitor array control signal cb is shown in fig. 5, and includes the following steps:

step S301: one cb is selected within the second interval.

And selecting a voltage-controlled oscillator capacitor array control signal cb in the second interval.

Suppose that the second section cb_min-cb_maxM voltage-controlled oscillator capacitor array control signals cb are included in the circuit, and the cb is respectively the largest from the smallest₁、cb₂、……、cb_mWherein cb is₁Is equal to cb_min，cb_mIs equal to cb_max. Selecting a voltage controlled oscillator capacitor array control signal cb in the second interval according to a predetermined sequence_jWhere j is 1, 2, … …, m. In the embodiment shown in fig. 5, one vco capacitor array control signal cb is selected in the second interval in descending order_jThat is, when the first execution is performed, the selected VCO capacitor array control signal is cb₁。

Step S302: the bias voltage generating circuit outputs VL to calculate DOUT_L。

The control bias voltage generating circuit 3 outputs a second bias voltage VL to obtain a selected VCO capacitor array control signal cb_jDigital frequency signal DOUT corresponding to second bias voltage VL_LWherein the voltage-controlled oscillator 2 controls the signal cb according to the selected voltage-controlled oscillator capacitor array_jAnd a second bias voltage VL to generate a frequency signal VOUT, from which the frequency-to-digital converter 10 outputs the digital frequency signal DOUT_L。

Step S303: the bias voltage generation circuit outputs VH and calculates DOUT_H。

The control bias voltage generation circuit 3 outputs a third bias voltage VH to obtain a selected voltage-controlled oscillator capacitor array control signal cb_jDigital frequency signal DOUT corresponding to third bias voltage VH_HWherein the voltage controlled oscillator controls the signal cb according to the selected voltage controlled oscillator capacitor array_jAnd a third bias voltage VH to generate a frequency signal from which the frequency-to-digital converter 10 outputs the digital frequency signal DOUT_H。

It should be understood that the above steps S302 and S303 do not distinguish the execution order.

Step S304: the conversion gain KVCO is calculated.

According to the obtained digital frequency signal DOUT_LAnd DOUT_HCalculating a conversion gain KVCO, wherein the specific calculation formula is as follows:

wherein, DOUT_LFor a digital frequency signal, DOUT, corresponding to the output VL of the bias voltage generating circuit 3_HWhen the bias voltage generation circuit 3 outputs VH, VL is the second bias voltage, VH is the third bias voltage, and Fref is the frequency of the reference signal ref.

Step S305: the charge pump current control signal ICP is calculated.

Calculating the current control signal ICP according to the obtained KVCO, wherein the specific calculation formula is as follows:

wherein KVCO is the conversion gain, KVCO_initFor the initial value of the conversion gain, FCW is the control signal cb corresponding to the selected VCO capacitor array_jCorresponding frequency control word signal, FCW_initIs an initial value of the frequency control word signal, ICP is a charge pump current control signal, is a desired current value of the charge pump current, ICP_initAn initial value of the charge pump current is characterized.

Therefore, the charge pump current control signal ICP corresponding to the selected voltage-controlled oscillator capacitor array control signal cb can be obtained and stored.

Step S306: detecting if cb equals cb_max。

Detecting whether cb at this time is equal to cb_maxIf yes, the process proceeds to step S307.

Detecting whether cb at this time is equal to cb_maxIf not, return to step 301 to select the next cb until cb equals cb_maxThen, step 307 is entered.

Step S307: and (6) ending.

Therefore, the charge pump current control signal ICP corresponding to each voltage-controlled oscillator capacitor array control signal cb can be obtained.

To sum up, when the phase-locked loop circuit works in the calibration phase, the vco capacitive array control signal cb corresponding to each frequency control word signal FCW and the charge pump current control signal ICP corresponding to the vco capacitive array control signal cb are obtained and stored, and when the phase-locked loop circuit works in the phase-locked phase, for a given target locking frequency, the cb value and the charge pump current control signal ICP can be directly determined through stored data to achieve fast phase locking, and in addition, when the selected cb value enables the control voltage of the voltage-controlled oscillator to exceed the working range, the cb value is finely adjusted to enable the control voltage of the voltage-controlled oscillator to be within the working range, thereby achieving phase locking.

Further, when the phase locking is performed, the switch K2 is turned on, and the switch K1 is turned off, and the equivalent circuit is shown in fig. 6.

In this embodiment, the voltage-controlled oscillator 2 includes an analog signal receiving terminal and a digital signal receiving terminal, receives the analog control signal through the analog signal receiving terminal, receives the digital control signal through the digital signal receiving terminal, and outputs the corresponding frequency signal VOUT according to the analog control signal and the digital control signal.

Further, the analog control signal received by the analog signal receiving end is the output signal of the charge pump 8, and more specifically, the output signal of the charge pump 8 is the signal output after passing through the filter circuit 7, and the digital signal receiving end is connected to the output end of the selection circuit 11 for receiving the digital control signal output by the selection circuit 11.

In this embodiment, the selection circuit 11 includes an enable terminal for receiving the enable signal EN, a first input terminal connected to the output terminal of the calculation storage circuit 1 for receiving the vco capacitor array control signal cb output by the calculation storage circuit 1, and a second input terminal. The second input terminal is used for receiving the vco capacitor array control signal cb' output by the lock monitor circuit 4. The selection circuit 11 selects one of the signals cb and cb' to be output to the voltage-controlled oscillator 2. That is, the vco capacitor array control signal is the digital control signal. For example, when the enable signal EN is in the first state, the signal cb 'is selected to be output to the voltage controlled oscillator 2, and when the enable signal EN is in the second state, the signal cb' is selected to be output to the voltage controlled oscillator 2. In the present embodiment, the enable signal EN is in the second state, that is, the vco 2 receives the vco capacitor array control signal cb'.

In some embodiments, when the second state is low, that is, the enable signal EN is low, the signal cb' is selected to be output to the voltage-controlled oscillator 2.

In some embodiments, the calculation storage circuit 1 receives the target frequency control word signal FCW.

The calculation storage circuit 1 obtains stored data including a first correspondence of the frequency control word signal FCW and the vco capacitor array control signal cb and a second correspondence of the vco capacitor array control signal cb and the charge pump current control signal ICP. And searching a corresponding voltage-controlled oscillator capacitor array control signal cb in the first corresponding relation according to the target frequency control word signal, determining the control signal as a target voltage-controlled oscillator capacitor array control signal, searching a corresponding charge pump current control signal in the second corresponding relation according to the target voltage-controlled oscillator capacitor array control signal, and determining the control signal as a target charge pump current control signal. And outputting a target voltage-controlled oscillator capacitor array control signal to the lock monitoring circuit 4, and outputting a target charge pump current control signal to the charge pump 8.

The charge pump 8 receives the output signal of the phase frequency detector 9 and the target charge pump current control signal, and outputs a corresponding voltage signal according to the output signal of the phase frequency detector 9 and the target charge pump current control signal. The voltage signal is processed by the filter circuit 7 and then output to the analog signal receiving end of the voltage-controlled oscillator 2 as an analog control signal. The analog control signal output by the filter circuit 7 is denoted as Vc.

The lock monitoring circuit 4 is used for judging whether the control voltage of the voltage-controlled oscillator 2 exceeds the working range or not, and adjusting the capacitor array control signal cb of the voltage-controlled oscillator when the control voltage exceeds the working range. It should be understood that in some cases, it may happen that the directly found corresponding vco capacitor array control signal cb is not accurate, and at this time, the vco capacitor array control signal cb needs to be trimmed to meet the requirement. The lock monitoring circuit 4 receives the target voltage-controlled oscillator capacitor array control signal cb output by the calculation storage circuit 1 and the signal Vc output by the filter circuit 7, adjusts the target voltage-controlled oscillator capacitor array control signal cb according to the signal Vc to generate cb ', and outputs cb' to the selection circuit 11. As described above, the selection circuit 11 selects to output the signal cb 'to the voltage-controlled oscillator 2, so that the voltage-controlled oscillator 2 outputs the corresponding frequency signal VOUT according to the signals cb' and Vc.

The frequency divider 6 divides the frequency signal VOUT output by the voltage-controlled oscillator 2 to obtain a frequency-divided signal, and outputs the frequency-divided signal to the phase frequency detector 9. Further, since the division ratio is not necessarily an integer, a modulator (e.g., a Sigma-delta modulator) 5 is also required to modulate the division ratio according to the target frequency control word signal FCW so that the frequency divider 6 can equivalently generate a fractional division ratio.

The phase frequency detector 9 receives the frequency-divided signal and the reference signal ref, and outputs a charge pump control signal according to the frequency-divided signal and the reference signal ref, so that the charge pump 8 outputs the signal Vc according to the charge pump current control signal ICP and the charge pump control signal.

Further, the lock monitoring circuit 4 compares the signal Vc output by the charge pump with the first threshold and the second threshold, respectively, where the first threshold is smaller than the second threshold, adjusts the target vco capacitor array control signal cb in a predetermined direction in response to the analog control signal Vc being smaller than the first threshold, and adjusts the target vco capacitor array control signal cb in a direction opposite to the predetermined direction in response to the analog control signal Vc being larger than the second threshold. The above direction may be determined according to the properties of the voltage controlled oscillator. For example, if the vco capacitor array control signal cb increases and the frequency of the output signal of the vco decreases when the signal Vc is not changed, the above-mentioned adjusting process is: the cb value is decremented by one in response to the signal Vc being less than a first threshold and incremented in response to the signal Vc being greater than a second threshold.

Further, the first threshold is a second bias voltage VL output by the bias voltage generation circuit, and the second threshold is a third bias voltage VH output by the bias voltage generation circuit.

Specifically, with reference to the phase-locking process shown in fig. 7, when the phase-locked loop circuit performs phase locking, the method specifically includes the following steps:

step S401: a target frequency control word signal FCW is obtained.

The calculation storage circuit 1 obtains a target frequency control word signal that is used to characterize the ratio of the frequency desired to be locked to the frequency of the reference signal.

Step S402: EN is 0, K2 is on, and K1 is off.

The control enable signal EN is 0, so that the selection circuit 11 selects the output signal of the lock monitor circuit 4 to be output to the voltage-controlled oscillator 2. Meanwhile, K2 is turned on, K1 is turned off, so that the analog control signal of the vco 2 is the output signal of the charge pump 8, and the output signal of the vco 2 is fed back to the phase frequency detector 9 to form a feedback regulation.

Step S403: and determining a target voltage-controlled oscillator capacitor array control signal cb.

The calculation storage circuit 1 obtains a target voltage-controlled oscillator capacitor array control signal cb corresponding to the target frequency control word signal FCW according to the stored data. And determining a target charge pump current control signal ICP according to the target voltage controlled oscillator capacitor array control signal cb, wherein the target charge pump current control signal ICP is used for adjusting the charge pump current of the charge pump 8 so as to make the loop bandwidth of the phase-locked loop circuit constant. Further, the target vco capacitor array control signal cb and the output signal of the charge pump control the output signal of the vco 2 at the same time.

Step S404: the signal Vc is acquired.

The lock monitor circuit 4 obtains the signal Vc output by the charge pump 8.

Step S405: signals Vc and VH are compared.

The lock monitor circuit 4 compares the signals Vc and VH.

In response to Vc being greater than VH, the process proceeds to step S407, and the cb value is increased by 1 to control the voltage controlled oscillator 2.

In response to Vc not being greater than VH, the flow proceeds to step S406, where signals Vc and VL are compared.

In response to Vc being smaller than VL, the process proceeds to step S409, and the voltage controlled oscillator 2 is controlled by subtracting 1 from the cb value.

In response to Vc not less than VL, the process proceeds to step S408, and the phase locking is completed.

In the above manner, for a given frequency control word signal, the corresponding voltage-controlled oscillator capacitor array control signal and the charge pump current control signal are obtained according to the pre-stored data, wherein the loop bandwidth is kept constant by the charge pump current control signal. When the control voltage of the voltage-controlled oscillator exceeds the working range under the current voltage-controlled oscillator capacitor array control signal, the lock monitoring circuit adjusts the voltage-controlled oscillator capacitor array control signal (namely, the digital control signal of the voltage-controlled oscillator) so that the control voltage of the voltage-controlled oscillator is in the working range. Meanwhile, the output signal of the voltage-controlled oscillator is fed back and regulated through a feedback loop (a frequency divider, a phase frequency detector, a charge pump and a filter circuit).

In the embodiment of the invention, a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a plurality of corresponding charge pump current control signals are obtained in a calibration stage, and a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are determined to control a phase-locked loop circuit to realize phase locking according to data obtained in the calibration stage in a phase-locked stage. Therefore, the optimal sub-frequency band can be directly determined according to the pre-acquired data, and the phase locking time and the circuit power consumption can be reduced.

Fig. 8 is a flowchart of a control method of an embodiment of the present invention. As shown in fig. 8, the control method according to the embodiment of the present invention includes the following steps:

s510: in a calibration phase, a plurality of vco capacitor array control signals and a corresponding plurality of charge pump current control signals corresponding to a plurality of desired frequency control word signals, each representing a ratio of a desired lock frequency to a frequency of a reference signal, are obtained.

S520: in the phase locking stage, a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are read to control the phase-locked loop circuit to realize phase locking.

In some embodiments, a voltage controlled oscillator in the phase locked loop circuit controls the output frequency signal by an analog control signal and a digital control signal to achieve phase locking.

In some embodiments, the vco capacitor array control signal is used as the digital control signal to control a total capacitance value accessed by a capacitor array in the vco to change the frequency signal output by the vco.

In some embodiments, during the calibration phase, the analog control signal is a bias voltage generated by a bias voltage generation circuit; in the phase-locked phase, the analog control signal is an output signal of a charge pump in the phase-locked loop circuit.

In some embodiments, the method further comprises:

in the calibration phase, storing a first corresponding relationship between the plurality of frequency control word signals and the plurality of voltage controlled oscillator capacitor array control signals, and a second corresponding relationship between the plurality of voltage controlled oscillator capacitor array control signals and the plurality of charge pump current control signals.

In some embodiments, the method further comprises:

in the phase locking stage, searching a corresponding voltage-controlled oscillator capacitor array control signal in the first corresponding relation according to the target frequency control word signal, and determining the signal as the target voltage-controlled oscillator capacitor array control signal; and

and searching a corresponding charge pump current control signal in a second corresponding relation according to the target voltage-controlled oscillator capacitor array control signal, and determining the corresponding charge pump current control signal as the target charge pump current control signal.

In some embodiments, obtaining a plurality of voltage controlled oscillator capacitive array control signals corresponding to a plurality of desired frequency control word signals comprises:

determining the theoretical minimum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical minimum value of the frequency control word signal;

determining the theoretical maximum value of the control signal of the voltage-controlled oscillator capacitor array according to the theoretical maximum value of the frequency control word signal; and

and acquiring voltage-controlled oscillator capacitor array control signals corresponding to other frequency control word signals in a first interval, wherein the first interval is an interval between a theoretical minimum value and a theoretical maximum value of a predetermined frequency control word signal, and the interval between the theoretical minimum value and the theoretical maximum value of the voltage-controlled oscillator capacitor array control signals is a second interval.

In some embodiments, the determining the theoretical minimum of the vco capacitor array control signal according to the theoretical minimum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical minimum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical minimum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical minimum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, the determining the theoretical maximum of the vco capacitor array control signal based on the theoretical maximum of the frequency control word signal comprises:

determining a voltage-controlled oscillator capacitor array control signal in the current execution step;

outputting a corresponding frequency signal according to a first bias voltage generated by the bias voltage generating circuit and the control signal of the voltage-controlled oscillator capacitor array;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring a first error according to the difference value between the theoretical maximum value of the frequency control word signal and the digital frequency signal;

estimating the conversion gain in the executing step;

determining a second error based on the estimated conversion gain and the first error;

in response to the second error meeting a preset condition, determining the voltage-controlled oscillator capacitor array control signal in the current execution step as a theoretical maximum value of the voltage-controlled oscillator capacitor array control signal and storing the theoretical maximum value; and

and adjusting the voltage-controlled oscillator capacitor array control signal according to the first error in response to the difference not meeting a predetermined condition.

In some embodiments, estimating the conversion gain in the performing step comprises:

and calculating the conversion gain according to the difference between the digital frequency signals in the current execution step and the digital frequency signals in the last execution step and the difference between the voltage-controlled oscillator capacitor array control signals in the current execution step and the last execution step.

In some embodiments, the second error is a product of a ratio of the first error to the conversion gain and a frequency of the reference signal.

In some embodiments, the predetermined condition is satisfied: the absolute value of the second error is less than 1.

In some embodiments, adjusting the vco capacitive array control signal according to the first error comprises:

and superposing the voltage-controlled oscillator capacitor array control signal and the second error to be used as a voltage-controlled oscillator capacitor array control signal in the next execution step until the preset condition is met.

In some embodiments, obtaining the vco capacitor array control signals corresponding to the other frequency control word signals in the first interval comprises:

selecting a frequency control word signal within said first interval;

outputting corresponding frequency signals according to the first bias voltage generated by the bias voltage generating circuit and each voltage-controlled oscillator capacitor array control signal in the second interval;

converting the frequency signal into a digital frequency signal according to the reference signal;

acquiring the selected frequency control word signal and a first error of each digital frequency signal; and

and determining the voltage-controlled oscillator capacitor array control signal corresponding to the minimum first error as the voltage-controlled oscillator capacitor array control signal corresponding to the selected frequency control word signal and storing the voltage-controlled oscillator capacitor array control signal.

In some embodiments, obtaining the charge pump current control signals corresponding to the plurality of desired frequency control word signals comprises:

selecting a voltage-controlled oscillator capacitor array control signal in the second interval;

outputting a corresponding second frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and a second bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding second digital frequency signal according to the reference signal;

outputting a corresponding frequency signal according to the selected voltage-controlled oscillator capacitor array control signal and the third bias voltage generated by the bias voltage generating circuit;

converting the frequency signal into a corresponding third digital frequency signal according to the reference signal;

determining corresponding conversion gain according to the second digital frequency signal and the third digital frequency signal corresponding to the selected voltage-controlled oscillator capacitor array control signal; and

and determining and storing the charge pump current control signal corresponding to the selected voltage-controlled oscillator capacitor array control signal according to the conversion gain.

In some embodiments, the conversion gain is a product of a ratio of a difference between the second and third digital frequency signals corresponding to the selected vco capacitive array control signal to a difference between the second and third bias voltages and a frequency of the reference signal.

In some embodiments, the charge pump current control signal is used to compensate for variations in loop bandwidth due to variations in conversion gain of the voltage controlled oscillator under different voltage controlled oscillator capacitor array control signals, such that the loop bandwidth is constant.

In some embodiments, the method further comprises:

performing frequency division processing on the frequency signal output by the voltage-controlled oscillator to obtain a frequency division signal;

outputting a charge pump control signal according to the frequency divided signal and the reference signal, such that a charge pump outputs the analog control signal according to the target charge pump current control signal and the charge pump control signal; and

filtering an analog control signal of an output of the charge pump.

In some embodiments, the method further comprises:

adjusting and outputting the target voltage-controlled oscillator capacitor array control signal according to the analog control signal; and

and outputting the adjusted control signal of the capacitor array of the voltage-controlled oscillator to the voltage-controlled oscillator.

In some embodiments, the adjusting the output of the target vco capacitor array control signal according to the analog control signal includes:

comparing the analog control signal output by the charge pump with a first threshold and a second threshold respectively, wherein the first threshold is smaller than the second threshold;

in response to the analog control signal being less than a first threshold, adjusting the target voltage controlled oscillator capacitor array control signal in a predetermined direction; and

in response to the analog control signal being greater than a second threshold, adjusting the target voltage controlled oscillator capacitive array control signal in a direction opposite the predetermined direction.

In some embodiments, the first threshold is a second bias voltage output by the bias voltage generation circuit, and the second threshold is a third bias voltage output by the bias voltage generation circuit.

In the embodiment of the invention, a plurality of voltage-controlled oscillator capacitor array control signals corresponding to a plurality of expected frequency control word signals and a plurality of corresponding charge pump current control signals are obtained in a calibration stage, and a target voltage-controlled oscillator capacitor array control signal and a target charge pump current control signal corresponding to a target frequency control word signal are determined to control a phase-locked loop circuit to realize phase locking according to data obtained in the calibration stage in a phase-locked stage. Therefore, the optimal sub-frequency band can be directly determined according to the pre-acquired data, and the phase locking time and the circuit power consumption can be reduced.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.