阅读说明：本技术 用于宽带隙超结功率器件的结终端的系统和方法 (System and method for junction termination of wide bandgap superjunction power devices ) 是由 斯蒂芬·戴利·阿瑟 维克多·马里奥·托雷斯 迈克尔·J·哈提格 列扎·甘迪 戴维·阿兰·利林 于 2019-12-20 设计创作，主要内容包括：公开的超结(SJ)器件包括形成SJ器件的第一SJ层的第一外延(epi)层,并且包括设置在第一SJ层上并形成SJ器件的器件层的第二epi层。第一epi层和第二epi层的有源区域包括：包括第一导电类型的特定掺杂浓度的第一组SJ柱、和包括第二导电类型的该特定掺杂浓度的第二组SJ柱。第一epi层和第二epi层的终端区域具有第一导电类型的小于该特定掺杂浓度的最小epi掺杂浓度,并且第二epi层的终端区域包括第二导电类型的多个浮空区,该多个浮空区形成SJ器件的结终端。(A Super Junction (SJ) device is disclosed that includes a first epitaxial (epi) layer forming a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer and forming a device layer of the SJ device. The active regions of the first epi layer and the second epi layer include: a first set of SJ pillars comprising a particular doping concentration of a first conductivity type, and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. The termination regions of the first and second epi layers have a minimum epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination region of the second epi layer includes a plurality of float-out regions of the second conductivity type that form junction terminations of the SJ device.)

1. A Super Junction (SJ) device (4) comprising:

a first epitaxial (epi) layer (14A, 14B, 14C) forming a first SJ layer of the SJ device; and

a second epi layer (14Z) disposed on the first SJ layer and forming a device layer of the SJ device, wherein the active regions (6) of the first and second epi layers include a first set of SJ pillars (62A, 64A) including a particular doping concentration of a first conductivity type and a second set of SJ pillars (62B, 64B) including the particular doping concentration of a second conductivity type, and wherein the termination regions (10) of the first and second epi layers include a minimum epi doping concentration of the first conductivity type that is less than the particular doping concentration, and wherein the termination regions of the second epi layer include a plurality of float-out regions of the second conductivity type forming junction terminations (12) of the SJ device.

2. The SJ device of claim 1, wherein the SJ device (4) is a silicon carbide (SiC) SJ device, and the minimum epi dopant concentration is less than or equal to 1.5 x 10¹⁵cm^-3。

3. The SJ device of claim 1, wherein the junction termination (12) comprises a Floating Field Ring (FFR), a single-zone Junction Termination Extension (JTE), a multi-zone JTE, a graded-zone JTE, a multi-float-zone JTE, a spatially modulated JTE, or a combination thereof.

4. The SJ device of claim 1, wherein the minimum epi dopant concentration is at least 50% less than the particular dopant concentration.

5. The SJ device of claim 1, wherein the first epi layer (14A, 14B, 14C) has a thickness of between 2 micrometers (μ ι η) and 15 μ ι η.

6. The SJ device of claim 1, wherein the first epi layer (14A) is disposed on a wide bandgap substrate layer (20) therebelow.

7. The SJ device of claim 1, wherein the first epi layer (14B, 14C) is disposed on a third epi layer (14A) that forms a second SJ layer of the SJ device, wherein the active region (10) of the third epi layer includes the first set of SJ pillars (62A) and the second set of SJ pillars (62B), the first set of SJ pillars including the particular doping concentration of the first conductivity type, the second set of SJ pillars including the particular doping concentration of the second conductivity type, and wherein the terminal region (10) of the third epi layer includes the minimum epi doping concentration of the first conductivity type.

8. The SJ device of claim 1, wherein the middle region (8) of the second epi layer (14Z) comprises modified SJ pillars (302) of the first conductivity type, wherein the modified SJ pillars comprise modified portions (306) having a doping concentration less than the particular doping concentration.

9. A method of manufacturing a Super Junction (SJ) device (4), comprising:

forming a first SJ layer (18A, 18B, 18C) by:

forming a first epitaxial (epi) layer (14A, 14B, 14C) on the base layer, wherein the first epi layer includes a minimum epi doping concentration of the first conductivity type;

implanting a first set of SJ pillars (62A) into an active region (6) of the first epi layer to produce a particular doping concentration of the first conductivity type, wherein the particular doping concentration is greater than the minimum epi doping concentration; and

implanting the active region (6) of the first epi layer to produce a second set of SJ pillars (62B) comprising the particular doping concentration of the second conductivity type; and

forming a device layer (16) by:

forming a second epi layer (14Z) over the first SJ layer, wherein the second epi layer includes the minimum epi doping concentration of the first conductivity type;

implanting a first set of device layer pillars (64A) into an active region (6) of the second epi layer to produce a second doping concentration of the first conductivity type that is less than the particular doping concentration;

implanting a second set of device layer pillars (64B) into an active region of the second epi layer to produce the particular doping concentration of the second conductivity type; and

forming a junction termination (12) in the device layer by injecting a plurality of floating regions (68) of the second conductivity type into the termination region (10) of the second epi layer.

10. The method of claim 9, wherein the SJ device is a silicon carbide (SiC) SJ device, and the minimum epi dopant concentration is less than or equal to 1.5 x 10¹⁵cm^-3。

11. The method of claim 9, wherein injecting the first set of SJ columns (62A) into the active region (6) of the first epi layer (14A, 14B, 14C) and injecting the second set of SJ columns (62B) into the active region (6) of the first epi layer comprises:

forming a first mask over first and second portions of an active area (10) of the first epi layer, and then patterning the first mask to selectively expose second portions of the active area of the first epi layer;

selectively injecting the first set of SJ pillars (62A) into the exposed second portion of the active area of the first epi layer;

forming a second mask over a second portion of the active area of the first epi layer to expose a first portion of the active area of the first epi layer and not to expose a second portion of the active area of the first epi layer;

selectively injecting the second set of SJ pillars (62B) into the exposed first portion of the active area of the first epi layer; and

removing the second mask to produce the first SJ layer (18A, 18B, 18C).

12. The method of claim 11, wherein the first mask, the second mask, or a combination thereof comprises a high energy implantation mask comprising silicon-on-insulator (SOI), polysilicon, thick silicon oxide, a metal layer, a resist layer, or a combination thereof.

13. The method of claim 9, wherein injecting the first set of SJ pillars (62A) into the active region (6) of the first epi layer (14A, 14B, 14C) or the first set of device layer pillars (64A) into the active region (10) of the second epi layer (14Z) comprises injecting at an injection energy greater than or equal to 500 kilo electron volts (keV) and less than or equal to 50 mega electron volts (MeV).

14. The method of claim 9, wherein the junction termination (12) comprises a Junction Termination Extension (JTE), wherein the JTE comprises a width five times less than a combined thickness of the first epi layer and the second epi layer.

15. The method of claim 9, wherein forming the device layer (16) comprises:

implanting a well region (40) of said second conductivity type in an active area (6) of said second epi layer (14Z) such that said well region extends from at least one of said second set of device layer pillars (62B) to a surface of said device layer; and

a source region (44) having the first conductivity type is implanted adjacent the well region in the active area of the second epi layer such that the source region extends to a surface of the device layer.

Background

The subject matter disclosed herein relates to wide bandgap power devices (e.g., silicon carbide (SiC) power devices), and more particularly to termination designs for wide bandgap Super Junction (SJ) power devices.

For semiconductor power devices, terminations (such as junction terminations) may be used to generally prevent electric fields from collecting near the edges of the active area of the device during reverse bias operation. As used herein, the term "junction termination" is intended to include termination structures that employ a floating or p/n junction electrically attached to a primary blocking junction as a means of shaping and controlling the electric field around the active region of the device. However, while terminations improve device reliability and operability, there are also costs associated with using terminations. For example, the termination typically occupies a certain amount of die area (referred to herein as the termination area) of the semiconductor power device. The termination region, along with other portions of the device (e.g., gate bus region, gate pad region, etc.), contributes to what is referred to herein as the overhead region of the device. Thus, while the active area of the device includes device cells (e.g., Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cells) for power conversion, the overhead area includes features that support the operation of these device cells.

Accordingly, it may be desirable to maximize the ratio of the active area to the overhead area of the device to improve performance. The wide termination results in a large termination area and a large overhead area, and this limits the amount of die area available for the active area of the device. Thus, by reducing the overhead area, the ratio of active area to overhead area may be increased, which may improve the efficiency and/or operation of the device.

Disclosure of Invention

In an embodiment, a Super Junction (SJ) device includes a first epitaxial (epi) layer forming a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer and forming a device layer of the SJ device. The active regions of the first epi layer and the second epi layer include: a first set of SJ pillars comprising a particular doping concentration of a first conductivity type, and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. The termination regions of the first and second epi layers have a minimum epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination region of the second epi layer includes a plurality of float-out regions of the second conductivity type that form junction terminations of the SJ device.

In another embodiment, a method of manufacturing a Super Junction (SJ) device includes forming a first SJ layer by: forming a first epitaxial (epi) layer on the base layer, wherein the first epi layer has a minimum epi doping concentration of the first conductivity type; implanting a first set of SJ pillars into an active region of the first epi layer to produce a particular doping concentration of the first conductivity type, wherein the particular doping concentration is greater than the minimum epi doping concentration; and implanting the active regions of the first epi layer to produce a second set of SJ pillars comprising the particular doping concentration of the second conductivity type. The method further includes forming a device layer by: forming a second epi layer on the first SJ layer, wherein the second epi layer has a minimum epi doping concentration of the first conductivity type; implanting a first set of device layer pillars into an active region of the second epi layer to produce a second doping concentration of the first conductivity type that is less than the particular doping concentration; implanting a second set of device layer pillars into the active region of the second epi layer to produce the particular doping concentration of the second conductivity type; and forming a junction termination in the device layer by injecting a plurality of floating regions having the second conductivity type into the termination region of the second epi layer.

In another embodiment, a silicon carbide (SiC) Superjunction (SJ) device includes a first Superjunction (SJ) layer formed in a first epitaxial (epi) layer of the SiC-SJ device, wherein a termination region of the first epi layer has a minimum epi doping concentration of the first conductivity type, wherein the minimum epi doping concentration is less than or equal to 1.5 x 10¹⁵cm^-3. The SiC-SJ device also includes a device layer formed in a second epi layer of the SiC-SJ device, wherein the second epi layer is disposed on the first SJ layer, and wherein a termination region of the device layer has a minimum epi doping concentration of the first conductivity type and a plurality of float-off regions of the second conductivity type forming junction terminations of the SiC-SJ device.

Drawings

These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

FIG. 1 is a schematic diagram illustrating a cross-sectional view of a portion of an embodiment of a multi-layer silicon carbide super junction (SiC-SJ) device having a termination region including a junction termination having a floating doped region in accordance with aspects of the present technique;

FIG. 2 is a top view of the SiC-SJ device of FIG. 1, in accordance with aspects of the present technique;

FIG. 3 is a graph plotting obtainable breakdown voltage as a function of Junction Termination Extension (JTE) width for an exemplary embodiment of the SiC-SJ device of FIG. 1 in accordance with aspects of the present technique;

FIG. 4 is a schematic diagram illustrating an embodiment of the SiC-SJ device of FIG. 1 including a termination region having a first width, including an equal rate line exhibiting an impact ionization rate present in a reverse bias state, in accordance with aspects of the present technique;

FIG. 5 is a schematic diagram illustrating another embodiment of the SiC-SJ device of FIG. 1 including a termination region having a second width, including isocratic lines exhibiting impact ionization rates present in a reverse biased state, in accordance with aspects of the present technique;

FIG. 6 is a graph illustrating termination regions in units of cubic centimeters (cm) of an exemplary embodiment of a SiC-SJ device according to FIG. 1 in accordance with aspects of the present technique^-3) The epi doping concentration of the semiconductor substrate;

FIG. 7 is a schematic diagram illustrating a cross-sectional view of an embodiment of the SiC-SJ device of FIG. 1 including a termination region having a first epi doping concentration, including isocratic lines exhibiting impact ionization rates present in a reverse biased state, in accordance with aspects of the present technique;

FIG. 8 is a schematic diagram illustrating a cross-sectional view of another embodiment of the SiC-SJ device of FIG. 1 including a termination region having a second epi doping concentration, including an isocratic line exhibiting the impact ionization rate present in a reverse bias state, in accordance with aspects of the present technique;

figure 9 is a flow diagram of a process for fabricating an embodiment of a wide bandgap SJ device having one or more junction terminations, in accordance with aspects of the present technique;

FIG. 10 is a cross-sectional view of an embodiment of an intermediate structure formed during fabrication of the SiC-SJ device of FIG. 1, wherein the intermediate structure has a first epitaxial (epi) layer formed on a substrate layer, in accordance with aspects of the present technique;

FIG. 11 is a cross-sectional view of the embodiment of the intermediate structure of FIG. 10 after forming several SJ layers and device layers, in accordance with aspects of the present technique;

FIG. 12 is a cross-sectional view of an embodiment of the intermediate structure of FIG. 11 after a Junction Termination Extension (JTE) has been implanted into the termination region of the device layer, in accordance with aspects of the present technique;

FIG. 13 is a cross-sectional view of a portion of an embodiment of a SiC-SJ device having a termination region that includes JTE, in accordance with aspects of the present technique;

FIG. 14 is an enlarged view of an embodiment of the SiC-SJ device of FIG. 13, in accordance with aspects of the present technique;

FIG. 15 is a graph illustrating absolute net doping concentration as a function of distance along lines A and B of FIG. 14 in accordance with aspects of the present technique;

fig. 16 is a graph illustrating breakdown voltage as a function of doping-modified depth for the SJ pillars of the first conductivity type closest to the termination region in accordance with aspects of the present technique;

FIGS. 17A and 17B illustrate the collision incidence in a reverse bias condition of an embodiment of the SiC-SJ device of FIG. 13 broken down in the termination region and the active region of the device, respectively, in accordance with aspects of the present technique; and

fig. 18 is a graph illustrating breakdown voltage as a function of dopant concentration in a doping modification of a modified SJ column in accordance with aspects of the present technique.

Detailed Description

One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in an engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, when introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be open-ended and mean that there may be additional elements other than the listed elements. In addition, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. If certain ranges are disclosed, the endpoints of all ranges directed to the same component or property are inclusive and independently combinable. The modifier "about" used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., includes the degree of process variation or error associated with measurement of the particular quantity). The modifier "substantially" when used in connection with a descriptive term is intended to convey that the descriptive term applies principally, substantially, or in most cases (e.g., for greater than 90%, greater than 95%, or greater than 99%) and may be used to account for limited exceptions that may arise due to process variations and technical limitations as understood by those skilled in the art.

As used herein, the term "layer" refers to a material that is disposed in a continuous or discontinuous manner on at least a portion of an underlying surface. Further, the term "layer" does not necessarily mean that the disposed material has a uniform thickness, but the disposed material may have a uniform or variable thickness. Further, the term "layer" as used herein refers to a single layer or a plurality of layers, unless the context clearly dictates otherwise. As used herein, the term "adjacent" means that two layers or features are disposed consecutively and in direct contact with each other. In the present disclosure, when a layer/device is described as being "on" another layer or substrate, it is to be understood that the layers/devices can be in direct contact with each other or have one (or more) layer(s) or feature(s) between layers and between devices. Furthermore, the term "on … …" describes the relative position of layers/devices with respect to each other and does not necessarily mean "on top of … …" as the relative position above or below depends on the orientation of the device with respect to the viewer. Moreover, the use of "top," "bottom," "above," "below," "upper," "buried," and variations of these terms is made for convenience, and does not require any particular orientation of the components unless otherwise specified. With this in mind, as used herein, the terms "under", "buried", "intermediate" or "bottom" refer to features that are relatively closer to the substrate layer (e.g., epitaxial layers, termination regions), while the terms "top" or "upper" refer to particular features that are relatively furthest from the substrate layer (e.g., epitaxial layers, termination regions).

The present embodiments relate to designs and methods for manufacturing wide bandgap Super Junction (SJ) power devices, such as silicon carbide super junction (SiC-SJ) power devices. The disclosed designs and methods may be used to fabricate SJ devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Junction Field Effect Transistors (JFETs), Bipolar Junction Transistors (BJTs), diodes, and other SJ devices that may be used for medium voltage (e.g., 2kV-10kV) and high voltage (e.g., greater than or equal to 10kV) power conversion related applications. As discussed below, the disclosed SJ device design includes a multi-layer termination region that is achieved using repeated epitaxial growth and dopant implantation steps. As used herein, the term "multilayer" and references to a particular number of layers (e.g., "two", "three", "four") refer to the number of epitaxial layers (referred to herein as epi layers).

More particularly, the present embodiments relate to designs and methods for fabricating power device terminals (such as junction terminals) for wide bandgap SJ devices (e.g., SiC-SJ devices). As described above, the junction termination is a termination structure that employs a p/n junction, which is either floating or electrically attached to the main blocking junction, as a means of shaping and controlling the electric field around the active region of the device. In general, the disclosed termination design satisfies a number of design parameters to provide an effective edge termination for wide bandgap SJ devices. For example, the disclosed termination design provides a breakdown voltage that is close to or equal to (e.g., 90% or more) the device should have (event), while reducing the termination width. The disclosed termination design is also relatively robust to process variations (e.g., dopant concentration in the implanted region, dopant concentration in the epitaxial layer, percentage of doping activation, etc.). The disclosed termination design consumes a smaller portion of the die area and is relatively inexpensive to manufacture relative to typical junction termination designs. For example, certain disclosed SJ device embodiments may be fabricated using common semiconductor fabrication equipment (such as high volume ion implantation systems used in existing Si/SiC device fabrication) to provide additional cost advantages.

As discussed in detail below, the disclosed SJ termination design includes one or more n-type and/or p-type doped regions arranged in a particular manner to form a junction termination, such as a Junction Termination Extension (JTE), to allow for a gradual reduction in the magnitude of the electric field outside of the active region (e.g., the conductive region) of the SJ power device under reverse bias conditions. In various embodiments, these doped regions may be implemented as unconnected blocks, continuous pillars, bars, segments, grids, dots, or any other suitable shape. In some embodiments, these doped regions may be described as "floating," meaning that they are not in electrical contact with the device terminals or under an externally applied bias; however, in other embodiments, at least a portion of these regions may be in electrical contact with device terminals. The location and dimensions of these implanted regions in the termination region of the disclosed SJ device are designed to achieve a high blocking voltage to prevent premature breakdown of the device due to electric field crowding effects and to allow reliable operation of these devices, especially when subjected to long-term high temperature/high voltage operation. Furthermore, by using high energy ion implantation to control the doping of the epitaxial (epi) layer within the active area of the SJ device, and for example by controlling the epi doping in the termination area of the device, the disclosed termination design occupies significantly less die area than conventional junction termination designs, which significantly increases the ratio of active area to overhead area without a performance loss in terms of breakdown voltage.

It will be appreciated that for this embodiment, the epi layer of the SJ device may be formed at a minimum controllable doping level, e.g., without any intentional epi doping (e.g., without any dopants intentionally introduced), or at a minimum doping level that allows control of the doping type (n or p) within a specified low concentration range. However, it should be appreciated that because impurities, such as nitrogen, may be present in the instruments and/or tools used during the epitaxial growth process, the epi layer may still include a small amount of epi doping (e.g., of the first conductivity type (n-type)), referred to herein as the "minimum epi doping concentration". Thus, while the epi layer may be formed without an intentional doping concentration, the actual epi doping concentration of the epi layer may generally be 8.0 × 10¹³cm^-3Or higher depending on the equipment used for epitaxial growth. For example, in certain embodiments discussed below, the minimum epi doping concentration of the first conductivity type (e.g., n-type) may be less than 3.0 x 10¹⁵cm^-3Less than 2X 10¹⁵cm^-3Less than 1X 10¹⁵cm^-3Or at 8X 10¹³cm^-3And 2X 10¹⁵cm^-3In the meantime. For example, when the first conductivity type is n-type, nitrogen, phosphorus, arsenic, antimony, or the like may be used as a dopant. Alternatively, when the first conductivity type is p-type, boron, aluminum, or the like may be used as a dopant.

As discussed below, after each epi layer having such a minimum epi doping concentration is formed, dopants of the first conductivity type and the second conductivity type are implanted into portions of the active region of the device using a High Energy (HE) implant operation to form SJ pillars of the SJ layer. Additionally, the top or device epi layer may also be implanted one or more times to form device structures (e.g., well regions, source regions, etc.), and in some embodiments, these implantation operations may be performed using standard energy implantation processes. For example, at a doping concentration having a minimum epi (e.g., atLess than or equal to 3X 10¹⁵cm^-3) After the SJ pillars are formed using the HE implantation operation in the epi layer, a portion of the SJ pillars of the active region of the epi layer have a particular doping concentration of the first dopant type (e.g., greater than or equal to 5x 10)¹⁵cm^-3) And the remaining SJ pillars may have a particular doping concentration of the second dopant type (e.g., greater than or equal to 5x 10)¹⁵cm^-3). Additionally, as discussed below, in some embodiments, some SJ pillars may include modified portions having relatively reduced dopant concentrations, where the reduced dopant concentrations and the depth of the modified portions also affect the breakdown characteristics of the SJ devices.

In view of the above, fig. 1 shows a cross-sectional view of an embodiment of a SiC-SJ device 4 having an active region 6 and an intermediate region 8, and a termination region 10 having junction terminations, such as Junction Termination Extensions (JTEs) 12, according to an embodiment of the present scheme. It will be appreciated that certain well-known design elements (e.g., top metallization, passivation, etc.) may be omitted in order to more clearly show certain components of the SiC-SJ device 4. It is also understood that although device 4 is described herein in the context of a SiC-SJ device, other wide bandgap materials (e.g., germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), boron nitride, gallium arsenide (GaAs), diamond (C), etc.) may be used in other embodiments in accordance with the present disclosure.

The illustrated embodiment of the SiC-SJ device 4 includes several epitaxial (epi) layers 14. These epi layers include epi layer 14Z, which forms device layer 16 of SiC-SJ device 4, and epi layers 14A, 14B, and 14C, which form Superjunction (SJ) layers 18A, 18B, and 18C, respectively, of SiC-SJ device 4. Although the illustrated embodiment includes four epi layers 14, in other embodiments, the SiC-SJ device 4 may include any suitable number of epi layers 14 (e.g., 2, 3, 4, 5, 6, or more) to produce a SiC-SJ device 4 having a particular desired voltage rating. The epi layer 14 may be fabricated using repeated cycles of epitaxial overgrowth. As shown, a first epi layer 14A is formed and disposed directly on substrate layer 20, and a second epi layer 14B is formed and disposed directly on first epi layer 14A. Further, a third epi layer 14C is formed and disposed directly on second epi layer 14B, and a fourth epi layer 14Z (e.g., a device epi layer) is formed and disposed directly on third epi layer 14C. In other embodiments, the SiC-SJ device 4 may include additional epi layers 14 (e.g., 14D, 14E, 14F, etc.) including any suitable number of SJ layers 18 interposed between the first epi layer 14A and the device epi layer 14Z and/or disposed below the first epi layer 14A.

For the embodiment shown in fig. 1, in active region 6, top surface 42 of device layer 16 includes a well region 40 (e.g., p-well region 40) having the second conductivity type disposed adjacent a source region 44 (e.g., n-type source region 44) having the first conductivity type. A dielectric layer 46 (also referred to as a gate insulating layer or gate dielectric layer) is disposed adjacent device layer 16, and a gate electrode 48 is disposed adjacent dielectric layer 46. Further, a SJ layer 18 is disposed on substrate layer 20 (e.g., semiconductor substrate layer, wide bandgap substrate layer), and a drain contact 50 is disposed on a bottom 52 of SiC-SJ device 4 adjacent substrate layer 20. As additionally illustrated in the embodiment of fig. 1, source contact 54 is disposed adjacent top surface 42 of device layer 16 and is disposed on a portion of both source region 44 and well region 40 of device layer 14Z.

During the illustrated on-state operation of the SiC-SJ device 4, the appropriate gate voltage (e.g., equal to or higher than the threshold voltage (V) of the SiC-SJ device 4)_TH) Creates inversion layer formation in the channel region 56 and an enhanced conduction path in the Junction Field Effect Transistor (JFET) region 58 due to carrier accumulation, allowing current to flow from the drain contact 50 (e.g., drain electrode, drain terminal) to the source contact 54 (e.g., source electrode, source terminal) within portions of the active region 6 and/or in the intermediate region 8. Channel region 56 may generally be defined as an upper portion of well region 40 that is disposed below gate electrode 48 and dielectric layer 46.

To reduce on-state resistance (rds (on)) and the on-state conduction losses that result therefrom, SiC-SJ device 4 includes SJ regions 60, which may have any suitable number of SJ layers 18 formed in active regions 6 and/or intermediate regions 8 of SiC-SJ device 4. Each SJ layer 18 includes a first set of implanted SJ pillars 62A that are oppositely doped relative to a second set of implanted SJ pillars 62B. In other words, the first set of SJ pillars 62A has a first conductivity type (e.g., n-type SJ pillars 62), while the second set of SJ pillars 62B has a second conductivity type (e.g., p-type SJ pillars 62). In some embodiments, the first set of SJ pillars 62A may be doped with nitrogen, phosphorous, or other suitable n-type dopant, while the second set of SJ pillars 62B are doped with boron, aluminum, or other suitable p-type dopant, or vice versa.

Further, the dopant concentration in the first set of SJ columns 62A and the second set of SJ columns 62B of the SJ region 60 are approximately the same (e.g., ± 3%, ± 2%, ± 1%). For example, in some embodiments, each of the first set of SJ pillars 62A and each of the second set of SJ pillars 62B may have a width greater than 5 × 10¹⁵cm^-3And/or less than 1 x 10¹⁷cm^-3Dopant concentration of (a). In some embodiments, first set SJ pillars 62A and second set SJ pillars 62B are each generally designed to be substantially depleted and provide a similar amount (e.g., substantially equal amount) of effective charge (e.g., per square centimeter (cm) from ionized dopant under reverse bias^-2) Normalized to the device active area 6). Thus, the illustrated superjunction structure allows the SiC-SJ device 4 to achieve a high breakdown voltage and low on-state resistance, since both the p-type semiconductor portion and the n-type semiconductor portion are substantially (e.g., fully) depleted in the nominal blocking state.

In certain embodiments, the respective thicknesses 65A, 65B, 65C, and 65Z of the first epi layer 14A, the second epi layer 14B, the third epi layer 14C, and the device epi layer 14Z may be the same or different. For example, in certain embodiments, the thickness 65 (e.g., 65A, 65B, 65C, and 65Z) of the epi layer 14 may be between 2 micrometers (μm) and 15 μm (e.g., 10 μm or 12 μm). Additionally, the SJ pillars 62 in the SJ region 60 of the SiC-SJ device 4 are shown to have a particular depth (e.g., extending along the Y-axis). It should be understood that in some embodiments, the depth of the SJ pillars 62 may be the same between the first set of SJ pillars 62A and the second set of SJ pillars 62B. In some embodiments, for example, each SJ post 62 can extend through the entire thickness 65A of epi layer 14A and can contact (e.g., be electrically coupled to) substrate layer 20. Alternatively, each SJ pillar 62 may not extend through the entire thickness 65A of the first epi layer 14A, leaving a gap (e.g., epi-doped region) between the SJ pillar 62 and the substrate layer 20. Further, in some embodiments, each of the first set of SJ pillars 62A may contact (e.g., be electrically coupled to) at least one of a first set of device layer pillars 64A (e.g., n-type device layer pillars) having a similar conductivity type, and each of the second set of SJ pillars 62B may contact (e.g., be electrically coupled to) at least one of a second set of device layer pillars 64B (e.g., p-type device layer pillars) having a similar conductivity type, as described in more detail below. It can be appreciated that because the first set of device layer pillars 64A and the second set of device layer pillars 64B are not charge balanced due to other structures in the device layer, these device layer pillars are not themselves SJ structures in technology. However, for convenience, for certain embodiments, device layer pillars 64A and 64B may be described herein as part of SJ pillars 62A and 62B, respectively.

Further, the depth of the SJ columns 62 may be different in different SJ layers 18 of the SJ section 60. For example, as shown in fig. 1, each of the first and second sets of SJ columns 62A, 62B in the first SJ layer 18A has a depth 67, and each of the first and second sets of SJ columns 62A, 62B in the second SJ layer 18B has a depth 69. A first set SJ of SJ columns 62A and a second set SJ of SJ columns 62B in second SJ layer 18B extend through the entire thickness 65B of epi layer 14B. By extending through thickness 65B of epi layer 14B, a continuous vertical SJ column 62 may be formed from each SJ layer 18 in SJ zone 60. The continuous vertical SJ pillars 62 may then provide low conduction losses and high blocking voltage. It should be understood that for the illustrated embodiment, the total depth of the first set of SJ columns 62A is equal to the sum of the respective depths (e.g., 67, 69, and 71) of the first set of SJ columns 62A in the first SJ layer 18A, the second SJ layer 18B, and the third SJ layer 18C. Similarly, the total depth of the second set of SJ columns 62B is equal to the sum of the respective depths (e.g., 67, 69, and 71) of the second set of SJ columns 62B in the first SJ layer 18A, the second SJ layer 18B, and the third SJ layer 18C.

With respect to size, each SJ post 62 may have a particular width 73. In some embodiments, the size (e.g., width 73) of the SJ pillars 62 may vary along the Y-axis. Further, the size of the first set of SJ pillars 62A may vary relative to the size of the second set of SJ pillars 62B. Further, the SJ pillars 62 may have different cross-sectional shapes (e.g., defined by a mask set used during implantation). However, the size of the first set of SJ columns 62A in the first SJ layer 18A generally matches the size of the corresponding first set of SJ columns 62A in the other SJ layers 18 (e.g., SJ layer 18B). Similarly, the size of the second set of SJ columns 62B in the first SJ layer 18A may match the size of the corresponding second set of SJ columns 62B in the other SJ layers 18 (e.g., SJ layer 18B) such that the corresponding first set of SJ columns 62A and the corresponding second set of SJ columns 62B of each SJ layer 18 are aligned with each other.

Further, it should be understood that the doping of epi layer 14, the doping of SJ pillars 62, the thickness 65 of epi layer 14, the depth of SJ pillars 62 (e.g., 67, 69, 71), and the width 73 of SJ pillars 62 may be varied for different embodiments to achieve a desired electrical performance (e.g., a desired breakdown voltage) of SiC-SJ device 4. For example, in some embodiments, certain device parameters (e.g., thickness 65 and doping of epi layer 14) may be selected to provide a breakdown voltage of SiC-SJ device 4 of between about 1 kilovolt (kV) and 10kV, between 1kV and 5kV, or any other suitable range. Further, in some embodiments, the dopant concentration of the SJ pillars 62 may be about 5 × 10¹⁵cm^-3And about 1X 10¹⁷cm^-3In the meantime. Further, in some embodiments, for example, the SiC-SJ device 4 may include fewer or additional SJ layers 18 (e.g., two SJ layers 18, three SJ layers 18, four SJ layers 18, etc.) to obtain a desired voltage rating.

For certain semiconductor materials with low dopant diffusion coefficients, it may be difficult to fabricate a continuous vertical superjunction column extending through thickness 65 of epi layer(s) 14. For example, for embodiments in which the epi layer 14 is fabricated from SiC (which has a lower dopant diffusion coefficient than silicon (Si)), fabricating such SJ pillars 62 may be difficult. For example, to form SJ pillars 62 (and device pillars 64) that extend through the entire thickness 65 of one or more epi layers 14, at least in some cases as is present in a complete SJ device, a number (e.g., 10+) of thin epitaxial growth/shallow ion implantation steps may be performed. In addition, a combination of low energy implantation (e.g., an implantation acceleration energy of less than 0.5 megaelectron volts (MeV)) and high energy implantation (e.g., an implantation acceleration energy of greater than 0.5 MeV) may be used to inject the SJ column 62. For example, implant acceleration energies greater than 0.1MeV and/or less than 50MeV may be used. For example, in some embodiments, an implant acceleration energy between 0.1MeV and 30MeV may be employed. Thus, the intrusion range (e.g., penetration depth) of the most commonly used SiC dopants (e.g., boron, nitrogen, phosphorous, aluminum) is approximately between 2 microns (μm) and 15 μm, which is at least suitable for implanting SJ pillars 62 through epi layer 14 having a thickness between 2 μm and 15 μm. Further, in some embodiments, a suitable energetic mask material (e.g., silicon-on-insulator (SOI), polysilicon, thick silicon oxide, and high-Z metal) may be employed during implantation of the SJ pillars 62 and device pillars 64, as described in more detail below.

Additionally, for the embodiment shown in fig. 1, device layer 16 includes a first set of device layer pillars 64A and a second set of device layer pillars 64B implanted in active region 6 and intermediate region 8. The first set of device layer pillars 64A has the same conductivity as the first set of SJ pillars 62A, while the second set of device layer pillars 64B has the same conductivity as the second set of SJ pillars 62B. Thus, the first set of device layer pillars 64A are oppositely doped relative to the second set of device layer pillars 64B. In other words, the first set of device layer pillars 64A have a first conductivity type (e.g., n-type device layer pillars 64), while the second set of device layer pillars 64B have a second conductivity type (e.g., p-type device layer pillars 64). Further, as shown, the first set of device layer pillars 64A are in contact with and electrically coupled to a first set of SJ pillars 62A in the third epi layer 14C (e.g., SJ layer 18C). Further, the second set of device layer pillars 64B are in contact with and electrically coupled to a second set of SJ pillars 62B in the third epi layer 14C (e.g., SJ layer 18C), the well regions 40 have the same conductivity type as the second set of device layer pillars 64B, and/or the well regions 66 in the intermediate region 8 have the same conductivity type as the second set of device layer pillars 64B. Thus, in some embodiments, as described above with reference to the set of SJ pillars 62, the first set of device layer pillars 64A and/or the second set of device layer pillars 64B may be implanted according to any suitable means, such as using a high-energy implant, a low-energy implant, or a combination thereof.

In some embodiments, the dopant concentration in the first set of device layer pillars 64A and the second set of device layer pillars 64B of device layer 16 are about the same (e.g., one embodiment is a single device layer with a single device layer in each of the first and second sets of device layer pillars 64A, 64B)Such as + -3%, + -2%, + -1%). For example, in some embodiments, first set SJ pillars 62A and second set SJ pillars 62B are each generally designed to be substantially depleted and provide a similar amount (e.g., substantially equal amount) of effective charge (e.g., per square centimeter (cm) from ionized dopant under reverse bias^-2) Normalized to the device active area 6). Further, in some embodiments, the dopant concentration in the first and second sets of device layer pillars 64A, 64B of device layer 16 is about the same (e.g., ± 3%, ± 2%, ± 1%) as the dopant concentration in the first and second sets of SJ pillars 62A, 62B. In such an embodiment, first and second sets of device layer pillars 64A and 64B may be included within first and second sets of SJ pillars 62A and 62B, respectively, and SJ layer 18Z or portions of the SJ layer may be formed within device layer 16.

In other embodiments, the dopant concentration in the first set of device layer pillars 64A is different than the dopant concentration in the second set of device layer pillars 64B of device layer 16. For example, the dopant concentration in the second set of device layer pillars 64B may be about the same as the dopant concentration in the second set of SJ pillars 62B (e.g., ± 3%, ± 2%, ± 1%), while the dopant concentration in at least one of the first set of device layer pillars 64A may be lower than the dopant concentration in the second set of device layer pillars 64B and/or the dopant concentration in the first set of SJ pillars 62A, as discussed below with respect to fig. 13-18. In such an embodiment, premature avalanche breakdown at the interface of termination region 10 and intermediate region 8 and/or active region 6 may be reduced when the specific on-state resistance of SiC-SJ device 4 may be greater than the on-state resistance of SiC-SJ device 4 having substantially equal dopant concentrations in first and second sets of device layer pillars 64A and 64B. Thus, as discussed below, the maximum breakdown voltage of the SiC-SJ device 4 may be increased compared to other device designs.

As described above, the termination region 24 disposed in the termination region 10 of the SiC-SJ device 4 may have a doping concentration of the first conductivity type corresponding to the minimum epi doping concentration. Further, as discussed in more detail below, within active region 6 and/or intermediate region 8, the doping concentrations of first set of SJ pillars 62A and second set of SJ pillars 62BThe degree is significantly greater (e.g., 2, 3, 5, 10, or more times) than the minimum epi doping concentration of the termination region 24. For example, in some embodiments, the doping concentration of the first conductivity type in the first set of SJ pillars 62A and the doping concentration of the second conductivity type in the second set of SJ pillars may be greater than or equal to 5x 10¹⁵Per cubic centimeter (cm)^-3) And/or less than 1 x 10¹⁷cm^-3E.g. 1.0 x 10¹⁶cm^-3. Furthermore, the doping concentration of the first conductivity type in some portions of the epi layer (e.g., the termination region 24, the first set of SJ pillars 62A, and/or the second set of SJ pillars 62B, respectively) may be the same or different within a certain device region (e.g., the termination region 10, the middle region 8, and/or the active region 6).

For the embodiment shown in fig. 1, termination region 10 includes a junction termination (i.e., JTE 12) in termination region 24Z of device layer 16. In some embodiments, JTE12 includes several implant regions of dopants of the second conductivity type (e.g., p-type) that extend from intermediate region 8 across width 11 and are used to reconfigure the electric field in at least termination region 10 of SiC-SJ device 4. In certain embodiments, these implanted regions include the float-out regions 68, which are implemented in the SiC-SJ device 4 of fig. 1 as unconnected, implanted dopant blocks. When the floating regions 68 are arranged as disclosed, they gradually reduce the strength of the electric field outside the active region 6 of the SiC-SJ device 4 during the high-voltage blocking operation. Additionally, the SiC-SJ device 4 may also include several passivation layers 70 disposed on the device layer 16 in the termination region 10, which may be formed of one or more dielectric materials that help reduce the electric field above the device layer 16.

As noted above, the floating regions 68 of the SiC-SJ devices 4 shown are regions of opposite conductivity type relative to the minimum epi doping of the epi layer 14Z (e.g., termination region 24Z) in which they are located. When the embodiment of the SiC-SJ device 4 shown in fig. 1 is in the off state under reverse bias, the floating regions 68 are depleted to provide ionized dopants (immobile charges) that, when appropriately sized, shaped, and positioned relative to the X-axis and Z-axis, allow the electric field to be reconstructed within the perimeter of the SiC-SJ device 4 (e.g., within the termination region 10). More specifically, when the floating regions 68 are depleted under reverse bias, they prevent electric field peaks and provide an electric field distribution that gradually decreases in magnitude with increasing distance from the active region 6 of the SiC-SJ device 4. Under reverse bias, the particular electric field distribution in the termination region 10 of the SiC-SJ device 4 depends, for example, on the dopant distribution (e.g., dopant concentration, size and location of the float-off regions 68).

For the embodiment of the SiC-SJ device 4 shown in fig. 1, the float-out regions 68 have a particular depth 72. In other embodiments, the floating region 68 may extend through the entire thickness of the device epitaxial layer 14Z (e.g., thickness 65Z). Additionally, for the embodiment shown in fig. 1, the width 74 of the float-off regions 68 and the spacing 76 between the float-off regions 68 in the termination region 10 vary (e.g., decrease or increase) as the distance from the active region 6 of the SiC-SJ device 4 increases to provide a gradual decrease in the effective sheet doping concentration (effective sheet doping concentration) in the termination region 10. It will be appreciated that in other embodiments, the width 74 of the floating-out regions 68 decreases significantly with increasing distance from the active region 6, while the spacing 76 between the floating-out regions 68 remains substantially constant. In still other embodiments, the spacing 76 between the float-out regions 68 increases significantly with increasing distance from the active region 6, while the width 74 of the float-out regions 68 remains substantially constant. Further, in some embodiments, the SiC-SJ device 4 may include at least one additional JTE12 in at least one buried epi layer 14 (e.g., SJ layer 18). That is, for example, while the illustrated embodiment includes a single JTE12, it is understood that in some embodiments, the SiC-SJ device 4 may include a respective JTE12 (e.g., 12B, 12C, 12D, etc.) in each epi layer 14. Alternatively, the SiC-SJ device 4 may include a JTE12 for each epi layer in a set of epi layers 14, such that the JTE12 is adjacent to every other epi layer 14, every third epi layer 14, and so on. Thus, in some embodiments, the float zones 68 of each epi layer 14 may have different depths 72, widths 74, and spacings 76. For such an embodiment, one or more masking/photolithography steps may be used to fabricate JTE12 for each epi layer 14.

Furthermore, in some instancesIn embodiments, the disclosed float-out region 68 may have one or more characteristics (e.g., doping, width, depth, spacing, etc.), as described FOR the float-out region in co-pending U.S. patent application No. 16/060,549 entitled EDGE TERMINATION design FOR SILICON CARBIDE SUPER JUNCTION POWER DEVICES, filed on 8.6.2018, the disclosure of which is incorporated herein by reference in its entirety FOR all purposes. For example, in some embodiments, the width 74 of each of the float-out regions 68 may be between 0.8 microns (μm) and about 5 μm, while the spacing 76 between the float-out regions 68 may be generally less than the thickness of the corresponding epi layer 14 in which the float-out regions 68 are disposed (e.g., the thickness 65Z of the epi layer 14Z of the device). Further, the depth 72 of each of the float-out zones 68 may be about 1 μm. Furthermore, the overall charge (e.g., dose) of JTE12 may be at 6X 10¹²cm^-2And 3X 10¹³cm^-2In the meantime. For example, in some embodiments, the overall charge of JTE12 may be 1.6 × 10¹³cm^-2。

JTE12 described herein provides an illustrative example of junction termination, and more specifically, JTE12 described herein depicts an illustrative example of a graded region JTE. However, in some embodiments, an implanted region having a second conductivity type (e.g., p-type), such as the floating region 68, may additionally or alternatively be implemented to have one or more characteristics corresponding to another termination and/or junction termination structure. For example, the implant region may be implemented as a single region JTE (which may include a single implant region in contact with the interwell region 66), and/or as a multi-region JTE (which may include two or more interconnected implant regions). In some embodiments, the two or more interconnected implant regions may have the same or different characteristics, and at least one of the two or more interconnected implant regions may contact the intermediate well region 66. Additionally, in some embodiments, an implant region may be implemented to form a multi-float region JTE. In such an embodiment, the first implant region may contact the intermediate well region 66, while a set of additional implant regions (such as the floating regions 68) having different spacings and/or widths may be implanted separately from the first implant region and from each other. Further, in some embodiments, an implant region (e.g., the float-out region 68) may be implemented to form a Float Field Ring (FFR) termination. In such an embodiment, the floating regions 68 may be implanted without connecting to each other and without connecting to the intermediate well regions 66. Additionally or alternatively, an implant region may be implemented to form a spatially modulated JTE, which may include a first implant region in contact with the intermediate well region and unconnected to an additional set of implant regions implanted to form an FFR. Thus, it is to be understood that the techniques described herein may be applied to any suitable junction termination (such as single-region JTE, multi-region JTE, graded JTE, multi-float-region JTE, FFR, spatially modulated JTE, etc.), and the embodiments described herein are intended to be illustrative and not limiting.

Fig. 2 shows a top view (view perpendicular to fig. 1) of the SiC-SJ device 4 according to an embodiment of the present scheme. More specifically, fig. 2 illustrates a top view of an embodiment of a SiC-SJ device 4 having a termination region 10 that includes a floating void region 68 implemented as a disconnected doped block. In particular, fig. 2 shows a top view of JTE12 and a cross-section 100 revealing SJ layer 18C. In other words, JTE12 and SJ layers 18C are shown in the same top view. However, it is understood that the SJ layer 18C may be disposed at a different depth (e.g., along the Y-axis) than the JTE12, as indicated by the cross-section.

For the embodiment shown in FIG. 2, each of the float-out zones 68 has a particular length 78 along the Z-axis and an additional spacing 80. In some embodiments, the length 78 of each of the float-out regions 68 may be between 0.8 μm and about 5 μm, while the additional spacing 80 between the float-out regions 68 may be generally less than the thickness 65 of the corresponding epi layer 14 in which the float-out regions 68 are disposed (e.g., the thickness 65Z of the epi layer 14Z of the device). Although the floating empty regions 68 are illustrated as unconnected blocks to each other, the floating empty regions 68 may be implemented as unconnected blocks to each other, as continuous columns, bars, segments, grids, dots, or any other suitable shape. Accordingly, the length 78 and the additional spacing 80 between the float-out regions 68 may vary between certain embodiments. Further, as described above, the floating void region 68 may be implemented to have characteristics (e.g., length 78, additional spacing 80, etc.) for forming alternative termination and/or junction termination structures. Accordingly, the embodiments disclosed herein are intended to be illustrative and not restrictive.

In some embodiments, reconstructing the electric field of the SiC-SJ device 4 may include forming JTEs 12 such that avalanche breakdown (a result of impact ionization) occurs outside the termination region 10 (e.g., within the active region 6 and/or the intermediate region 8) at the nominal voltage rating. That is, for example, in some embodiments avalanche breakdown may occur in isolation in active region 6 and/or intermediate region 8, which may maximize the breakdown voltage of SiC-SJ device 4, thereby achieving a breakdown voltage that is close to or equal to what the device should have. Briefly referring back to fig. 1, it can be appreciated that in a conventional SiC device (e.g., having 5.0 x 10 in termination region 24)¹⁵cm^-3Or higher epi dopant concentration) the width 11 of JTE12 may be greater than or equal to five times (5x) the one-dimensional (1-D) depletion width of the device, where the 1-D depletion width may be approximately equal to the epi thickness of active region 6 (e.g., the sum of thicknesses 65 of epi layers 14), in order to limit avalanche breakdown to only active region 6 and/or intermediate region 8. That is, for example, in a conventional device, the ratio of the width 11 of JTE12 to the 1-D depletion width of the device may be 5: 1. However, as shown in graph 120 shown in FIG. 3, to achieve a peak (e.g., maximum) breakdown voltage in a SiC-SJ device 4 having one or more SJ layers 18 and having termination regions 24 with the smallest epi doping concentration, the ratio of the width 11 of JTE12 to the 1-D depletion width of the SiC-SJ device 4 may be significantly reduced. For example, as described in more detail below, graph 120 shows that for a SiC-SJ device design having JTEs 12 with widths 11 greater than or equal to 2.75x (e.g., between 2.75x and 5x, between 2.75x and 4x, between 2.75x and 3 x) of the 1-D depletion width of SiC-SJ device 4, avalanche breakdown may be limited to only within active region 6 and/or intermediate region 8. Thus, by using the disclosed JTE design, it is now recognized that for SiC-SJ devices 4, the ratio of active regions 6 to overhead regions (e.g., including termination regions 10) of SiC-SJ devices 4 may be increased. Thus, the die area available for the active area 6 may be increased. It may be noted that, as discussed below, in certain embodiments, it may be desirable to have termination regions 10 in the SiC-SJ devices 4Breakdown occurs at JTE 12. For such embodiments, the disclosed junction termination design may also enable a breakdown voltage to approach or equal the device's intended breakdown voltage with a reduced termination width 11.

More specifically, graph 120 depicts an example of the achievable breakdown voltage of SiC-SJ device 4 that varies according to the width 11 of JTE12 (e.g., the width of termination region 10). For the illustrated example of the SiC-SJ device 4 in FIG. 3, the 1-D depletion width is 40 μm. Thus, the ratio of the width 11 of JTE12 (e.g., the width of termination region 10) to the 1-D depletion width of SiC-SJ device 4 may be determined by dividing the width 11 by 40 μm. However, it is understood that the ratio of the width 11 of JTE12 (e.g., the width of termination region 10) to the 1-D depletion width of SiC-SJ device 4 described herein may be extended to SiC-SJ device designs having any suitable 1-D depletion width. Accordingly, the embodiments described herein are intended to be illustrative and not restrictive.

On the left side of line 122 (e.g., for a ratio of JTE12 width 11 to the device's 1-D depletion width below about 2.75), avalanche breakdown occurs at JTE12 (e.g., termination region 10) and/or at the intersection of JTE12 and intermediate well region 66. To aid in illustration, a cross-sectional view of a portion of an embodiment of a SiC-SJ device 4 having a JTE12 with a width 11 of 100 μm (e.g., the ratio of the width 11 of the JTE12 to the 1-D depletion width of the device is about 2.5) is shown in FIG. 4. Additionally, fig. 4 includes isocratic lines 140 that indicate the incidence of collisions (e.g., collision ionization rate) that exist in different regions of the SiC-SJ device 4 under reverse bias conditions. It may be noted that the collision occurrence rate is indicated as being higher (e.g., larger) when the isocratic lines 140 are close to each other, and lower when there is a larger spacing between the isocratic lines 140. Therefore, because avalanche breakdown occurs at the JTE12 (e.g., termination region 10), the incidence of collisions is highest at the JTE12 and termination region 10 and decreases outward from these regions.

Looking briefly back at fig. 3, on the right side of line 122 (e.g., for a ratio of width 11 of JTE12 to the 1-D depletion width of the device of greater than or equal to about 2.75), avalanche breakdown desirably occurs at active region 6 and/or intermediate region 8, rather than in termination region 10 of SiC-SJ device 4. To aid in illustration, a cross-sectional view of a portion of an embodiment of a SiC-SJ device 4 having a JTE12 with a width 11 of 160 μm (e.g., the ratio of the width 11 of the JTE12 to the 1-D depletion width of the device is about 4) is shown in FIG. 5. For comparison, all other device parameters included in the embodiment shown in fig. 4 (e.g., minimum epi doping, thickness 65, etc.) remain unchanged in the embodiment shown in fig. 5. Additionally, fig. 5 includes isocratic lines 160 that indicate the incidence of collisions (e.g., collision ionization rate) that exist in different regions of the SiC-SJ device 4 under reverse bias conditions. It may be noted that the collision occurrence rate is indicated as being higher (e.g., larger) when the isocratic lines 160 are close to each other, and lower when there is a larger spacing between the rate lines 140. Therefore, because avalanche breakdown occurs at active region 6 and/or intermediate region 8, the collision occurrence rate is highest at SJ region 60 and well region 66 in intermediate region 8 and decreases outward from these regions. Thus, for the illustrated embodiment, the incidence of collisions within the termination region 10 is minimized and may gradually decrease as the distance from the intermediate region 8 and/or the active region 6 increases. Thus, embodiments of SiC-SJ devices 4 where the ratio of the width 11 of JTE12 to the 1-D depletion width of the device is greater than or equal to about 2.75 may achieve a maximum breakdown voltage for the SiC-SJ device 4.

As described above, the termination region 24 (e.g., 24A, 24Z) typically has a minimum epi doping concentration that is significantly lower than the doping concentration of the first conductivity type in the first set of SJ pillars 62A and/or the second set of SJ pillars 62B of the device. In some embodiments, along with the width of JTE12, the minimum epi doping concentration of termination region 24 may affect the maximum breakdown voltage of SiC-SJ device 4 and/or the location of avalanche breakdown within SiC-SJ device 4. To demonstrate this relationship, a graph 180 shown in FIG. 6 illustrates the doping concentration (cm) according to epi in the termination region 24^-3) And an example of the breakdown voltage of the SiC-SJ device 4 changed.

Curve 182 on graph 180 plots the breakdown voltage of the embodiment of the SiC-SJ device 4 of fig. 1 as a function of epi dopant concentration in the termination region 24. More specifically, curve 182 shows an example of the relationship between the breakdown voltage of a SiC-SJ device 4 having a single device JTE12 and the epi doping concentration of termination region 24. Graph 180 additionally includes a first line 184 indicating a threshold breakdown voltage that permits the device to receive a device rating of 4.5 kilovolts (kV). Further, the graph 180 includes a second line 186 representing a breakdown voltage level below which avalanche breakdown of the SiC-SJ device 4 occurs outside the termination region 10 (e.g., avalanche breakdown occurs within the active region 6 and/or the middle region 8).

Thus, as shown in graph 180, to design a SiC-SJ device 4 with a particular device rating (e.g., 4.5kV) and limit avalanche breakdown to within active region 6 and/or intermediate region 8 (e.g., to increase the maximum breakdown voltage of the device), termination region 24 may be used with less than or equal to 1.5 x 10¹⁵cm^-3(e.g., 8.0X 10)¹³cm^-3、1.0×10¹⁵cm^-3) Is referred to herein as the minimum epi doping concentration 188 of this exemplary SiC-SJ device 4. For example, for less than or equal to 1.5 × 10¹⁵cm^-3With epi doping concentration, avalanche breakdown of SiC-SJ device 4 occurs in active region 6 and/or intermediate region 8 (e.g., at SJ region 60). On the other hand, for values greater than 1.5X 10¹⁵cm^-3At the epi doping concentration, avalanche breakdown occurs at the termination region 10 (e.g., device JTE 12) and/or at the intersection of the device JTE12 and the intermediate well region 66. As a result, for values greater than 1.5X 10¹⁵cm^-3With the epi doping concentration (e.g., the minimum epi doping concentration 188 for the present embodiment), the maximum breakdown voltage of the SiC-SJ device 4 decreases as the epi doping concentration of the termination region 24 increases. Further, in some cases, the maximum breakdown voltage of the SiC-SJ device 4 may be reduced below the threshold breakdown voltage (e.g., first line 184) used to classify the voltage rating of the SiC-SJ device 4. Further, while the minimum epi doping concentration 188 described herein is associated with embodiments of the SiC-SJ device 4 having a single JTE12, it is presently recognized that the range of minimum epi doping concentration 188 of the termination region 24 may have a greater tolerance to pin the end region 24The epi doping concentration is increased for device designs with a greater number of JTEs 12. Accordingly, the embodiments described herein are intended to be illustrative and not restrictive.

To help illustrate the effect of the epi dopant concentration of the termination region 24 on the maximum breakdown voltage of the SiC-SJ device 4 and/or the location of avalanche breakdown within the SiC-SJ device 4, fig. 7 and 8 each show a cross-sectional view of a portion of a corresponding embodiment of a SiC-SJ device 4 having a termination region 24 with a corresponding different epi dopant concentration. For the portion of the embodiment of the SiC-SJ device 4 shown in FIG. 7, the epi doping concentration of the termination region 24 is 8.0 × 10¹³cm^-3. Additionally, fig. 7 includes an isocratic line 200 that indicates the incidence of collisions (e.g., collision ionization rate) that exist in different regions of the SiC-SJ device 4 under reverse bias conditions. It may be noted that the collision occurrence rate is indicated as being higher (e.g., larger) when the isocratic lines 200 are close to each other, and lower when there is a larger spacing between the isocratic lines 200. Therefore, because avalanche breakdown occurs at the active region 6 and/or the intermediate region 8 (e.g., the SJ region 60), the collision occurrence rate is highest at the active region 6 and/or the intermediate region 8 and decreases outward from these regions. Further, for the embodiment in which avalanche breakdown occurs at the active region 6 and/or the intermediate region 8, the maximum breakdown voltage of the representative SiC-SJ device 4 is about 6300 kV.

For comparison, in the portion of the embodiment of the SiC-SJ device 4 shown in FIG. 8, the epi doping concentration of the termination region 24 is 1.4 × 10¹⁵cm^-3While all other device parameters included in the embodiment shown in fig. 7 (e.g., width 11, thickness 65, etc.) remain unchanged. Additionally, fig. 8 includes an isocratic line 220 that indicates the incidence of collisions (e.g., collision ionization rate) that exist in different regions of the SiC-SJ device 4 under reverse bias conditions. It may be noted that the collision occurrence rate is indicated as being higher (e.g., larger) when the rate lines 220 are close to each other, and lower when there is a larger spacing between the rate lines 220. Since avalanche breakdown of the illustrated embodiment occurs primarily at active region 6 and/or intermediate region 8 (e.g., SJ region 60), the incidence of collisions at JTE12 is higher than that at active region 6 and/or intermediate region 8The incidence of collisions at JTE12 shown in fig. 7. As a result, the maximum breakdown voltage of the embodiment of the portion of the SiC-SJ device 4 shown in FIG. 8 is lower than the maximum breakdown voltage of the embodiment of the portion of the SiC-SJ device 4 shown in FIG. 7. That is, the maximum breakdown voltage of the embodiment of the portion of the SiC-SJ device 4 shown in FIG. 8 is about 5600 kV. Thus, it can be appreciated that the maximum breakdown voltage of the SiC-SJ device 4 decreases as the epi doping concentration of the termination region 24 increases.

Fig. 9 is a flow diagram of a process 240 for fabricating an embodiment of a SiC-SJ device 4 having one or more junction terminations, such as one or more JTEs 12, according to an embodiment described herein. Although the following of process 240 is described in a particular order representative of particular embodiments, it should be noted that process 240 may be performed in any suitable order. Further, certain steps may be repeated or skipped altogether, and in other embodiments, additional steps may be included in process 240. The following of the process 240 is described with reference to the embodiment of the SiC-SJ device 4 shown in fig. 1 and with reference to fig. 10 to 12.

The illustrated process begins by forming (process block 242) an epi layer having a minimum epi doping concentration of the first conductivity type on the base layer, as shown in fig. 10. In some embodiments, the base layer may include a semiconductor substrate layer 20. As described above, the substrate layer 20 may be made of silicon, silicon carbide (SiC), gallium nitride, diamond, aluminum nitride, boron nitride, or any other suitable wide bandgap substrate. Alternatively, the epi layer may be formed on another epi layer 14 and/or SJ layer 18, as described in more detail below.

To form the first epi layer 14A on the base layer, the epi layer 14A may be grown using Chemical Vapor Deposition (CVD). However, in some embodiments, epi layer 14A may be grown onto the base layer using any suitable technique. epi layer 14A may be formed of one or more wide bandgap semiconductor materials such as silicon carbide, gallium nitride, diamond, aluminum nitride, and/or boron nitride. Further, as discussed above, epi layer 14A may have a first conductivity type (e.g., n-type) and a low dopant concentration relative to other regions of SiC-SJ device 4 (e.g., SJ pillars 62, JTEs 12, etc.). More specifically, in some embodimentsThe first epi layer 14A may be formed without any intentional epi doping such that the first epi layer 14A is less than or equal to 1.5 x 10¹⁵cm^-3(e.g., at 8.0X 10)¹³cm^-3And 1.0X 10¹⁵cm^-3In between) is formed.

Returning to fig. 9, after forming the first epi layer 14A on the base layer, the illustrated process continues by implanting (process block 244) pillars of the first conductivity type into the first epi layer 14A. More specifically, to form SJ layer 18A, a first set of SJ pillars 62A having a first conductivity type may be implanted into active region 6 and intermediate region 8 within first epi layer 14A. Further, as shown in fig. 11, an implanted region of the first conductivity type (e.g., n-type) may extend through a thickness 65A of first epi layer 14A. Thus, in some embodiments, the region of the first conductivity type may be implanted using a suitable high energy ion implantation technique. Thus, each of the one or more regions may be implanted to a depth greater than 1 μm within epi layer 14A (e.g., to a depth of 2 μm to 15 μm). Further, each of the one or more regions may be implanted using an implant energy of greater than 500keV and/or less than 50 MeV. Thus, a high-energy implantation mask (e.g., silicon-on-insulator (SOI), polysilicon, thick silicon oxides, high-Z metals such as platinum, molybdenum, gold, etc.) may be used in conjunction with the high-energy ion implantation. Further, the mask may be formed using any suitable means. That is, for example, the mask may be deposited, grown, and/or coated directly onto portions of epi layer 14A. Further, once a mask material has been deposited on the surface of the epi layer 14A, a mask may be formed by patterning (e.g., photolithographically patterning) the mask material to expose or expose a portion of the epi layer 14A. The set of SJ columns 62A may then be selectively injected through the exposed portions of epi layer 14A.

Additionally, to form SJ layer 18A, a second set of SJ pillars 62B of a second conductivity type (e.g., p-type) are implanted (process block 246) into active region 6 and/or intermediate region 8. In some embodiments, SJ layer 18A may be formed using a self-aligned method and a set of masks, as described in co-pending U.S. provisional patent application No. 62/738,961 entitled "SUPER-JUNCTION SEMICONDUCTOR DEVICE FABRICATION," filed on 28.9.2018, the disclosure of which is incorporated herein by reference in its entirety for all purposes. For example, after a first set of SJ pillars 62A is implanted into a first portion of epi layer 14A using a first mask covering a second portion of epi layer as described above, a second mask that is self-aligned with respect to the first mask may be formed on the first portion of epi layer 14A. In some embodiments, the second mask may be formed to have different physical and/or chemical properties relative to the first mask. For example, the second mask may be formed of a different material, may undergo different chemical and/or physical changes, and/or may be formed to have different optical and/or wavelength absorption characteristics relative to the first mask. Thus, the first mask may then be removed by a suitable process (e.g., dissolution, peeling, and/or degradation) that leaves the second mask intact. By removing the first mask, a second portion of epi layer 14A is exposed, while a first portion of epi layer 14A remains masked by the second mask. Thus, a second set of SJ pillars 62B may be selectively implanted into a second portion of epi layer 14A, and then the second mask may be removed. More specifically, in some embodiments, a second set of SJ columns 62B may be injected adjacent to first set SJ columns 62A and arranged interleaved with the first set SJ columns. For embodiments in which the first and second masks are self-aligned, misalignment (e.g., overlap and/or gaps) between the first and second sets of SJ pillars 62A and 62B, which may disrupt the uniformity of the electric field and reduce the maximum blocking voltage of the SiC-SJ device 4, may be reduced or avoided.

Further, the set of SJ columns 62 may be implanted using any suitable means (e.g., high energy implant, low energy implant), as discussed below. For example, in some embodiments, the set of SJ columns 62 may be implanted using standard low energy implantation techniques. For example, the set of SJ pillars 62 may be implanted to a depth of less than or equal to 1 μm. Thus, each SJ column 62 may be implanted using an implant energy of less than 500 keV. However, in some embodiments, the set of SJ columns 62 may be implanted using a suitable high-energy ion implantation technique. Accordingly, each SJ column 62 may be implanted using an implant energy of greater than 500keV and/or less than 50 MeV. Further, the mask may be a high energy implantation mask (e.g., silicon-on-insulator (SOI), polysilicon, thick silicon oxide, high-Z metal) used in conjunction with high energy ion implantation.

A portion of process 240 (e.g., process block 242, process block 244, and/or process block 246) may be repeated one or more times in order to form the appropriate number of SJ layers 18 in the SiC-SJ device 4. Thus, after forming the SJ layer 18A, the process 240 may continue to determine (decision block 248) whether to add additional SJ layers 18B to the SiC-SJ device 4. For example, in embodiments with one or more additional SJ layers 18, a second epi layer 14B may be formed on the previously injected SJ layer 18A (process block 242) and a second SJ layer 18B may be formed (e.g., process block 244, process block 246). For example, for the embodiment of SiC-SJ device intermediate 280 shown in fig. 11, portions of process 240 (e.g., process block 242, process block 244, and/or process block 246) may also be repeated to form third SJ layer 18C.

After fabrication of one or more SJ layers 18 is complete, process 240 shown in fig. 9 continues to form (process block 250) device epi layer 14Z having a minimum epi doping concentration of the first conductivity type. As discussed with reference to the formation of one or more epi layers 14 of SJ layer 18 (process block 242), CVD may be used to grow device epi layer 14Z. Alternatively, the device epi layer 14Z may be formed on the one or more underlying SJ layers 18 using any suitable technique. The device epi layer 14Z may also be formed of one or more wide bandgap semiconductor materials such as silicon carbide, gallium nitride, diamond, aluminum nitride, and/or boron nitride. More specifically, for a SiC-SJ device 4 having a single junction termination (e.g., a single JTE 12), the device epi layer 14Z may be less than or equal to 1.5 × 10¹⁵cm^-3(e.g., at 8.0X 10)¹³cm^-3And 1.0X 10¹⁵cm^-3In between) is formed.

The process 240 shown in fig. 9 then continues to form (process block 254) certain device features within the active region 6 and/or the intermediate region 8 within the device epi layer 14Z to define the device layer 16. That is, for example, the first set of device layer pillars 64A and the second set of device layer pillars 64B may be implanted in the active region 6 and/or the intermediate region 8 within the device epi layer 14Z. More specifically, in some embodiments, each of the first and second sets of device layer pillars 64A, 64B may be implanted using a high-energy ion implantation technique, such that the first set of device layer pillars 64A contacts and electrically couples to the first set SJ pillars 62A, and such that the second set of device layer pillars 64B contacts and electrically couples to the second set SJ pillars 62B, as shown in fig. 11. Further, in some embodiments, first set of device layer pillars 64A and second set of device layer pillars 64B may be implanted using a self-aligned method and mask set, as described above with reference to the set of SJ pillars 62. Further, as described below, the doping concentration of at least one of the first set of device layer pillars 64A may be less than the doping concentration of the second set of device layer pillars 64B. Further, well regions 40, source regions 44, intermediate well regions 66, etc. may be formed (e.g., implanted) in active region 6 and/or intermediate region 8 within device epi layer 14Z to define device layer 16, as shown in fig. 12. Thus, while process block 252 is described herein as a single step, it is understood that forming device features (e.g., first set of device layer pillars 64A, second set of device layer pillars 64B, well region 40, intermediate well region 66, source regions 44, etc.) may include multiple steps, such as a separate implant step for each respective feature and/or multiple implant steps for each feature.

Further, process 240 shown in fig. 9 involves implanting (process block 254) a floating region of the second conductivity type into termination region 24Z of epi layer 14Z of the device to define a junction termination, such as JTE12, in device layer 16, as shown in fig. 12. The float-out region 68 may be implanted according to any suitable means (e.g., high energy implantation, low energy implantation). Accordingly, in some embodiments, the floating-out regions 68 may be selectively implanted through portions of the termination region 24Z exposed by a mask formed over the termination region 24Z, which may then be removed. Further, in some embodiments, the floating regions 68 may be implanted to a depth of less than or equal to 1 μm. Accordingly, an implantation energy of less than 500keV can be used to implant each of the float-out regions 68. However, in some embodiments, the float-out region 68 may be implanted in accordance with a suitable high-energy ion implantation technique. Thus, for such embodiments, each of the floating regions 68 may be implanted to a depth greater than about 2 μm and/or less than about 15 μm within the epi layer 14Z of the device. Further, each of the float-out regions 68 may generally be implanted using an implantation energy of greater than 500keV and/or less than 50 MeV. Subsequently, other processing steps may be performed to form other features of the SiC-SJ device 4 (e.g., gate electrode 48, dielectric layer 46, source contact 54, drain contact 50, etc.) to form a functional power conversion device in accordance with the present disclosure.

In some embodiments, different implant operations may be used to implant features of the second conductivity type, such as well regions 40 and floating regions 68, in device epi layer 14Z. Alternatively, in some embodiments, the floating regions 68 may be implanted simultaneously with other features of the device epi layer 14Z (e.g., well regions 40, intermediate well regions 66). For example, during the same ion implantation step used to implant these features having the second conductivity type, the floating regions 68 of JTE12 may be implanted with the same dopant type (e.g., P-type or N-type dopants) and/or using the same material (e.g., Al, B, N, P, etc.), which may reduce fabrication time and cost.

As described above, in some embodiments, the doping of the SJ pillars 62A of the first conductivity type (e.g., n-type) closest to the termination region 10 may be modified relative to the other SJ pillars 62A to further adjust the BV (breakdown voltage) of the device and to control the portion of the device that undergoes breakdown when the BV is reached (e.g., active region 6 or termination region 10). To illustrate this, fig. 13 is a cross-sectional view of a portion of an embodiment of a SiC-SJ device 300 having termination region 10 that includes JTE12, in accordance with aspects of the present technique. For the illustrated embodiment of the SiC-SJ device 300, the first conductivity type is n-type, which corresponds to the conductivity type of the SJ pillars 62A, the smallest epi-doped epi layer 14 in the termination region 10, and the SiC substrate 20. Additionally, for the embodiment shown, the second conductivity type is p-type, which corresponds to the conductivity type of SJ pillars 62B, intermediate well regions 66, and JTE 12.

The illustrated SiC-SJ device 300 is modeled to determine how the doping variation of the last SJ pillars 64A of the first conductivity type closest to the termination region 10 (hereinafter referred to as modified SJ pillars 302) affects the breakdown characteristics of the device 300. In view of this, fig. 14 is an enlarged view of an embodiment of the SiC-SJ device 300 of fig. 13. As shown, the modified SJ pillars 302 include modified portions 304 having a lower n-type doping concentration relative to the remainder of the pillars 302 and relative to other n-type SJ pillars 62A in the active region 6 of the device 300 (not shown). Modified portions 304 of SJ pillars 302 may be described as having a depth 306 that extends to one or more epi layers 14 below intermediate well region 66. For example, in the illustrated embodiment, the modified portion 304 has a depth 306 of about 12 μm. As discussed below, by controlling both the depth 306 and the doping concentration within the modified portion 304 of the modified SJ pillars 302, the breakdown properties of the device 300 can be controlled. It is to be understood that while fig. 13 and 14 show only the middle region 8 and the terminal regions 10 of one portion of the device 300, the n-type SJ pillars 64A in the other portion of the device 300 closest to the terminal regions 10 may also be modified SJ pillars 302, as discussed herein.

For the model discussed below, the embodiment of the SiC-SJ device 300 has a 1 × 10¹⁵cm^-3And a combined or total epi layer thickness of 40 μm. The intermediate well region 66 has a depth of 1 μm and a 3 × 10 depth¹⁷cm^-3The doping concentration of (c). JTE12 has a 3X 10¹³cm^-2And a width of 160 μm (e.g., slightly greater than four times the 1-D depletion width). The p-type SJ pillars 62B of device 300 have a width 73 of 5 μm and 1.7 × 10¹⁶cm^-3The doping concentration of (c). The n-type SJ pillars 62A had a width 73 of 5 μm and also had 1.7X 10 in addition to the modified portions 304 of the modified SJ pillars 302¹⁶cm^-3The doping concentration of (c). Additionally, it may be noted that for these examples, device layer pillars 64A and 64B are generally depicted as part of SJ pillars 62A and 62B, respectively.

Fig. 15 is a graph 310 illustrating the absolute net doping concentration as a function of distance (μm) along lines a and B for the embodiment of the SiC-SJ device 300 shown in fig. 14. More specifically, curve 312 corresponds to line a, and curve 314 corresponds to line B. As shown, the net doping concentrations within the unmodified portion of the modified SJ pillars 302 and within the p-type SJ pillars 64B are approximately the same when moving along line B until a significantly lower minimum epi doping concentration is reached in the termination region 10. When moving along line a, the net doping concentration within the modified portions 304 of the modified SJ pillars 302 is significantly less (e.g., about 40% less) than the net doping concentration of the p-type SJ pillars 64B until a significantly lower minimum epi concentration is again reached in the termination region 10.

Fig. 16 is a graph 320 illustrating the breakdown voltage as a function of the depth 306 of the modified portion 304 of the modified SJ column 302 for an embodiment of a SiC-SJ device. In addition to the model parameters discussed above, the doping concentration of the modified portion 304 is 1.02 x 10 for the embodiment represented in graph 320¹⁶cm^-3. Graph 320 includes a line 322 representing the nominal BV of SiC-SJ device 300, which for these examples is 6092V. Graph 320 also includes a curve 324 corresponding to the data of table 1, which represents the breakdown voltage of an embodiment of the Si-SJ device 300 having modified portions 304 of different depths 306 of the modified SJ pillars 302.

Table 1 data corresponding to curve 324 of fig. 16.

As shown in graph 320, for the modeled embodiment of SiC-SJ device 300, the breakdown voltage approaches the due breakdown voltage of the device when the modified portions 304 of the modified SJ pillars 302 have a depth 306 of about 11 μm or greater. In certain embodiments, this depth 306 may correspond to about 30% or more (e.g., about 1/3) of the total depth of the modified SJ column 302. Accordingly, embodiments of the SiC-SJ device 300 may be fabricated based on the modeling parameters described above, and the depth 306 of the modified portion 304 may be about 7.1 μm, which results in a breakdown voltage of about 5483V or about 90% of the breakdown voltage that the device should have. As also shown in graph 320, for the modeled SiC-SJ device 300, when modified portions 304 of modified SJ pillars 302 have a depth 306 of less than about 12 μm, then breakdown occurs at the top of n-type SJ pillars 62A in active region 6 and middle region 8 of device 300, and when modified portions 304 have a depth 306 of greater than about 12 μm, then breakdown occurs at JTE12 in termination region 10 of device 300.

It is also presently recognized that in certain embodiments, it may be advantageous for the depth 306 of the modified portion 304 of the modified SJ pillars 302 to correspond to the thickness of the epi layer 14Z of the device. For example, referring briefly back to fig. 13, in an embodiment where the device epi layer 14Z has a thickness 65Z of about 14 μm and the intermediate well regions 66 occupy about the top 1 μm of the device epi layer 14Z, the depth 306 of the modified portions 304 of the modified SJ pillars 302 would be about 13 μm. In other words, in some embodiments, the modified portion 304 may be confined to the device layer pillar 64B that is closest to the termination region 10 of the device in the middle region 8 of the device epi layer 14Z. For such an embodiment, the modified portion 304 of the modified SJ pillars 302 is completely contained within the device epi layer 14Z, and only that portion of the modified SJ pillars 302 in the device epi layer 14Z is less doped relative to the rest of the modified SJ pillars 302 or the other n-type SJ pillars 62A of the active region 6, which simplifies the fabrication of the device 300. In certain embodiments, the thickness 65Z of the device epi layer 14Z may be between 2 μm and 15 μm, such as between 2 μm and 10 μm or between 10 μm and 15 μm.

It will be appreciated that in general, it is desirable that breakdown occurs uniformly over a relatively large device area/volume. Thus, based on the data presented in fig. 16, it is presently recognized that a device designer may use the depth 306 of the modified portion 304 of the modified SJ pillars 302 as a way to control where breakdown occurs within the device 300. Fig. 17A and 17B are graphs showing collision incidence rates of the embodiment of the SiC-SJ device 300 shown in fig. 16. More specifically, fig. 17A is a graph 330 illustrating the incidence of collisions for an embodiment of a SiC-SJ device 300 having a modified portion 304 of modified SJ pillars 302 with a depth 306 of 13.5 μm, and, therefore, breakdown occurs at JTE12 in termination region 10. In contrast, fig. 17B is a graph 340 illustrating the incidence of collisions for a SiC-SJ device 300 with a modified portion 304 of modified SJ pillars 302 having a depth 306 of 12 μm, and therefore, breakdown of the tops of n-type SJ pillars 62A in active region 6 and middle region 8 of the device.

In addition to the depth 306 of the modified SJ pillars 302, it is presently recognized that the doping of the modified portions 304 of the modified SJ pillars 302 also affects the breakdown characteristics of the SiC-SJ device 300. Fig. 18 is a graph 350 illustrating the breakdown voltage as a function of doping concentration in the modified portion 304 of the modified SJ column 302. The data of graph 350 was modeled based on the model parameters described above, except that the depth 306 of the modified portion 304 was maintained at a constant value of 13.5 μm. Graph 350 also includes a curve 352 corresponding to the data of table 2, which represents the breakdown voltage of an embodiment of SiC-SJ device 300 having different dopant concentrations in modified portions 304 of modified SJ pillars 302.

Table 2. data corresponding to curve 352 of fig. 18.

As shown in graph 350 of fig. 18, the doping concentration in the modified portion 304 for the modified SJ column 302 is greater than about 1.05 x 10¹⁶cm^-3The embodiment of SiC-SJ device 300, breakdown occurs at the top of n-type SJ pillars 34A in active region 6 and middle region 8 of the device. In contrast, the doping concentration in the modified portions 304 for the modified SJ columns 302 is less than or equal to about 1.05 x 10¹⁶cm^-3The breakdown occurs at JTE12 in the termination region 10 of the device. Additionally, the doping concentration in the modified portions 304 of the modified SJ columns 302 is less than or equal to about 1.05 x 10¹⁶cm^-3The embodiment of (a) exhibits a breakdown voltage equal to that of device 300. Thus, in one example, embodiments of the SiC-SJ device 300 can be fabricated when the doping concentration in the modified portions 304 of the modified SJ pillars 302 is about 1.26 x 10¹⁶cm^-3With a due breakdown voltage of about 90% of the SiC-SJ device 300.

The technical effect of the scheme comprises the effective terminal of the SJ device. Additionally, the disclosed termination design consumes a relatively small portion of die area and is relatively low in manufacturing cost relative to common junction termination designs. For example, the disclosed junction termination designs may be designed to have a width such that the ratio of the termination width to the one-dimensional (1-D) depletion width is minimized (e.g., less than 5, such as between 2.75 and 5, between 2.75 and 4, between 2.75 and 3), which increases the die area of the device available for the active area while also providing a breakdown voltage that is close to or equal to the breakdown voltage that the device should have. Additionally, some SJ pillars near the termination region (e.g., device pillars) may include an upper portion having a reduced doping concentration relative to other SJ pillars of the device, which may increase the breakdown voltage of the device 300. In addition, the depth and doping concentration of this modified portion of the SJ pillars can be varied to tune the breakdown voltage of the SJ device and where breakdown occurs.

This written description uses examples to disclose the invention and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those of ordinary skill in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

The technology presented and claimed herein is cited and applied to physical objects and embodiments of a matter of practical nature which clearly improve the art and are therefore not abstract, intangible or purely theoretical. Further, if any claim appended to the end of this specification contains one or more elements designated as "means for performing [ function … …" or "step for performing [ function … …"), it is intended that such elements be construed in accordance with 35 u.s.c.112 (f). However, for any claim that contains elements specified in any other way, such elements should not be construed according to 35 u.s.c.112 (f).