阅读说明：本技术 具有电场钳位层的匀场器件及其制造方法和应用 (Shimming device with electric field clamping layer and manufacturing method and application thereof ) 是由 章文通 吴旸 张科 何乃龙 乔明 李肇基 张波 于 2021-08-19 设计创作，主要内容包括：本发明提供一种具有电场钳位层的匀场器件及其制造方法和应用,第一介质氧化层和浮空场板多晶硅电极构成纵向浮空场板,分布在整个第二导电类型漂移区中,形成纵向浮空等势场板阵列；由于硅的介电系数是二氧化硅的三倍,在相同漂移区长度下,介质层能够取得更大的电场,提高击穿电压。电场钳位层Ptop的引入带来了双电荷自平衡,MIS电极高电位辅助耗尽P型杂质,低电位辅助耗尽N型杂质,同时P型杂质和N型杂质之间可以相互耗尽,因此可以大大增大漂移区浓度,从而降低比导通电阻。同时,电场钳位层Ptop保证了耗尽的连续性,具有钳位表面电场的作用,使得在很宽的漂移区浓度内保持高的击穿电压,具有高容差性。(The invention provides a shimming device with an electric field clamping layer and a manufacturing method and application thereof.A first dielectric oxidation layer and a floating field plate polycrystalline silicon electrode form a longitudinal floating field plate which is distributed in a whole second conductive type drift region to form a longitudinal floating equipotential field plate array; because the dielectric coefficient of silicon is three times of that of silicon dioxide, under the same drift region length, the dielectric layer can obtain a larger electric field, and the breakdown voltage is improved. The introduction of the electric field clamping layer Ptop brings double-charge self-balance, the MIS electrode is high in potential to assist in depleting the P-type impurities, the low in potential to assist in depleting the N-type impurities, and meanwhile, the P-type impurities and the N-type impurities can be mutually depleted, so that the concentration of a drift region can be greatly increased, and the specific on-resistance is reduced. Meanwhile, the electric field clamping layer Ptop ensures the continuity of depletion, has the function of clamping a surface electric field, keeps high breakdown voltage in a very wide drift region concentration and has high tolerance.)

1. A shimming device having an electric field clamping layer, comprising:

the transistor comprises a first conduction type semiconductor substrate (11), a first conduction type well region (12), a first conduction type source end heavily doped region (13), a first conduction type electric field clamping layer (14), a second conduction type drift region (21), a second conduction type well region (22), a second conduction type source end heavily doped region (23), a second conduction type drain end heavily doped region (24), a first medium oxidation layer (31), a second medium oxidation layer (32), a third medium oxidation layer (33), a polycrystalline silicon electrode (41) and a control gate polycrystalline silicon electrode (42);

the second conduction type drift region (21) is positioned above the first conduction type semiconductor substrate (11), the first conduction type source end heavily doped region (13) and the second conduction type source end heavily doped region (23) are positioned in the first conduction type well region (12), the second conduction type well region (22) is positioned on the right side of the inside of the second conduction type drift region (21), the first conduction type well region (12) is positioned on the left side of the second conduction type drift region (21), and the second conduction type drain end heavily doped region (24) is positioned in the first conduction type well region (22); one part of the first conduction type electric field clamping layer (14) is positioned above the inner part of the second conduction type drift region (21) and below the third dielectric oxide layer (33), and the other part of the electric field clamping layer (14) is positioned in the first conduction type well region (12); the second dielectric oxide layer (32) is positioned above the first conductive type well region (12), the left end of the second dielectric oxide layer is contacted with the second conductive type source end heavily doped region (23), and the right end of the second dielectric oxide layer is contacted with the second conductive type drift region (21); the third dielectric oxide layer (33) is positioned on the upper surface of the second conduction type drift region (21) between the second dielectric oxide layer (32) and the second conduction type drain terminal heavily doped region (24); the control gate polysilicon electrode (42) covers the upper surface of the second dielectric oxide layer (32) and partially extends to the upper surface of the third dielectric oxide layer (33);

the first dielectric oxide layer (31) and the floating field plate polycrystalline silicon electrode (41) form a longitudinal extending floating field plate, and the number of the longitudinal floating field plates is 1 to a plurality; the longitudinal floating field plates are periodically distributed in the whole second conduction type drift region (21) to form a voltage-resistant layer with a plurality of equipotential floating grooves; the longitudinal distance and the transverse distance of adjacent longitudinal floating field plates distributed in the whole second conduction type drift region (21) are equal, the transverse direction is a source-drain direction, and the longitudinal direction is perpendicular to the source-drain direction.

2. The shimming device with electric field clamping layer according to claim 1, characterized in that: the adjacent longitudinal floating field plates in the source and drain direction are arranged in a staggered mode.

3. The shimming device with electric field clamping layer according to claim 1, characterized in that: the body of the second conduction type drift region (21) is provided with 1 or more first conduction type electric field clamping layers (14).

4. The shimming device with electric field clamping layer according to claim 1, characterized in that: a first conductivity type electric field clamp layer (14) and a second conductivity type buried layer (25) are provided in the body of the second conductivity type drift region (21).

5. The shimming device with electric field clamping layer according to claim 1, characterized in that: the depth of the second conduction type drift region (21) is greater than that of the longitudinal floating field plate, and a section of space is reserved between the bottom end of the longitudinal floating field plate and the first conduction type semiconductor substrate (11) to form a bottom conduction path;

or the longitudinal floating field plate of the drift region is inserted inside the first conductivity type semiconductor substrate (11).

6. The shimming device with electric field clamping layer according to claim 1, characterized in that: a buried layer (25) of the second conductivity type is formed through the slot implant at the bottom of the vertical floating field plate.

7. The shimming device with electric field clamping layer according to claim 1, characterized in that: the cross section of the longitudinal floating field plate is rectangular, circular, elliptical or hexagonal;

and/or the first conductivity type electric field clamping layer (14) is a plurality of separated strip-shaped, or circular, or oval strip-shaped in the source-drain direction.

8. A method of manufacturing a shim device having a field clamping layer as claimed in claim 1, comprising the steps of:

step 1: selecting a first conductivity type semiconductor substrate (11);

step 2: injecting a push junction above the first conductive type semiconductor substrate (11) to obtain a second conductive type drift region (21);

and step 3: determining the depth and the distance between the grooves, and forming the grooves by photoetching and etching;

and 4, step 4: forming a first dielectric oxide layer on the groove wall, depositing polycrystal and etching to a silicon plane;

and 5: forming a second conductivity type well region (22) by ion-implanting second conductivity type impurities and junction-pushing;

step 6: forming a second dielectric oxide layer (32) by thermal oxidation, and forming a third dielectric oxide layer (33) by deposition and etching;

and 7: implanting first conductive type impurities through ions and pushing the impurities to form a first conductive type well region (12), and implanting the ions to penetrate through a second medium oxide layer to form a first conductive type electric field clamping layer (14), wherein the first conductive type electric field clamping layer and the first conductive type electric field clamping layer adopt the same edition;

and 8: depositing and etching polysilicon to form a control gate polysilicon electrode (42);

and step 9: and (3) forming a first conduction type source end heavily doped region (13), a second conduction type source end heavily doped region (23) and a second conduction type drain end heavily doped region (24) by injection activation.

9. The method of manufacturing a shim device with an electric field clamping layer according to claim 8, wherein: the second conductivity type drift region (21) of step 2 is obtained by epitaxy.

10. The use of the method of claim 8 for manufacturing a shim device with an electric field clamping layer for the preparation of SiC, GaN wide bandgap semiconductors.

Technical Field

The invention belongs to the field of power semiconductors, and mainly provides a shimming device with an electric field clamping layer, and a manufacturing method and application thereof.

Background

The power semiconductor device has the characteristics of high input impedance, high switching speed, low loss, wide safe working area and the like, and is widely applied to computers, peripheral equipment, consumer electronics, network communication, electronic special equipment, automobile electronics, instruments and meters, LED display screens, electronic lighting and other aspects. The source electrode, the grid electrode and the drain electrode of the transverse device are on the same surface, so that the transverse device is easy to integrate with other devices and circuits through internal connection, and is widely applied to power integrated circuits. In the design of the lateral device, the device is required to have high breakdown voltage and low specific on-resistance. A higher breakdown voltage requires a longer drift region length and a lower drift region doping concentration for the device, but this also results in an increased specific on-resistance of the device. The proposed resurfr device alleviates this contradiction, but the resurfr device can achieve high withstand voltage depending on strict charge balance.

In order to alleviate the contradiction between the breakdown voltage and the specific on-resistance, researchers have proposed a device with a longitudinal floating field plate and a manufacturing method thereof (CN 201910819933.6). Meanwhile, when the device is in an on state, an accumulation layer can be formed on the surface of the floating field plate, the specific on-resistance is reduced, and the saturation current is improved. However, since the depletion continuity is not easily maintained between the trenches, when the concentration of the drift region is increased, the drain end electric field is easily decreased, and the breakdown voltage is easily lowered. The invention provides a shimming device of an electric field clamping layer and a manufacturing method thereof, which solve the problem of voltage resistance reduction caused by discontinuous depletion of the device, have wider tolerance on breakdown voltage within a wide concentration range of a drift region, and have simpler manufacturing method.

Disclosure of Invention

The invention introduces a longitudinal equipotential floating field plate array connected with a dielectric layer in a drift region, and provides a new structure of a low-resistance device with equipotential floating grooves, wherein the structure enables the device to obtain a larger average electric field, improves the withstand voltage and reduces the specific conductance.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a shimming device having an electric field clamping layer, comprising:

the semiconductor device comprises a first conduction type semiconductor substrate 11, a first conduction type well region 12, a first conduction type source end heavily doped region 13, a first conduction type electric field clamping layer 14, a second conduction type drift region 21, a second conduction type well region 22, a second conduction type source end heavily doped region 23, a second conduction type drain end heavily doped region 24, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a polycrystalline silicon electrode 41 and a control gate polycrystalline silicon electrode 42;

the second conductive type drift region 21 is located above the first conductive type semiconductor substrate 11, the first conductive type source end heavily doped region 13 and the second conductive type source end heavily doped region 23 are located in the first conductive type well region 12, the second conductive type well region 22 is located on the right side inside the second conductive type drift region 21, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type drain end heavily doped region 24 is located in the first conductive type well region 22; a part of the first conductivity type electric field clamp layer 14 is located above the inside of the second conductivity type drift region 21 and below the third dielectric oxide layer 33, and another part of the electric field clamp layer 14 is located in the first conductivity type well region 12; the second dielectric oxide layer 32 is located above the first conductive type well region 12, and the left end of the second dielectric oxide layer is in contact with the second conductive type source heavily doped region 23, and the right end of the second dielectric oxide layer is in contact with the second conductive type drift region 21; the third dielectric oxide layer 33 is positioned on the upper surface of the second conductive type drift region 21 between the second dielectric oxide layer 32 and the second conductive type drain heavily doped region 24; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;

the first dielectric oxide layer 31 and the floating field plate polycrystalline silicon electrode 41 form a longitudinally extending longitudinal floating field plate, and the number of the longitudinal floating field plates is 1 to a plurality; the longitudinal floating field plates are periodically distributed in the whole second conductive type drift region 21 to form a voltage-resistant layer with a plurality of equipotential floating grooves; the longitudinal distance and the transverse distance of adjacent longitudinal floating field plates distributed in the whole second conductivity type drift region 21 are equal, the transverse direction is the source-drain direction, and the longitudinal direction is perpendicular to the source-drain direction.

An electric field clamping layer (a Ptop layer) is introduced to ensure the continuity of depletion, so that the surface electric field of the Ptop layer is at a higher level, and the withstand voltage is kept unchanged in a wide concentration range of a drift region.

As a preferred mode, the adjacent longitudinal floating field plates in the source and drain direction are arranged in a staggered mode.

Preferably, 1 or more first conductivity type electric field clamp layers 14 are provided in the body of the second conductivity type drift region 21.

Preferably, the first conductivity type electric field clamp layer 14 and the second conductivity type buried layer 25 are provided in the body of the second conductivity type drift region 21.

Preferably, the depth of the second conductivity type drift region 21 is greater than that of the longitudinal floating field plate, and a gap is left between the bottom end of the longitudinal floating field plate and the first conductivity type semiconductor substrate 11 to form a bottom conductive path; or the longitudinal floating field plate of the drift region is inserted inside the first conductivity type semiconductor substrate 11.

Preferably, a buried layer 25 of the second conductivity type is formed through a trench implant at the bottom of the vertical floating field plate. FIG. 7

Preferably, the cross section of the longitudinal floating field plate is rectangular, circular, elliptical or hexagonal; and/or first conductivity type electric field clamp layer 14 has a plurality of separated stripe shapes, or circular shapes, or elliptical stripe shapes in the source-drain direction. A high concentration of the second conductivity type drift region 21 at the surface can be flown out to improve the performance.

The invention also provides a manufacturing method of the shimming device with the electric field clamping layer, which comprises the following steps:

step 1: selecting a first conductivity type semiconductor substrate 11;

step 2: injecting a push junction above the first conductivity type semiconductor substrate 11 to obtain a second conductivity type drift region 21;

and step 3: determining the depth and the distance between the grooves, and forming the grooves by photoetching and etching;

and 4, step 4: forming a first dielectric oxide layer on the groove wall, depositing polycrystal and etching to a silicon plane;

and 5: forming a second conductive type well region 22 by ion-implanting second conductive type impurities and junction-pushing;

step 6: forming a second dielectric oxide layer 32 by thermal oxidation, and depositing and etching to form a third dielectric oxide layer 33;

and 7: forming a first conductive type well region 12 by ion implantation of first conductive type impurities and junction pushing, and forming a first conductive type electric field clamping layer 14 by ion implantation through a second dielectric oxide layer, wherein the first conductive type electric field clamping layer and the first conductive type electric field clamping layer adopt the same edition;

and 8: depositing and etching polysilicon to form a control gate polysilicon electrode 42;

and step 9: the implantation activation forms a first conductive type source end heavily doped region 13, a second conductive type source end heavily doped region 23 and a second conductive type drain end heavily doped region 24.

Preferably, the second conductivity type drift region 21 of step 2 is obtained by epitaxy.

Preferably, the first-conductivity-type well region 12 formed in step 7 and the first-conductivity-type electric field clamp layer 14 share one plate, and the first-conductivity-type well region does not affect the concentration of the first-conductivity-type electric field clamp layer 14 due to the blocking of the second dielectric oxide layer 32.

Preferably, the second conductivity type drift region 21 is obtained by junction pushing, so that the dose can be higher, and the isolation effect can be better formed.

Preferably, the depth of the trench in step 3 is determined by the thickness of the drift region to ensure full depletion; the groove distance does not need to ensure the mutual contact of the groove wall oxide layers due to the existence of the electric field clamping layer.

The invention also provides application of the manufacturing method of the shimming device with the electric field clamping layer in preparation of SiC and GaN wide bandgap semiconductors.

The invention has the beneficial effects that: a longitudinal floating field plate structure formed by connecting dielectric layers consisting of a first dielectric oxide layer 31 and a floating field plate polycrystalline silicon electrode 41 is introduced into a second conductive type drift region 21 of the device, and as the dielectric coefficient of silicon is three times that of silicon dioxide, the dielectric layers can obtain a larger electric field under the same drift region length, so that the breakdown voltage is improved. The introduction of the first conduction type electric field clamping layer brings double-charge self-balance, the MIS electrode is high in potential to assist in depleting the P-type impurities, the low in potential to assist in depleting the N-type impurities, and meanwhile, the P-type impurities and the N-type impurities can be mutually depleted, so that the concentration of a drift region can be greatly increased, and the specific on-resistance is reduced. Meanwhile, the first conduction type electric field clamping layer ensures the continuity of depletion and has the function of clamping a surface electric field, so that high breakdown voltage is kept in a very wide drift region concentration, and high tolerance is realized. The same plate is adopted in the process as the first conductive type well region, the blocking effect of the field oxide layer is utilized, and high-energy injection is performed without additional plates.

Drawings

Fig. 1(a) is a front view of the structure of a shimming device with an electric field clamping layer in embodiment 1;

FIG. 1(b) is a sectional view of example 1 BB'.

FIG. 1(c) is an AA' sectional view of example 1.

Fig. 2 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 2;

fig. 3 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 3;

fig. 4 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 4;

FIG. 5 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 5;

fig. 6 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 6;

fig. 7 is a schematic structural diagram of a shimming device with an electric field clamping layer in embodiment 7;

FIGS. 8(a) -8 (l) are schematic process flow diagrams of the device of example 1;

FIG. 9 is a comparison of surface electric fields of devices with and without electric field clamping layers;

11 is a first conductivity type semiconductor substrate, 12 is a first conductivity type well region, 13 is a first conductivity type source heavily doped region, 14 is a first conductivity type electric field clamping layer, 21 is a second conductivity type drift region, 22 is a second conductivity type well region, 23 is a second conductivity type source heavily doped region, 24 is a second conductivity type drain heavily doped region, 25 is a second conductivity type buried layer, 31 is a first dielectric oxide layer, 32 is a second dielectric oxide layer, 33 is a third dielectric oxide layer, 41 is a polysilicon electrode, 42 is a control gate polysilicon electrode, and 51 is a surface metal of a longitudinal field plate.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

FIG. 9 shows a comparison of the surface electric field of a device with and without an electric field clamping layer, D-HOF, where it can be seen that the surface single field of D-HOF remains substantially constant as the concentration of the drift region increases; and due to the fact that the surface field of the S-HOF does not have the electric field clamping layer, the electric field of the source end tends to be reduced along with the increase of the concentration of the drift region, and the breakdown voltage is reduced.

Example 1

The shimming device with the electric field clamping layer according to embodiment 1, as shown in fig. 1(a) -1 (c), specifically includes:

the semiconductor device comprises a first conduction type semiconductor substrate 11, a first conduction type well region 12, a first conduction type source end heavily doped region 13, a first conduction type electric field clamping layer 14, a second conduction type drift region 21, a second conduction type well region 22, a second conduction type source end heavily doped region 23, a second conduction type drain end heavily doped region 24, a first dielectric oxide layer 31, a second dielectric oxide layer 32, a third dielectric oxide layer 33, a polycrystalline silicon electrode 41 and a control gate polycrystalline silicon electrode 42;

the second conductive type drift region 21 is located above the first conductive type semiconductor substrate 11, the first conductive type source end heavily doped region 13 and the second conductive type source end heavily doped region 23 are located in the first conductive type well region 12, the second conductive type well region 22 is located on the right side inside the second conductive type drift region 21, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type drain end heavily doped region 24 is located in the first conductive type well region 22; a part of the first conductivity type electric field clamp layer 14 is located above the inside of the second conductivity type drift region 21 and below the third dielectric oxide layer 33, and another part of the electric field clamp layer 14 is located in the first conductivity type well region 12; the second dielectric oxide layer 32 is located above the first conductive type well region 12, and the left end of the second dielectric oxide layer is in contact with the second conductive type source heavily doped region 23, and the right end of the second dielectric oxide layer is in contact with the second conductive type drift region 21; the third dielectric oxide layer 33 is positioned on the upper surface of the second conductive type drift region 21 between the second dielectric oxide layer 32 and the second conductive type drain heavily doped region 24; the control gate polysilicon electrode 42 covers the upper surface of the second dielectric oxide layer 32 and partially extends to the upper surface of the third dielectric oxide layer 33;

the first dielectric oxide layer 31 and the floating field plate polycrystalline silicon electrode 41 form a longitudinally extending longitudinal floating field plate, and the number of the longitudinal floating field plates is 1 to a plurality; the longitudinal floating field plates are periodically distributed in the whole second conductive type drift region 21 to form a voltage-resistant layer with a plurality of equipotential floating grooves; the longitudinal distance and the transverse distance of adjacent longitudinal floating field plates distributed in the whole second conductivity type drift region 21 are equal, the transverse direction is the source-drain direction, and the longitudinal direction is perpendicular to the source-drain direction.

An electric field clamping layer (a Ptop layer) is introduced to ensure the continuity of depletion, so that the surface electric field of the Ptop layer is at a higher level, and the withstand voltage is kept unchanged in a wide concentration range of a drift region.

The adjacent longitudinal floating field plates in the source and drain direction are arranged in a staggered mode.

In this embodiment, the depth of the second conductivity type semiconductor 21 is greater than that of the vertical floating field plate, and a gap is left between the bottom end of the vertical floating field plate and the first conductivity type semiconductor substrate 11 to form a bottom conductive path.

The number of the longitudinal floating field plates can be 1 to more.

The cross section of the longitudinal floating field plate is rectangular, circular, elliptical or hexagonal;

the basic working principle is as follows: taking the first conductive type semiconductor material as P-type, under the condition of no gate voltage, the PN junction formed by the second conductive type drift region 21 and the first conductive type well region 12 is under the reverse voltage V_dDepletion is started by the action, and the PN junction formed by the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21 also starts depletion at the drain voltage. Meanwhile, the floating electrode in the longitudinal field plate has an auxiliary depletion effect on the drift region and the Ptop, so that the surface electric field is uniformly distributed, most of the breakdown voltage is borne by the dielectric layer, and the dielectric coefficient of silicon dioxide is smaller than that of silicon, so that the withstand voltage of the device is greatly improved, and the breakdown voltage of the device is improved. When the gate bias voltage V_gWhen the threshold voltage is higher than the threshold voltage, inversion layer electrons appear on the surface of the first conductivity type well region 12 close to the second dielectric oxide layer 32, so that the source and drain are conducted. Because the MIS electrode consumes the P-type impurity with high potential assistance and the N-type impurity with low potential assistance, double charge self-balancing is introduced, the device can improve the injection dosage of a drift region while ensuring high withstand voltage, thereby reducing the specific on-resistance. In conclusion, the shimming device with the electric field clamping layer has higher breakdown voltage and lower specific on-resistance than the conventional shimming device.

As shown in fig. 8, a schematic process flow diagram of embodiment 1 of the present invention specifically includes the following steps:

step 1: selecting a first conductivity type semiconductor substrate 11;

step 2: injecting a push junction above the first conductive type substrate 11 to obtain a second conductive type drift region 21;

and step 3: determining the depth and the space of the grooves, and forming deep grooves by photoetching and etching;

and 4, step 4: forming a first dielectric oxide layer on the groove wall, depositing polycrystal and etching to a silicon plane;

and 5: implanting second conductivity type impurities by high energy ions and forming a second conductivity type well region 22;

step 6: forming a second dielectric oxide layer 32 by thermal oxidation, and depositing and etching to form a third dielectric oxide layer 33;

and 7: implanting first conductive type impurities through ions and pushing the first conductive type impurities to form a first conductive type well region 12, and implanting high-energy ions through a second dielectric oxide layer to form an electric field clamping layer 14, wherein the high-energy ions and the electric field clamping layer adopt the same layout;

and 8: depositing and etching polysilicon to form a control gate polysilicon electrode 42;

and step 9: injecting and activating heavy doping to form a first conductive type source end heavy doping region 13, a second conductive type source end heavy doping region 23 and a second conductive type drain end heavy doping region 24;

it should be noted that:

the first conductive type well region 12 formed in step 7 and the first conductive type electric field clamping layer 14 share one plate, and the first conductive type well region does not affect the concentration of the first conductive type electric field clamping layer 14 due to the blocking of the second oxide layer dielectric 32.

The second conductive type drift region 21 is obtained by junction pushing, so that the dosage can be higher, and the isolation effect can be better formed.

In the step 3, the deep groove is determined by the thickness of the drift region so as to ensure full depletion; the groove distance does not need to ensure that the groove wall oxide layers are mutually contacted due to the existence of the charge clamping layer.

The manufacturing method of the shimming device with the electric field clamping layer is completely applicable to the preparation of SiC and GaN wide bandgap semiconductors, and the process is completely compatible.

Example 2

As shown in fig. 2, a schematic diagram of the shimming device with the electric field clamping layer in embodiment 2 is shown, and this example is different from the structure in embodiment 1 in that the first conductivity type electric field clamping layer 14 is in a body, and an additional electric field peak is introduced in the body, so that the doping concentration of the second conductivity type drift region 21 can be further increased, and the specific on-resistance can be reduced, and the process is basically the same as that in embodiment 1, and only the implantation energy of the electric field clamping layer needs to be changed. The working principle is basically the same as that of embodiment 1.

Example 3

As shown in fig. 3, a schematic diagram of the shimming device with electric field clamping layers in embodiment 3 is shown, and this example is different from the structure in embodiment 1 in that a plurality of first conductivity type electric field clamping layers 14 are in a body, and a plurality of additional electric field peaks are introduced in the body, so that the doping concentration of the second conductivity type drift region 21 can be further increased, the specific on-resistance is reduced, and only a plurality of injections are required in the process, and no extra steps are required.

Example 4

As shown in fig. 4, a schematic diagram of the shimming device with electric field clamping layers of embodiment 4 is shown, and this example is different from the structure of embodiment 1 in that a first conductivity type electric field clamping layer 14 and a second conductivity type buried layer 25 are provided in the body of the second conductivity type drift region 21. The device introduces two buried layers with different conductive types into the device body, the buried layers have the function of improving the electric field distribution in the device body, meanwhile, the number of the buried layers can be increased according to the needs, the buried layers are completely compatible in process, and only the type and the energy of injected impurities need to be changed.

Example 5

As shown in fig. 5, a schematic diagram of a shimming device having an electric field clamping layer in embodiment 5 is shown, and this example is different from the structure in embodiment 1 in that, under the condition of ensuring depletion continuity, the first conductivity type electric field clamping layer 14 is in a plurality of separated strips in the source-drain direction, which is significant in that the drift region of the device is in a form of injection push well, the concentration distribution satisfies gaussian distribution, the impurity concentration on the surface is the highest, and the impurity concentration in the body is the lowest, so that the electric field clamping layer is changed into a strip, which not only can maintain the original electric field clamping effect, but also can increase the conduction path with high concentration on the surface, and reduce the specific on-resistance of the device. Further, the first conductivity type electric field clamp layer 14 has a plurality of separated circular, or elliptical stripe shapes in the source-drain direction with the depletion continuity ensured. A high concentration of the second conductivity type drift region 21 at the surface can be flown out to improve the performance.

Example 6

As shown in fig. 6, a schematic diagram of the shimming device with electric field clamping layers of embodiment 2 is shown, and this example is different from the structure of embodiment 1 in that the longitudinal floating field plates of the drift region are inserted into the first conductivity type semiconductor substrate 11. The longitudinal floating field plate can simultaneously deplete the first conductivity type semiconductor substrate 11 and the second conductivity type drift region 21, and the drain terminal longitudinal field plate optimizes the internal electric field near the drain terminal, and the operating principle thereof is substantially the same as that of embodiment 1.

Example 7

As shown in fig. 7, a schematic diagram of a shimming device with an electric field clamping layer in embodiment 7 is shown, and this embodiment is different from the embodiment 1 in that a second conductive type buried layer 25 is formed at the bottom of a longitudinal floating field plate by slot implantation. In this example, the second conductive type buried layer 25 introduces a low-resistance conductive path at the bottom of the trench to further reduce the device resistance and increase the device current, and the operation principle is basically the same as that of embodiment 1.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.