阅读说明：本技术 一种相位同步装置、相位同步系统及收发装置 (Phase synchronization device, phase synchronization system and transceiver ) 是由 高鹏 于 2019-05-31 设计创作，主要内容包括：一种相位同步装置、相位同步系统及收发装置,用以为多芯片拼接方案中的每个射频收发机芯片提供相位一致的本振信号。相位同步系统包括：第一射频收发机芯片和第二射频收发机芯片,第一射频收发机芯片包括第一锁相环和第一控制电路,第二射频收发机芯片包括第二锁相环；其中,第一锁相环,用于产生第一本振信号；第二锁相环,用于产生第二本振信号；第一控制电路,用于根据第一本振信号以及第二本振信号检测得到第一相位差,并根据第一相位差产生第一控制信号,以及利用第一控制信号对第一锁相环进行相位控制或对第二锁相环进行相位控制。(A phase synchronization device, a phase synchronization system and a transceiver device are used for providing local oscillator signals with consistent phases for each radio frequency transceiver chip in a multi-chip splicing scheme. The phase synchronization system includes: the first radio frequency transceiver chip comprises a first phase-locked loop and a first control circuit, and the second radio frequency transceiver chip comprises a second phase-locked loop; the first phase-locked loop is used for generating a first local oscillator signal; the second phase-locked loop is used for generating a second local oscillator signal; the first control circuit is used for detecting according to the first local oscillator signal and the second local oscillator signal to obtain a first phase difference, generating a first control signal according to the first phase difference, and performing phase control on the first phase-locked loop or performing phase control on the second phase-locked loop by using the first control signal.)

A phase synchronization system is characterized by comprising a first radio frequency transceiver chip and a second radio frequency transceiver chip, wherein the first radio frequency transceiver chip comprises a first phase-locked loop and a first control circuit, and the second radio frequency transceiver chip comprises a second phase-locked loop; wherein the content of the first and second substances,

the first phase-locked loop is used for generating a first local oscillator signal;

the second phase-locked loop is used for generating a second local oscillator signal;

the first control circuit is used for detecting according to the first local oscillator signal and the second local oscillator signal to obtain a first phase difference, generating a first control signal according to the first phase difference, and performing phase control on the first phase-locked loop or performing phase control on the second phase-locked loop by using the first control signal.

The phase synchronization system of claim 1, wherein the first control circuit comprises:

and the first phase detector is used for detecting and obtaining the first phase difference according to the first local oscillation signal and the second local oscillation signal.

The phase synchronization system of claim 1 or 2, wherein the first control circuit comprises:

and the first phase controller is used for generating the first control signal according to the first phase difference, and the first control signal is used for controlling the frequency division control word of the first phase-locked loop or the second phase-locked loop.

The phase synchronization system of claim 3, wherein the first phase controller is any one of a proportional controller, an integral controller, a proportional-integral controller.

The phase synchronization system according to any of claims 1 to 4, wherein the first phase locked loop is specifically configured to:

generating the first local oscillator signal based on a first reference clock signal;

the second phase-locked loop is specifically configured to:

the second local oscillator signal is generated based on the first reference clock signal.

The phase synchronization system of claim 5, wherein the first phase locked loop is specifically configured to:

and generating the first local oscillator signal according to the first reference clock signal under the control of the first control signal.

The phase synchronization system of claim 5, wherein the second phase locked loop is specifically configured to:

and generating the second local oscillator signal according to the first reference clock signal under the control of the first control signal.

The phase synchronization system of claim 7, further comprising: a third radio frequency transceiver chip comprising a third phase-locked loop and a second control circuit; wherein the content of the first and second substances,

the third phase-locked loop is used for generating a third local oscillator signal;

the second control circuit is configured to obtain a second phase difference according to the third local oscillator signal and the first local oscillator signal, and generate the second control signal according to the second phase difference;

the first phase-locked loop is specifically configured to:

and generating the first local oscillator signal according to the first reference clock signal under the control of the second control signal.

The phase synchronization system of claim 8, wherein the first control circuit comprises:

and the first driver is used for receiving the first local oscillation signal and outputting the driven first local oscillation signal to the second control circuit.

The phase synchronization system of any one of claims 1 to 9, wherein the first control circuit comprises:

and the first buffer is used for buffering the second local oscillation signal.

The phase synchronization system of any one of claims 8 to 10, wherein the first control circuit comprises:

a second phase detector for detecting a third phase difference according to the third local oscillator signal and the first local oscillator signal,

when the second control circuit generates the second control signal, the second control circuit is specifically configured to:

and generating the second control signal according to the difference between the second phase difference and the third phase difference.

The phase synchronization system of claim 11, wherein the second radio frequency transceiver chip further comprises:

the third control circuit is used for detecting according to the first local oscillator signal and the second local oscillator signal to obtain a fourth phase difference;

the first control circuit, when generating the first control signal, is specifically configured to:

and generating the first control signal according to the difference between the first phase difference and the fourth phase difference.

The phase synchronization system of claim 12, wherein the first control circuit comprises:

and the second driver is used for receiving the first local oscillation signal and outputting the driven first local oscillation signal to the third control circuit.

The phase synchronization system of any of claims 11 to 13, wherein the first control circuit further comprises:

and the second buffer is used for buffering the third local oscillation signal.

The phase synchronization system according to any one of claims 1 to 14, wherein the first control circuit, when detecting the first phase difference according to the first local oscillator signal and the second local oscillator signal, is specifically configured to:

the first control circuit detects a phase difference between the first local oscillation signal and the second local oscillation signal to obtain the first phase difference.

The phase synchronization system of any one of claims 12-15, wherein the first control circuit further comprises:

a first frequency divider coupled to the first phase locked loop and configured to divide the frequency of the first local oscillator signal;

the third control circuit further includes:

the second frequency divider is coupled with the second phase-locked loop and used for dividing the frequency of the second local oscillator signal, and the frequency dividing ratio of the second frequency divider is the same as that of the first frequency divider;

when the first phase difference is obtained by detecting according to the first local oscillator signal and the second local oscillator signal, the first control circuit is specifically configured to:

the first control circuit detects a phase difference between the first local oscillation signal subjected to frequency division by the first frequency divider and the second local oscillation signal subjected to frequency division by the second frequency divider to obtain the first phase difference.

The phase synchronization system of any one of claims 5 to 16, wherein the first phase locked loop comprises:

a third phase detector for detecting a phase difference of the first reference clock signal and a feedback clock signal;

a loop controller coupled to the third phase detector for generating a third control signal according to a phase difference between the first reference clock signal and the feedback clock signal;

a controlled oscillator coupled to the loop controller for generating the first local oscillator signal according to the third control signal;

a modulator for generating a frequency division control word according to the first control signal or the second control signal and the frequency control word;

and the third frequency divider is coupled with the controlled oscillator and the modulator and used for generating the feedback clock signal according to the first local oscillator signal and the frequency division control word and outputting the feedback clock signal to the third phase detector.

The phase synchronization system of any one of claims 1-17, wherein the first radio frequency transceiver chip further comprises a first digital interface, the second radio frequency transceiver chip further comprises a second digital interface, the system further comprising a control chip;

wherein the first digital interface is coupled with the first control circuit, and is used for receiving and outputting the first control signal; the control chip is coupled with the first digital interface and the second digital interface and used for transmitting the first control signal output by the first digital interface to the second digital interface; the second digital interface is coupled to the second phase locked loop.

The phase synchronization system of any one of claims 1-18, wherein the first radio frequency transceiver chip further comprises:

the fourth phase-locked loop is used for generating a fourth local oscillator signal;

and the fourth control circuit is used for detecting according to the fourth local oscillator signal and the first local oscillator signal to obtain a fifth phase difference, generating a fourth control signal according to the fifth phase difference, and performing phase control on the first phase-locked loop or performing phase control on the fourth phase-locked loop by using the fourth control signal.

The phase synchronization system of any one of claims 1-19, wherein the first radio frequency transceiver chip further comprises: the first phase-locked loop is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: the second phase-locked loop is specifically configured to provide the second local oscillator signals for the plurality of second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are used for supporting MIMO transmission.

The phase synchronization system of any one of claims 1-19, wherein the first radio frequency transceiver chip further comprises: the first phase-locked loop is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: the second phase-locked loop is specifically configured to provide the second local oscillator signals for the plurality of second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are configured to support phased array transmission.

A phase synchronization apparatus, comprising a first phase locked loop and a first control circuit integrated in a first radio frequency transceiver chip; wherein the content of the first and second substances,

the first phase-locked loop is used for generating a first local oscillator signal;

the first control circuit is used for detecting according to the first local oscillator signal and a second local oscillator signal generated by a second phase-locked loop in a second radio frequency transceiver chip to obtain a first phase difference, generating a first control signal according to the first phase difference, and performing phase control on the first phase-locked loop or performing phase control on the second phase-locked loop by using the first control signal.

The phase synchronization apparatus of claim 22, wherein the first phase-locked loop is specifically configured to:

generating the first local oscillator signal based on a first reference clock signal; the first reference clock signal is a reference clock signal based on which the second local oscillator signal is generated by the second phase-locked loop.

Phase synchronization device according to claim 22 or 23, characterized in that the first phase locked loop is specifically configured to:

and generating the first local oscillator signal according to the first reference clock signal under the control of the first control signal.

Phase synchronization device according to claim 22 or 23, characterized in that the first phase locked loop is specifically configured to:

and under the control of a second control signal, generating the first local oscillation signal according to the first reference clock signal, wherein the second control signal is a control signal generated by a second control circuit in a third radio frequency transceiver chip, and the second control circuit is used for detecting a second phase difference according to a third local oscillation signal generated by a third phase-locked loop in the third radio frequency transceiver chip and the first local oscillation signal and generating the second control signal according to the second phase difference.

The phase synchronization apparatus of any one of claims 22 to 25, further comprising: a first digital interface;

the first digital interface is coupled with the first control circuit and used for receiving the first control signal and outputting the first control signal to a control chip; the control chip is coupled with the first digital interface and a second digital interface in the second radio frequency transceiver chip and is used for transmitting the first control signal output by the first digital interface to the second digital interface; the second digital interface is coupled to the second phase locked loop.

The phase synchronization device according to any one of claims 22 to 26, wherein the first radio frequency transceiver chip further comprises: the first phase-locked loop is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: the second phase-locked loop is specifically configured to provide the second local oscillator signals for the plurality of second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are configured to support MIMO transmission.

The phase synchronization device according to any one of claims 22 to 26, wherein the first radio frequency transceiver chip further comprises: the first phase-locked loop is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: the second phase-locked loop is specifically configured to provide the second local oscillator signals for the plurality of second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are configured to support phased array transmission.

A transceiver device comprising the first and second rf transceiver chips as claimed in any one of claims 1 to 21; the first radio frequency transceiver chip further comprises: a first phase-locked loop in the first radio frequency transceiver chip is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: a second phase-locked loop in the second radio frequency transceiver chip is specifically configured to provide the second local oscillator signals for the second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are configured to support MIMO transmission.

A transceiver device comprising the first and second rf transceiver chips as claimed in any one of claims 1 to 21; the first radio frequency transceiver chip further comprises: a first phase-locked loop in the first radio frequency transceiver chip is specifically configured to provide the first local oscillator signals for the plurality of first transmission channels;

the second radio frequency transceiver chip further comprises: a second phase-locked loop in the second radio frequency transceiver chip is specifically configured to provide the second local oscillator signals for the second transmission channels;

the plurality of first transmission channels and the plurality of second transmission channels are configured to support phased array transmission.