阅读说明：本技术 沟槽栅vdmos器件及其制备方法 (Trench gate VDMOS device and preparation method thereof ) 是由 方冬 肖魁 于 2020-05-18 设计创作，主要内容包括：本申请涉及一种沟槽栅VDMOS器件及其制备方法,其中,器件包括：漂移区、形成于漂移区内的体区、形成于体区上的源区,漂移区和源区具有第一导电类型,体区具有第二导电类型；源区开设有底部延伸至漂移区的第一沟槽和第二沟槽,各沟槽内壁形成有栅氧层；第一多晶硅体形成于第一沟槽内和第二沟槽内且相互电连接,第二多晶硅体形成于第一沟槽内并与第一多晶硅体隔离,在第一沟槽内,第一多晶硅体的深度大于第二多晶硅体的深度；源极引出结构与源区以及第一多晶硅体连接；栅极引出结构与第二多晶硅体连接。上述VDMOS器件,在元胞区开设多个沟槽以在漂移区内部形成多个内场板,增强漂移区的耗尽,提高器件耐压。(The application relates to a groove grid VDMOS device and a preparation method thereof, wherein the device comprises: the drift region, the body region formed in the drift region, the source region formed on the body region, the drift region and the source region have the first conductivity type, the body region has the second conductivity type; the source region is provided with a first groove and a second groove, the bottoms of the first groove and the second groove extend to the drift region, and a gate oxide layer is formed on the inner wall of each groove; the first polycrystalline silicon body is formed in the first groove and the second groove and is electrically connected with each other, the second polycrystalline silicon body is formed in the first groove and is isolated from the first polycrystalline silicon body, and the depth of the first polycrystalline silicon body is larger than that of the second polycrystalline silicon body in the first groove; the source electrode lead-out structure is connected with the source region and the first polycrystalline silicon body; the grid electrode leading-out structure is connected with the second polycrystalline silicon body. According to the VDMOS device, the cell region is provided with the plurality of grooves so as to form the plurality of inner field plates in the drift region, the depletion of the drift region is enhanced, and the withstand voltage of the device is improved.)

1. A trench-gate VDMOS device, comprising:

a drift region formed on the semiconductor substrate and having a first conductivity type;

the body region is formed on the upper surface layer of the drift region and has a second conduction type;

the source region is formed on the upper surface layer of the body region and has a first conduction type;

the first groove penetrates through the source region and the body region in sequence and extends into the drift region;

the second groove is arranged at an interval with the first groove, sequentially penetrates through the source region and the body region, and extends into the drift region;

the first polycrystalline silicon body is formed in the first groove and the second groove and is electrically connected with each other, and gate oxide layers are formed between the first polycrystalline silicon body and the inner wall of the first groove and between the first polycrystalline silicon body and the inner wall of the second groove;

the second polycrystalline silicon body is formed in the first groove and isolated from the first polycrystalline silicon body, a gate oxide layer is formed between the second polycrystalline silicon body and the inner wall of the first groove, and the distance between the bottom of the first polycrystalline silicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polycrystalline silicon body and the bottom of the first groove in the first groove;

a source lead-out structure connected to the source region and the first polysilicon body; and

and the grid electrode leading-out structure is connected with the second polycrystalline silicon body.

2. The VDMOS device of claim 1, wherein the first trenches and the second trenches are alternately juxtaposed.

3. The VDMOS device of claim 2, wherein the first trench and the second trench are elongated, the gate-out structure is disposed at an end of each of the first trenches on the same side and connected to the second poly body in the first trench, the gate-out structure is disposed on each of the second trenches and connected to the first poly body in the second trench, and the gate-out structure and the source-out structure are staggered from each other.

4. The VDMOS device of claim 1, wherein the first trench and the second trench are interconnected by a communication trench, wherein the first polysilicon body is further formed within the communication trench, and wherein a gate oxide layer is formed between the first polysilicon body and an inner wall of the communication trench.

5. The VDMOS device of claim 4, wherein the source extraction structure is disposed on the first polysilicon in the second trench and connected to the first polysilicon body in the second trench, and wherein an end of the source extraction structure extends along a length of the second trench and through the connecting trench.

6. The VDMOS device of claim 4, wherein the communication trench penetrates the source region and the body region in sequence and extends into the drift region.

7. The VDMOS device of claim 1, wherein a bottom of the second trench is flush with a bottom of the first trench.

8. The VDMOS device of claim 1, further comprising:

an interlayer dielectric layer formed on the top surfaces of the source region, the first trench and the second trench;

the source electrode leading-out structure penetrates through the interlayer dielectric layer and the source region and is connected with the source and the first polycrystalline silicon body in the second groove;

the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second polycrystalline silicon body in the first groove.

9. A preparation method of a groove gate VDMOS device is characterized by comprising the following steps:

providing a semiconductor substrate and forming a first conductive type drift region on the semiconductor substrate;

forming a first groove and a second groove on the drift region;

forming a gate oxide layer on the inner walls of the first trench and the second trench, forming first polysilicon bodies electrically connected with each other in the first trench and the second trench, and forming a second polysilicon body isolated from the first polysilicon body in the first trench, wherein in the first trench, the distance between the bottom of the first polysilicon body and the bottom of the first trench is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first trench;

doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the side wall of the first groove and the side wall of the second groove, wherein the depth of the body region is smaller than that of the first groove and the second groove; doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the side wall of the first groove and the side wall of the second groove; and

and forming a source electrode lead-out structure connected with the source region and the first polycrystalline silicon body, and forming a grid electrode lead-out structure connected with the second polycrystalline silicon body.

10. The VDMOS device manufacturing method according to claim 9, wherein a first trench and a second trench are opened in the drift region, and a communication trench communicating the first trench and the second trench is opened in the drift region; forming a gate oxide layer on the inner wall of the communication groove while forming the gate oxide layer on the inner walls of the first and second grooves; and forming a first polycrystalline silicon body in the first groove and the second groove, wherein the first polycrystalline silicon body is electrically connected with each other and is formed in the communication groove at the same time.

Technical Field

The application relates to the field of semiconductors, in particular to a trench gate VDMOS device and a preparation method thereof.

Background

In a MOS (Metal Oxide Semiconductor) field effect transistor, a conduction channel is formed between a source electrode and a drain electrode, and the presence of the conduction channel makes the MOS field effect transistor have a certain on resistance, and the larger the on resistance is, the larger the power consumption is, and therefore, the on resistance needs to be reduced as much as possible. At present, a Vertical Double diffusion Metal Oxide Semiconductor (VDMOS) field effect transistor (fet) is usually used, and a trench gate structure is formed to change a conduction channel from a horizontal direction to a Vertical direction, thereby greatly increasing cell density and reducing conduction resistance. However, in order to further reduce the on-resistance of the trench-gate VDMOS device, the doping concentration of the drift region needs to be increased, and the increase in the doping concentration would weaken the voltage endurance capability of the device.

Disclosure of Invention

Therefore, it is necessary to provide a new VDMOS device and a manufacturing method thereof for solving the technical problem that it is difficult to further reduce the on-resistance of the trench gate VDMOS device.

A trench-gate VDMOS device comprising:

a drift region formed on the semiconductor substrate and having a first conductivity type;

the body region is formed on the upper surface layer of the drift region and has a second conduction type;

the source region is formed on the upper surface layer of the body region and has a first conduction type;

the first groove penetrates through the source region and the body region in sequence and extends into the drift region;

the second groove is arranged at an interval with the first groove, sequentially penetrates through the source region and the body region, and extends into the drift region;

the first polycrystalline silicon body is formed in the first groove and the second groove and is electrically connected with each other, and gate oxide layers are formed between the first polycrystalline silicon body and the inner wall of the first groove and between the first polycrystalline silicon body and the inner wall of the second groove;

the second polycrystalline silicon body is formed in the first groove and isolated from the first polycrystalline silicon body, a gate oxide layer is formed between the second polycrystalline silicon body and the inner wall of the first groove, and the distance between the bottom of the first polycrystalline silicon body and the bottom of the first groove is smaller than the distance between the bottom of the second polycrystalline silicon body and the bottom of the first groove in the first groove;

a source lead-out structure connected to the source region and the first polysilicon body; and

and the grid electrode leading-out structure is connected with the second polycrystalline silicon body.

In the VDMOS device, a plurality of trenches are formed in the cell region, wherein the first trench is filled with the second polysilicon body, and the second polysilicon body is connected to the gate to form a trench gate structure, and a longitudinal conduction channel is formed through the trench gate structure. Meanwhile, the bottom of the first groove and the second groove are filled with first polycrystalline silicon bodies which are electrically connected with each other, the first polycrystalline silicon bodies are connected with the source electrode, namely a plurality of inner field plates connected with the source electrode are formed in the cell region, the electric field distribution of the drift region can be adjusted through the inner field plates, the depletion of the drift region is enhanced, and the breakdown voltage of the VDMOS device is improved. Therefore, under the condition of equal breakdown voltage, the drift region of the trench gate VDMOS can improve the doping concentration, so that the on-resistance is reduced. That is, the trench gate VDMOS device in the present application has a lower on-resistance under the same breakdown voltage.

In one embodiment, the first trenches and the second trenches are arranged in alternating columns.

In one embodiment, the first trenches and the second trenches are strip-shaped, the gate lead-out structures are disposed at ends of the first trenches on the same side and connected to the second polysilicon bodies in the first trenches, the gate lead-out structures are disposed on the second trenches and connected to the first polysilicon bodies in the second trenches, and the gate lead-out structures and the source lead-out structures are staggered.

In one embodiment, the first trench and the second trench are communicated with each other through a communication trench, the first polysilicon body is further formed in the communication trench, and a gate oxide layer is formed between the first polysilicon body and the inner wall of the communication trench.

In one embodiment, the source lead-out structure is arranged on the first polysilicon in the second trench and connected with the first polysilicon body in the second trench, and one end of the source lead-out structure extends along the length direction of the second trench and passes through the communication trench.

In one embodiment, the communication trench penetrates the source region and the body region in sequence and extends into the drift region.

In one embodiment, the bottom of the second trench is flush with the bottom of the first trench.

In one embodiment, the method further comprises the following steps:

an interlayer dielectric layer formed on the top surfaces of the source region, the first trench and the second trench;

the source electrode leading-out structure penetrates through the interlayer dielectric layer and the source region and is connected with the source and the first polycrystalline silicon body in the second groove;

the grid electrode leading-out structure penetrates through the interlayer dielectric layer and is connected with the second polycrystalline silicon body in the first groove.

A preparation method of a groove gate VDMOS device comprises the following steps:

providing a semiconductor substrate and forming a first conductive type drift region on the semiconductor substrate;

forming a first groove and a second groove on the drift region;

forming a gate oxide layer on the inner walls of the first trench and the second trench, forming first polysilicon bodies electrically connected with each other in the first trench and the second trench, and forming a second polysilicon body isolated from the first polysilicon body in the first trench, wherein in the first trench, the distance between the bottom of the first polysilicon body and the bottom of the first trench is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first trench;

doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the side wall of the first groove and the side wall of the second groove, wherein the depth of the body region is smaller than that of the first groove and the second groove; doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the side wall of the first groove and the side wall of the second groove; and

and forming a source electrode lead-out structure connected with the source region and the first polycrystalline silicon body, and forming a grid electrode lead-out structure connected with the second polycrystalline silicon body.

In the preparation method of the trench gate VDMOS device, a plurality of trenches are formed in the cell area, wherein a second polysilicon body is formed in the first trench and connected with the gate, which is equivalent to forming a plurality of trench gates in the cell area. And forming a first polysilicon body in the bottom of the first trench and the second trench, wherein the first polysilicon body is connected with the source electrode, which is equivalent to forming a plurality of inner field plates in the cellular region, so that the depletion of the drift region is enhanced, and the breakdown voltage is improved. Therefore, under the condition of equal breakdown voltage, the trench gate VDMOS device prepared by the method can improve the doping concentration of a drift region of the device, so that the on-resistance of the device is reduced.

In one embodiment, a first trench and a second trench are opened on the drift region, and a communication trench communicating the first trench and the second trench is opened on the drift region; forming a gate oxide layer on the inner wall of the communication groove while forming the gate oxide layer on the inner walls of the first and second grooves; and forming a first polycrystalline silicon body in the first groove and the second groove, wherein the first polycrystalline silicon body is electrically connected with each other and is formed in the communication groove at the same time.

Drawings

FIG. 1 is a cross-sectional side view of a cell region of a trench-gate VDMOS device in an embodiment of the present application;

FIG. 2 is a cross-sectional side view of a trench-gate VDMOS device at a via trench in an embodiment of the present application;

FIG. 3 is a cross-sectional side view of a trench gate VDMOS device at a gate lead-out structure in an embodiment of the present application;

FIG. 4 is a cross-sectional view of a trench-gate VDMOS device taken along line A-A' of FIG. 1 in accordance with an embodiment of the present application;

FIG. 5a is a schematic view of a structure in a first trench according to an embodiment of the present application;

FIG. 5b is a schematic view of a structure in a first trench according to another embodiment of the present application;

FIG. 6 is a flowchart illustrating steps of a method for manufacturing a trench gate VDMOS device according to an embodiment of the present disclosure;

fig. 7a to 7h are cross-sectional views of structures corresponding to relevant steps of a method for manufacturing a trench gate VDMOS device according to an embodiment of the present application.

Description of the reference symbols

A 100 drift region; a 110 body region; 111 a source region; 112 heavily doped region; 120 a first trench; 130 a second trench; 140 a gate oxide layer; 150 a first polysilicon body; 160 a second polysilicon body; 170 an isolation structure; 180 are communicated with the grooves; 200 dielectric layers; 310 source electrode leading-out structure; 320 gate lead-out structure.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In conjunction with fig. 1 and 4, fig. 4 is a cross-sectional view of the trench-gate VDMOS device taken along line AA 'in fig. 1, and fig. 1 is a cross-sectional view of the trench-gate VDMOS device taken along line BB' in fig. 4. The trench gate VDMOS device includes a drift region 100, the drift region 100 is formed on a semiconductor substrate, and may be specifically formed on an epitaxial layer formed by epitaxial growth on the semiconductor substrate, a body region 110 is formed on an upper surface of the drift region 100, an active region 111 is formed on an upper surface of the body region 110, the active region 111 is provided with a plurality of first trenches 120 and second trenches 130 penetrating through the active region 111 and the body region 110 and extending into the drift region 100, that is, bottom ends of the first trenches 120 and the second trenches 130 are both located in the drift region 100. The first polysilicon body 150 is formed in each of the first trench 120 and the second trench 130, the first polysilicon body 150 in the first trench 120 and the first polysilicon body 150 in the second trench 130 are electrically connected to each other and integrally formed, and the gate oxide layer 140 is formed between the first polysilicon body 150 and the inner wall of the first trench 120 and between the first polysilicon body 150 and the inner wall of the second trench 130. A second polysilicon body 160 is further formed in the first trench 120, the second polysilicon body 160 is isolated from the first polysilicon body 150, and a gate oxide layer 140 is also formed between the second polysilicon body 160 and the inner wall of the second trench 120, in the first trench 120, the depth of the first polysilicon body 150 is greater than the depth of the second polysilicon body 160, that is, the distance from the first polysilicon body 150 to the bottom of the first trench 120 is less than the distance from the second polysilicon body 160 to the bottom of the first trench 120. The trench gate VDMOS device further includes a source extraction structure 310 and a gate extraction structure 320, the source extraction structure 310 and the gate extraction structure 320 may be metal columns, specifically, tungsten metal, the source extraction structure 310 is connected to the source region 111 and the first polysilicon body 150, and the gate extraction structure 320 is connected to the second polysilicon body 160. The drift region 100 and the source region 111 have a first conductivity type, and the body region 110 has a second conductivity type. The first conductive type is an N type, and the second conductive type is a P type; or the first conduction type is P type, and the second conduction type is N type. It is understood that the front surface of the trench gate VDMOS device should further have a source metal layer and a gate metal layer which are isolated from each other, the source lead-out structures 310 are connected to the source metal layer, the gate lead-out structures 320 are connected to the gate metal layer, and a drain metal layer is further formed on the back surface of the trench gate VDMOS device.

In the trench gate VDMOS device, the top source region 111 is connected to the source metal layer through the source lead-out structure 310, the bottom drift region 100 is connected to the drain metal layer as the drain region, the body region 110 in the middle is used as the channel region, the first trench 120 penetrates through the body region 110 and extends into the drift region 100, the gate oxide layer 140 and the second polysilicon body 160 are arranged in the first trench 120 and connected to the gate metal layer through the gate lead-out structure 320, that is, the first trench 120 and the gate oxide layer 140 and the second polysilicon body 160 therein form a trench gate structure, thereby forming the trench gate VDMOS device. By means of this trench-gate structure, a longitudinal conducting channel can be formed in the body region 110. Meanwhile, the trench-gate VDMOS device further has a second trench 130, the second trench 130 penetrates the source region 111 and the body region 110, that is, a second trench 130 is opened in the cell region of the trench gate VDMOS device, a first polysilicon body 150 is formed in the first trench 120 and the second trench 130, the first polysilicon body 150 is connected to the source metal layer through the source lead-out structure, which is equivalent to a plurality of inner field plates formed in the drift region 100, through which inner field plates connected to the source metal layer, the distribution of the electric field in the drift region 100 can be adjusted, the depletion of the drift region 100 can be enhanced, and compared with the common trench gate VDMOS device, the trench gate VDMOS device in the present application has a higher breakdown voltage, that is, under the condition of ensuring the same breakdown voltage, the drift region 100 of the trench gate VDMOS device in the present application may have a higher doping concentration, therefore, the trench gate VDMOS device in the present application also has a lower on-resistance. Meanwhile, in the first trench 120, the first polysilicon body 150 connected to the source metal layer is closer to the bottom of the trench than the second polysilicon body 160 connected to the gate, whereby the parasitic capacitance between the gate and the drain can be reduced, resulting in better characteristics of the device.

In one embodiment, as shown in fig. 1, the first trenches 120 and the second trenches 130 are alternately arranged in parallel, and the distance between the trenches is smaller, which is more beneficial to enhance the depletion of the drift region. In one embodiment, as shown in fig. 4, the first trench 120 and the second trench 130 are both in a long strip shape, the first trench 120 and the second trench are arranged in parallel along the width direction (Y direction), and at least one end of the first trench 120 extends along the length direction (X direction) and crosses the source region 111 to extend out of the area covered by the source region 111. In the trench gate VDMOS device, a region covered by the source region 111 is a cell region of the trench gate VDMOS device, and a region not covered by the source region 111 is a peripheral region, in this embodiment, a part of the first trench 120 is located in the cell region, and another part is located in the peripheral region, wherein, as shown in fig. 2, fig. 2 is a cross-sectional side view of the trench gate VDMOS device along a CC' section line in fig. 4, and is connected to the gate lead-out structure 320 through the second polysilicon body 160 located in the first trench 120 in the peripheral region to lead out the gate. Because the source electrode leading-out structure 310 is formed in the cellular region, and the grid electrode leading-out structure 320 is arranged in the peripheral region, the source electrode leading-out structure 310 and the grid electrode leading-out structure 320 can be staggered, and the formation of a source electrode metal layer and a grid electrode metal layer which are mutually isolated at the later stage is facilitated.

In an embodiment, the first trench 120 and the second trench 130 are connected to each other, specifically, a connection trench 180 is further formed between the first trench 120 and the second trench 130, a first polysilicon body 150 is also formed in the connection trench 180, a gate oxide layer is also formed between the first polysilicon body in the connection trench and the inner wall of the trench, and the first polysilicon bodies 150 in the first trench 120, the second trench 130 and the connection trench 180 are electrically connected to each other and integrally formed. In the present embodiment, referring to fig. 3 and fig. 4, fig. 3 is a side sectional view of the trench-gate VDMOS device along the section line DD' in fig. 4, and the communication trench 180 is specifically opened in the cell region, that is, the communication trench penetrates through the source region 111 and the body region 110 in sequence and extends into the drift region 100. In the present embodiment, the connecting trench 180 is disposed in the cell region, and the first polysilicon body and the gate oxide layer of the connecting trench also serve as an inner field plate to further enhance the depletion of the drift region. The number of the communication grooves between the adjacent grooves is not limited, and specifically may be 1 or multiple, and the positions of the communication grooves may be connected to both ends of the first groove and the second groove, or connected to the middle of the first groove and the second groove, as long as the communication between the adjacent grooves is realized.

Further, with continued reference to fig. 4, the source lead-out structure 310 passes through the intersection point of the communicating trench 180 and the second trench 130, that is, the source lead-out structure 310 extends along the length direction of the second trench and passes through the communicating position of the second trench 130 and the communicating trench 180, which is beneficial to transmitting the voltage on the source lead-out structure 310 to the first polysilicon body 150 in the first trench 120, so that the voltage distribution on the first polysilicon body 150 in the first trench 120 and the second trench 130 is uniform, thereby being beneficial to performing electric field modulation on the drift region. Meanwhile, the gate lead-out structure 320 needs to be connected with the gate metal layer, the source lead-out structure 310 needs to be connected with the source metal layer, and the communication groove 180 and the gate lead-out structure 320 are arranged in a staggered mode, so that the source metal layer and the gate metal layer which are isolated from each other can be formed.

In an embodiment, the bottom of the first trench 120 is flush with the bottom of the second trench 130, that is, the depths of the first trench 120 and the second trench 130 are the same, so that on one hand, the etching process steps can be simplified, the first trench and the second trench can be formed through one etching step, and on the other hand, the modulation effect on the electric field of the drift region 100 can be enhanced. Further, the first trench 120 and the second trench 130 may have the same size. In an embodiment, the plurality of first trenches 120 and the plurality of second trenches 130 are alternately arranged, the adjacent first trenches 120 and the adjacent second trenches 130 have the same spacing, and the first trenches 120 and the second trenches 130 are uniformly distributed, so that the inner field plates in the drift region 100 are uniformly distributed, which is also beneficial to enhancing the modulation of the electric field in the drift region 100.

In an embodiment, an interlayer dielectric layer 200 is further formed on the source region 111, the first trench 120, and the second trench 130, the dielectric layer 200 may be specifically silicon oxide, the source lead-out structure 310 is formed right above the second trench 130, penetrates through the interlayer dielectric layer 200 and the source region 111, and is connected to the source region 111 and the first polysilicon body 150 in the second trench 130, and the gate lead-out structure 320 is formed right above the first trench 120, penetrates through the interlayer dielectric layer 200, and is connected to the second polysilicon body 160 in the first trench 120.

In an embodiment, as shown in fig. 1, a heavily doped region 112 is further formed in the body region 110, the heavily doped region 112 has the second conductivity type, and the doping concentration of the heavily doped region 112 is higher than that of the body region 110, the heavily doped region 112 is specifically located below the source region 111 and spaced apart from the first trench 120, the second trench 130 penetrates the source region 111, the heavily doped region 112 and the body region 110 in sequence and extends into the drift region 100, the source lead-out structure 310 penetrates the source region 111 and extends into the heavily doped region 112, the source lead-out structure 310 is connected with the source region 111 and the first polysilicon body 150, and the bottom of the source lead-out structure 310 is surrounded by the heavily doped region 112, so as to reduce the contact resistance between the source lead-out structure 310 and the body region 110.

Wherein the distribution of the first polysilicon body 150 and the second polysilicon body 160 within the first trench 120 has a variety of designs. In an embodiment, as shown in fig. 1, in the first trench 120, the first polysilicon body 150 is distributed at the bottom of the first trench 120, the second polysilicon body 160 is distributed at the top of the first trench 120, and the first polysilicon body 150 and the second polysilicon body 160 are isolated by an isolation structure 170, wherein a gate oxide layer is formed between the first polysilicon body 150 and the inner wall of the first trench 120 and between the second polysilicon body 160 and the inner wall of the first trench 120, specifically, the isolation structure 170 is silicon oxide. In this embodiment, the first polysilicon body 150 at the bottom of the first trench can adjust the electric field in the drift region, enhance the depletion of the drift region, and also weaken the parasitic capacitance between the gate and the drain, thereby improving the device performance. Further, a first polysilicon body 150 is also formed in the communicating trench 180, the first polysilicon bodies in the trenches are electrically connected to each other, a gate oxide layer is also formed between the first polysilicon body 150 and the inner wall of the communicating trench 180, and meanwhile, an isolation structure is also filled above the first polysilicon body in the communicating trench 180, specifically, the isolation structure in the communicating trench 180 is connected to the isolation structure in the first trench 120 and fills the communicating trench 180 to isolate the first polysilicon body 150 from the second polysilicon body 160. In one embodiment, the top surface of the first polysilicon body 150 and the bottom surface of the second polysilicon body 160 are approximately flat surfaces within the first trench 120. In another embodiment, as shown in FIG. 5a, in the first trench 120, the middle of the top surface of the first polysilicon body 150 is protruded outward, and the middle of the bottom surface of the second polysilicon body 160 is recessed inward to correspond to the protrusion of the first polysilicon body 150.

In an embodiment, as shown in fig. 5b, in the first trench 120, the first polysilicon body 150 extends from the top of the first trench 120 to the bottom of the first trench 120, a gate oxide layer 140 is formed between the first polysilicon body 150 and the inner wall of the first trench 120, the second polysilicon body 160 is formed in the gate oxide layer 140 on both sides of the first polysilicon body 150, the first polysilicon body 150 and the second polysilicon body 160 are isolated by the gate oxide layer 140, and the depth of the first polysilicon body 150 extending to the bottom of the trench is greater than the depth of the second polysilicon body 160 extending to the bottom of the trench. In the present embodiment, the second polysilicon body 160 is provided in the gate oxide layer 140, and the thickness of the gate oxide layer 140 can be increased, thereby enhancing the device withstand voltage.

The application also relates to a preparation method of the trench gate VDMOS device, as shown in fig. 6, the preparation method comprises the following steps:

step S610: a semiconductor substrate is provided and a drift region of a first conductivity type is formed on the semiconductor substrate.

As shown in fig. 7a, the drift region 100 is formed by doping the semiconductor substrate with the first conductivity type, and specifically, the drift region 100 may be formed on an epitaxial layer on the semiconductor substrate by doping the epitaxial layer.

Step S620: and forming a first trench and a second trench in the drift region.

As shown in fig. 7b, a plurality of first trenches 120 and second trenches 130 are opened on the drift region 100 by photolithography and etching processes. In a specific process, the first trench and the second trench may be formed by a single photolithography and etching process. The dimensions, positions and spacing relationships of the first trench 120 and the second trench 130 are described above, and are not described herein again.

In a specific embodiment, the first trench 120 and the second trench 130 are opened in the drift region, and simultaneously, a communication trench 180 for communicating the first trench 120 and the second trench 130 is opened in the drift region. In a specific process, the first trench, the second trench and the communication trench may be formed by a single photolithography and etching process.

Step S630: forming a gate oxide layer on the inner walls of the first trench and the second trench, forming first polysilicon bodies electrically connected with each other in the first trench and the second trench, and forming a second polysilicon body isolated from the first polysilicon body in the first trench, wherein in the first trench, the distance between the bottom of the first polysilicon body and the bottom of the first trench is smaller than the distance between the bottom of the second polysilicon body and the bottom of the first trench.

In an embodiment, when the communication trench 180 is formed, a gate oxide layer may be simultaneously formed on the inner walls of the first trench 120, the second trench 130, and the communication trench 180, and then the electrically connected first polysilicon body 150 may be integrally formed in the first trench 120, the second trench 130, and the communication trench 180 at the same time.

Since the structure of the first and second polysilicon bodies 150 and 160 in the first trench 120 has various forms, accordingly, the step of forming the first and second polysilicon bodies 150 and 160 in the first trench 120 has various embodiments. In one embodiment, step S630 may include the following steps:

step S631: and forming a gate oxide layer on the inner walls of the first trench and the second trench.

As shown in fig. 7c, a gate oxide layer 140 is formed on the inner walls of the first trench 120 and the second trench 130, and the gate oxide layer 140 may be formed, specifically, by thermal oxidation. Specifically, the first trench 120 and the second trench 130 communicate with each other through a communication trench, and a gate oxide layer is also formed on an inner wall of the communication trench. In a specific process, a gate oxide layer may be formed on the inner walls of all the trenches by a thermal oxidation process.

Step S632: and filling the first and second trenches with first polysilicon bodies electrically connected with each other.

As shown in fig. 7d, the first polysilicon body 150 is filled in the first trench 120 and the second trench 130, and the first polysilicon body 150 in the first trench 120 and the second trench 130 are electrically connected to each other and integrally formed. Specifically, the first polysilicon body may be formed by a deposition process, and the first polysilicon body 150 fills the first trench and the second trench. It will be appreciated that the communication trenches are also filled with the first polysilicon body. In a specific process, the first polysilicon body may be filled in all the trenches by a single deposition process.

Step S633: and etching the first polycrystalline silicon body and the gate oxide layer positioned at the top of the first groove, and reserving the first polycrystalline silicon body and the gate oxide layer at the bottom of the first groove.

As shown in fig. 7e, the first polysilicon body and the gate oxide layer at the top of the first trench 120 are etched, leaving the first polysilicon body 150 at the bottom of the first trench 120 and the gate oxide layer 140 between the first polysilicon body 150 and the first trench sidewall.

Step S634: and forming an isolation structure in the first trench, wherein the isolation structure covers the first polysilicon body at the bottom of the trench and does not fill the first trench.

As shown in fig. 7f, an isolation structure 170, which may be specifically silicon oxide, is deposited in the first trench 120 by a deposition process, wherein the isolation structure 170 covers the first polysilicon body 150 and does not fill the first trench 120.

Step S635: and forming a gate oxide layer on the side wall of the first groove above the isolation structure and filling the first groove with a second polysilicon body.

As shown in fig. 7g, a gate oxide layer is formed on the sidewall of the first trench 120 above the isolation structure 170 and the second polysilicon body 160 is filled in the first trench 120, the second polysilicon body 160 is isolated from the inner wall of the first trench 120 by the gate oxide layer 140, and the second polysilicon body 160 is isolated from the first polysilicon body 150 by the isolation structure 170. It is understood that, in order to isolate the first polysilicon body 150 from the second polysilicon body 160, in the step S633, the first polysilicon body and the gate oxide layer at the top of the communication trench are also etched away, in the step S634, an isolation structure is deposited in the communication trench, the isolation structure in the communication trench fills the communication trench and is connected to the isolation structure in the first trench 120, and the second polysilicon body 160 at the top of the first trench 120 is isolated from the first polysilicon body 150 at the bottom of the first trench 120 and the first polysilicon body 150 in the second trench 130 by the bottom isolation structure and the isolation structures at both sides.

Step S640: doping the upper surface layer of the drift region to form a second conductive type body region which is in contact with the side wall of the first groove and the side wall of the second groove, wherein the depth of the body region is lower than that of the first groove and the second groove; and doping the upper surface layer of the body region to form a first conductive type source region which is in contact with the side wall of the first groove and the side wall of the second groove.

As shown in fig. 7h, the upper surface layer of the drift region 100 is doped to form a body region 110 of the second conductivity type in contact with the sidewalls of the first trench 120 and the sidewalls of the second trench 130, the depth of the body region 110 is smaller than the depth of the first trench 120 and the second trench 130, i.e. the bottoms of the first trench 120 and the second trench 130 are still located within the drift region 100. The upper surface layer of the body region 110 is doped to form a first conductive type source region 111 contacting the sidewall of the first trench 120 and the sidewall of the second trench 130. An interlayer dielectric layer 200 is formed on the source region 111, the first trench 120 and the second trench 130.

Step S650: and forming a source electrode lead-out structure connected with the source region and the first polycrystalline silicon body, and forming a grid electrode lead-out structure connected with the second polycrystalline silicon body.

As shown in fig. 7h, a source lead-out structure 310 is formed in a region of the interlayer dielectric layer 200 facing the second trench 130, and a gate conductive region is formed in a region facing the first trench 120, wherein the source lead-out structure 310 penetrates through the interlayer dielectric layer 200 and the source region 111 and is connected to the source region 111 and the first polysilicon body 150 in the second trench 130, and the gate lead-out structure penetrates through the interlayer dielectric layer 200 and is connected to the second polysilicon body 160 in the first trench 120. Specifically, the positional relationship between the source lead-out structure and the gate lead-out structure is referred to the above description, and is not described herein again. Specifically, the process of forming the lead-out structure is to firstly form a contact hole, and then fill a conductive material into the contact hole to form the lead-out structure. In an embodiment, in the process of forming the source lead-out structure 310, a source contact hole penetrating through the source region 111 and extending into the body region 110 is firstly formed, then the second conductivity type heavy doping is performed on the body region 110 through the source contact hole, a heavily doped region 112 is formed in the body region 110, the doping concentration of the heavily doped region 112 is greater than that of the body region, finally, a conductive material is filled into the source contact hole, the source lead-out structure 310 is formed, and at this time, the bottom of the source lead-out structure 310 is surrounded by the heavily doped region 112.

According to the preparation method of the trench gate VDMOS device, the cell area is provided with the plurality of trenches, wherein the gate oxide layer and the second polysilicon body are formed in the first trench, the second polysilicon body is connected with the grid electrode to form the trench gate structure, meanwhile, the first polysilicon body is formed in the first trench and the second trench, the first polysilicon body is connected with the source electrode, and equivalently, a plurality of inner field plates are formed in the cell area, so that the electric field of a drift region can be adjusted, and the voltage resistance of the device is enhanced. Therefore, under the condition of the same breakdown voltage, the drift region of the trench gate VDMOS device obtained by the preparation method can have higher doping concentration, and the on-resistance of the device is lower. Meanwhile, according to the preparation method, the first groove, the second groove and the communicating groove can be formed through one-time photoetching and etching processes, compared with a process of only forming the first groove and introducing the groove gate in the traditional VDMOS device, the method for forming the grooves of different types does not increase photoetching times and does not need to increase a mask; and the filling structures in the second groove and the communication groove are synchronously formed in the process step of the groove gate structure, and the second groove and the communication groove are filled without additionally increasing the process, so that the VDMOS device prepared by the preparation method has lower on-resistance, does not need to increase additional process steps, and is compatible with the existing groove gate preparation process.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.