阅读说明：本技术 一种ook解调电路 (OOK demodulation circuit ) 是由 吕游 何峰 赵海军 龚高茂 于 2021-08-25 设计创作，主要内容包括：本发明公开了一种OOK解调电路,其包括模拟数字转换器ADC、第一抽取电路、第二抽取电路、符号硬判决；ADC用于接收,将硬件上的调制模拟信号转为数字信号,送给数字解调部分；第一抽取电路,第一抽取电路用于对ADC的输出进行2倍码率的抽取；第二抽取电路,第二抽取电路用于对第一抽取电路的输出进行1/2抽取,送给符号判决模块进行符号判决；符号硬判决电路用于对抽取后的数据进行判决输出,判决后的数据得到0和1就是恢复出的解调基带数据。本发明的ADC的采样时钟采用LO+DDS可以满足各种码率的OOK信号；此外,ADC只需要2倍码率Rb的采样率,减少了硬件功耗和设计难度,同时也减少了硬件成本。(The invention discloses an OOK demodulation circuit, which comprises an analog-digital converter (ADC), a first extraction circuit, a second extraction circuit and symbol hard decision; the ADC is used for receiving, converting the modulated analog signal on the hardware into a digital signal and sending the digital signal to the digital demodulation part; the first extraction circuit is used for extracting 2 times of code rate of the output of the ADC; the second extraction circuit is used for 1/2 extraction of the output of the first extraction circuit and sending the output to the symbol decision module for symbol decision; the symbol hard decision circuit is used for carrying out decision output on the extracted data, and the obtained 0 and 1 of the decided data are the recovered demodulation baseband data. The sampling clock of the ADC of the invention adopts LO + DDS to meet OOK signals of various code rates; in addition, the ADC only needs 2 times of the sampling rate of the code rate Rb, so that the power consumption and the design difficulty of hardware are reduced, and meanwhile, the hardware cost is also reduced.)

1. An OOK demodulation circuit comprises an analog-digital converter (ADC), a first extraction circuit, a second extraction circuit and symbol hard decision;

the ADC is used for receiving, converting the modulated analog signal on the hardware into a digital signal and sending the digital signal to the digital demodulation part;

the first extraction circuit is used for extracting 2 times of code rate of the output of the ADC;

the second extraction circuit is used for 1/2 extraction of the output of the first extraction circuit and sending the output to the symbol decision module for symbol decision;

the symbol hard decision circuit is used for carrying out decision output on the extracted data, and the obtained 0 and 1 of the decided data are the recovered demodulation baseband data.

2. The OOK demodulation method of claim 1, further comprising the following:

and the quadrature modulation circuit is used for receiving the error clock signal, synthesizing the error clock signal with the local oscillator signal and synthesizing a sampling clock.

3. The OOK demodulation circuit of claim 2, further comprising:

a bit-direct digital frequency synthesizer for converting the error signal into frequency information;

a digital-to-analog converter (DAC) for converting the frequency information to an error clock signal.

4. The OOK demodulation circuit of claim 3, further comprising a device,

the sign loop filter is used for filtering the error signal and sending the filtered error signal to the direct digital frequency synthesizer for processing;

the bit direct digital frequency synthesizer is used for converting the filtered error signal into frequency information.

5. The OOK demodulation circuit of claim 4, further comprising:

the sigma pre-integration is used for carrying out integral smoothing processing on the error signal so as to generate a smoothed error signal;

the sign loop filter is used for filtering the smoothed error signal.

6. The OOK demodulation circuit of claim 5, further comprising:

and the phase discriminator is used for carrying out error extraction on the bit synchronization result of the signal extracted by the first extraction circuit so as to obtain an error signal.

7. The OOK demodulation circuit of claim 2, wherein the quadrature modulation circuit combines a frequency generated by the local oscillator signal with a frequency of the error clock signal by complex conjugate multiplication.

8. The OOK demodulation circuit of claim 6, wherein the phase detector is:

E(r)＝S(YI(r-1/2))[S(YI(r))-S(YI(r-1))]+S(YQ(r-1/2))[sign(YQ(r))-S(YQ(r-1))]

wherein:

s (YI (r-1/2)) [ S (YI (r)) -S (YI (r-1)) ] and S (YQ (r-1/2)) [ sign (YQ (r)) -S (YQ (r-1)) ] are the accumulated sum of the instant branches of the I path and the Q path at the current moment; s represents the sign bit of the sampling point, the positive number is 1, and the negative number is 0; YI (r) and YQ (r) represent sample point values of the two paths of the r-th symbol I, Q at decision time, YI (r-1/2) and YQ (r-1/2) represent intermediate sample point values between the r-th and r-1-th symbols.

9. The OOK demodulation circuit of claim 4, the loop filter being a first order ideal active proportional-integral filter.

10. The OOK demodulation circuit of claim 8, wherein the loop filter is expressed as:

y(n)＝y(n-1)+k1·x(n)-k2·x(n-1)

wherein: x (n) is the loop error amount at the current moment, x (n-1) is the loop error amount at the previous moment, y (n) is the loop filter output error amount required at the current moment, y (n-1) is the loop filter output error amount at the previous moment, and k1 and k2 are parameters of the loop filter.

Technical Field

The invention relates to the field of integrated circuits, in particular to an OOK demodulation circuit.

Background

In the existing On-Off Keying (OOK) demodulation, a high-speed ADC is generally adopted to perform multiple sampling, usually more than 4 times, On a signal, and data bit estimation is performed On the multiple sampled data inside an FPGA to perform bit data recovery, thereby completing OOK demodulation.

Referring to fig. 1, fig. 1 is a diagram of a conventional OOK demodulation circuit using ADC multiple sampling, which includes an ADC, multiple rate integration, symbol hard decision, symbol phase discrimination, sigma-sigma pre-integration, a symbol loop filter, and a pulse generation circuit CLK.

The ADC is used for receiving a modulation signal, converting a modulation analog signal on hardware into a digital signal and sending the digital signal to the digital demodulation part. The multiple-time code rate integration is used for integrating the multiple-time sampling data to obtain a double-time sampling result. One symbol data is sampled twice.

The symbol hard decision circuit is used for carrying out decision distinction between 0 and 1 on the demodulated data. Resulting in recovered demodulated data.

The symbol phase discrimination is used for carrying out error extraction on the bit synchronization result of the received data, and the bit synchronization can be adjusted according to the error.

Sigma pre-integration is used for carrying out integral smoothing processing on an error signal, and a coarse value in an error amount is removed, so that a compensated error value is more accurate.

The sign loop filter is used for filtering the error signal, so that the controlled error signal is smoother.

The pulse generating circuit CLK is used for generating pulses for multiple-code-rate integration.

And performing code source recovery processing on the multiple sampling data inside the processor. The sampling clock of the ADC in fig. 1 must satisfy the rate of more than 4 times the communication code rate Rb. When the OOK communication code rate is high, the ADC sampling clock needs a higher sampling rate, and the processor needs to perform operations on a large amount of data acquired by the ADC to demodulate and recover baseband data.

The ADC samples signals, and bit synchronization tracking needs to be carried out on the sampled signals and baseband data needs to be recovered inside the demodulation processing chip. The specific recovery is to integrate the data under the multiple code rate to obtain symbol information, and then to perform synchronous phase discrimination of the symbols to obtain the in-place synchronous loop error. This error amount is compensated via a loop filter into the entire bit-synchronous loop, which completes the recovery of the baseband data. When the code rate is very high, the sampling rate required by ADC acquisition is multiplied, and the data processing capacity in the demodulation chip is also multiplied, so that the hardware design is very complex. And the sampling rate cannot be larger than Ghz due to the limitations of the ADC device. Resulting in OOK demodulation under this scheme only up to a hundred M code rate.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.

Disclosure of Invention

In view of the above technical problems in the related art, the present invention provides an OOK demodulation circuit, which includes an analog-to-digital converter ADC, a first decimation circuit, a second decimation circuit, and a symbol hard decision;

the ADC is used for receiving, converting the modulated analog signal on the hardware into a digital signal and sending the digital signal to the digital demodulation part;

the first extraction circuit is used for extracting 2 times of code rate of the output of the ADC;

the second extraction circuit is used for 1/2 extraction of the output of the first extraction circuit and sending the output to the symbol decision module for symbol decision;

the symbol hard decision circuit is used for carrying out decision output on the extracted data, and the obtained 0 and 1 of the decided data are the recovered demodulation baseband data.

Specifically, the OOK demodulation circuit further includes the following components:

and the quadrature modulation circuit is used for receiving the error clock signal, synthesizing the error clock signal with the local oscillator signal and synthesizing a sampling clock.

Specifically, the OOK demodulation circuit further includes the following components:

a bit-direct digital frequency synthesizer for converting the error signal into frequency information;

a digital-to-analog converter (DAC) for converting the frequency information to an error clock signal.

Specifically, the OOK demodulation circuit further includes the following components,

the sign loop filter is used for filtering the error signal and sending the filtered error signal to the direct digital frequency synthesizer for processing;

the bit direct digital frequency synthesizer is used for converting the filtered error signal into frequency information.

Specifically, the OOK demodulation circuit further includes the following components:

the sigma pre-integration is used for carrying out integral smoothing processing on the error signal so as to generate a smoothed error signal;

the sign loop filter is used for filtering the smoothed error signal.

Specifically, the OOK demodulation circuit further includes the following components:

and the phase discriminator is used for carrying out error extraction on the bit synchronization result of the signal extracted by the first extraction circuit so as to obtain an error signal.

In the OOK demodulation circuit, the quadrature modulation circuit synthesizes a frequency generated by the local oscillator signal and a frequency of the error clock signal by complex conjugate multiplication.

Specifically, in the OOK demodulation circuit, the phase discriminator is:

E(r)＝S(YI(r-1/2))[S(YI(r))-S(YI(r-1))]+S(YQ(r-1/2))[sign(YQ(r))-S(YQ(r-1))]

wherein:

s (YI (r-1/2)) [ S (YI (r)) -S (YI (r-1)) ] and S (YQ (r-1/2)) [ sign (YQ (r)) -S (YQ (r-1)) ] are the accumulated sum of the instant branches of the I path and the Q path at the current moment; s represents the sign bit of the sampling point, the positive number is 1, and the negative number is 0; YI (r) and YQ (r) represent sample point values of the two paths of the r-th symbol I, Q at decision time, YI (r-1/2) and YQ (r-1/2) represent intermediate sample point values between the r-th and r-1-th symbols.

Specifically, the loop filter is a first-order ideal active proportional integral filter.

Specifically, the loop filter has an expression as follows:

y(n)＝y(n-1)+k1·x(n)-k2·x(n-1)

wherein: x (n) is the loop error amount at the current moment, x (n-1) is the loop error amount at the previous moment, y (n) is the loop filter output error amount required at the current moment, y (n-1) is the loop filter output error amount at the previous moment, and k1 and k2 are parameters of the loop filter.

The sampling clock of the ADC of the invention adopts LO + DDS to meet OOK signals of various code rates; in addition, under the same OOK communication code rate, the ADC model selection only needs the sampling rate of 2 times of the code rate Rb, so that the hardware power consumption and the design difficulty are reduced, and the hardware cost is reduced. Signals received by the FPGA part are based on twice sampling, so that the data processing amount is smaller, and the processing is relatively simpler.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic diagram of a conventional OOK demodulation circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of an OOK demodulation circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a quadrature modulation circuit provided by an embodiment of the present invention;

fig. 4 is a schematic diagram of a bit synchronization phase detection according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

Example one

Referring to fig. 2, the present embodiment discloses an OOK demodulation circuit, which includes: ADC, a first extraction circuit, a phase discriminator, a second extraction circuit and symbol hard decision.

The ADC is used for receiving, converting the modulated analog signal on the hardware into a digital signal and sending the digital signal to the digital demodulation part.

And the first extraction circuit is used for extracting 2 times of code rate of the output of the ADC, and the sampled data obtained after extraction is 2 times of the communication code rate. When the sampling rate of the ADC is 2 times of the communication code rate, the decimation module cannot work.

A second decimation circuit for performing 1/2 decimation on the output of the first decimation circuit. I.e. the decimation factor of the second decimation circuit is 2. The extracted data is the communication code rate and is sent to a symbol judgment module for symbol judgment.

The symbol hard decision circuit is used for carrying out decision output on the extracted data, and the obtained 0 and 1 of the decided data are the recovered demodulation baseband data.

The phase discriminator is used for carrying out error extraction on the bit synchronization result of the received data to obtain an error signal, and the bit synchronization can be adjusted according to the error.

The ADC model selection of the embodiment only needs the sampling rate of 2 times of the code rate Rb, so that the hardware power consumption and the design difficulty are reduced, and the hardware cost is reduced. Signals received by the FPGA part are based on twice sampling, so that the data processing amount is smaller, and the processing is relatively simpler.

Example two

Referring to fig. 2, the present embodiment discloses an OOK demodulation circuit, which includes: the Digital-to-Analog Converter comprises an ADC (Analog-to-Digital Converter), a first extraction circuit, a phase discriminator, a second extraction circuit, sign hard decision, sigma pre-integration, a sign loop filter, a Direct Digital Synthesizer (DDS), a Digital-to-Analog Converter (DAC), a quadrature modulation circuit and a Local Oscillator (LO).

The ADC is used for receiving, converting the modulated analog signal on the hardware into a digital signal and sending the digital signal to the digital demodulation part.

And the first extraction circuit is used for extracting 2 times of code rate of the output of the ADC, and the sampled data obtained after extraction is 2 times of the communication code rate. When the sampling rate of the ADC is 2 times of the communication code rate, the decimation module cannot work.

A second decimation circuit for performing 1/2 decimation on the output of the first decimation circuit. I.e. the decimation factor of the second decimation circuit is 2. The extracted data is the communication code rate and is sent to a symbol judgment module for symbol judgment.

The symbol hard decision circuit is used for carrying out decision output on the extracted data, and the obtained 0 and 1 of the decided data are the recovered demodulation baseband data.

The phase discriminator is used for carrying out error extraction on the bit synchronization result of the received data to obtain an error signal, and the bit synchronization can be adjusted according to the error.

Sigma pre-integration is used for carrying out integral smoothing processing on an error signal, and a coarse value in an error amount is removed, so that a compensated error value is more accurate.

The sign loop filter is used for filtering the error signal, so that the controlled error signal is smoother.

The bit DDS is used for synthesizing an error signal provided by a loop filter and converting the error signal into frequency information, the frequency of a digital signal is converted into an electric signal through a DAC (digital-to-analog converter) on hardware, a Local Oscillator (LO) clock and an error clock sent by the DAC are synthesized through a quadrature modulation chip, the synthesized signal is sent to the ADC as a sampling clock, and the sampling clock contains error control information of bit synchronization, so that the loop can be stable, and the sampling of the ADC can be guaranteed to be capable of acquiring the middle of a communication data chip each time.

The sampling clock of the ADC of this embodiment adopts LO + DDS to satisfy OOK signals of various code rates; in addition, under the same OOK communication code rate, the ADC model selection only needs the sampling rate of 2 times of the code rate Rb, so that the hardware power consumption and the design difficulty are reduced, and the hardware cost is reduced. Signals received by the FPGA part are based on twice sampling, so that the data processing amount is smaller, and the processing is relatively simpler.

Referring to fig. 3, the quadrature modulation circuit in this embodiment is a process of synthesizing the frequency generated by the local oscillator LO and the local statistical bit synchronization error information frequency by complex conjugate multiplication as described in fig. 3, and no image frequency component is generated by complex multiplication synthesis.

The phase detector used in this embodiment is as follows:

E(r)＝S(YI(r-1/2))[S(YI(r))-S(YI(r-1))]+S(YQ(r-1/2))[sign(YQ(r))-S(YQ(r-1))]

wherein:

s (YI (r-1/2)) [ S (YI (r)) -S (YI (r-1)) ] and S (YQ (r-1/2)) [ sign (YQ (r)) -S (YQ (r-1)) ] are the accumulated sum (pre-integrated value) of the instantaneous branches of the I path and the Q path at the current time. S denotes the sign bit of the sample point (positive number takes 1 and negative number takes 0).

YI (r) and YQ (r) represent sample point values of the two paths of the r-th symbol I, Q at decision time, YI (r-1/2) and YQ (r-1/2) represent intermediate sample point values between the r-th and r-1-th symbols.

As can be known from the phase detection formula, if the polarity of the r-th sampling point is opposite to that of the r-1 th sampling point, the sampling point r-1/2 should be zero or positive and negative jumps around zero; if the polarity of the r-th and r-1-th spots is the same, S (YI (r)) -S (YI (r-1)) ═ 0. Referring to fig. 4, from another perspective, if bit synchronization is achieved, the error signal e (r) is 0. If leading, its error is negative, and if lagging, its error is positive.

The loop filter of the present embodiment uses a first-order ideal active proportional-integral filter (forming a second-order loop), and the filter formula is as follows:

expressed by loop system parameters

Calculating T₁And T₂Comprises the following steps:

will T₁And T₂And substituting into a filter formula to obtain:

getSubstituting to obtain:

and (3) carrying out backward difference digital processing (bipolar variation method) to obtain an expression in a Z domain:

finishing to obtain:

namely:

epsilon: damping coefficient omega_n: natural angular frequency

T: integration time (phase discrimination frequency) K: loop gain

U_i(t): input signal U_o(t): output signal

Converting the above equation into digital domain processing, corresponding to the expression between input and output:

thus obtaining:

y(n)＝y(n-1)+k1·x(n)-k2·x(n-1)

wherein:x (n) is the loop error amount at the current moment, x (n-1) is the loop error amount at the previous moment, y (n) is the error amount required to be output by the loop filter at the current moment, and y (n-1) is the error amount output by the loop filter at the previous moment. k1 and k2 are loop filter parameters required to be provided during engineering programming.

In the calculation formulas for k1 and k 2: t is integral accumulation time (the reciprocal is the updating/control frequency, the relationship between the updating frequency and the loop bandwidth is that the loop bandwidth can be stabilized under the updating frequency of 1/10, and the loop bandwidth can reach 1/50 or 1/100); omega_nBeing the natural circular frequency of the loop filter,BL is the equivalent noise bandwidth of the loop, xi is the damping coefficient; the optimal value of the damping coefficient xi is usually 0.707, then

ω₀＝1.89B_L。

In summary, in the engineering implementation, according to different loop performance requirements (loop dynamic performance to be satisfied), only an appropriate loop bandwidth B needs to be selected_LThe integration time T (update frequency) yields the coefficients K1, K2 (the loop gain K is typically designed to be 1) of the desired filter. Therefore, when the FPGA implements two loops, only 3 loop parameters T, k1 and k2 need to be set as configurable module parameters.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.