阅读说明：本技术 一种数据压缩方法、装置及电子设备和存储介质 (Data compression method and device, electronic equipment and storage medium ) 是由 孙旭 于 2021-07-23 设计创作，主要内容包括：本申请公开了一种数据压缩方法、装置及一种电子设备和计算机可读存储介质,该方法包括：确定压缩函数和本轮压缩的各寄存器初值；基于所述各寄存器初值执行所述压缩函数,在执行过程中利用旁路进位加法器计算所述压缩函数中的加法运算,得到所述本轮压缩完成后各寄存器的值。由此可见,本申请提供的数据压缩方法,通过进位旁路加法器实现压缩函数中的加法运算,提高了压缩函数的计算效率。在硬件实现时达到缩短关键路径,提高算法整体性能的作用。(The application discloses a data compression method, a data compression device, an electronic device and a computer readable storage medium, wherein the method comprises the following steps: determining a compression function and initial values of registers of the current round of compression; and executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the executing process to obtain the value of each register after the current round of compression is finished. Therefore, the data compression method provided by the application realizes the addition operation in the compression function through the carry bypass adder, and improves the calculation efficiency of the compression function. The method achieves the effects of shortening the key path and improving the overall performance of the algorithm in the hardware implementation.)

1. A method of data compression, comprising:

determining a compression function and initial values of registers of the current round of compression;

and executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the executing process to obtain the value of each register after the current round of compression is finished.

2. The data compression method of claim 1, wherein the compression function is an SM3 algorithm compression function, and the bypass carry adder is a two-input one-output 32-bit bypass carry adder.

3. The method of claim 2, wherein the 32-bit bypass carry adder comprises 8 cascaded sets of 4-bit bypass carry adders.

4. The data compression method as claimed in claim 2, wherein the initial value of each register is the value of each register or the initial value of each register after the previous compression round is completed.

5. The data compression method of claim 4, further comprising:

and acquiring data to be compressed, and performing filling grouping and grouping expansion on the data to be compressed according to a preset rule to calculate message words required by the compression function and generate initial values of registers.

6. The method of claim 5, wherein the calculating the addition operation in the compression function by using the bypass carry adder to obtain the value of each register after the current round of compression is completed comprises:

and calculating the addition operation of the main key path in the compression function by using a bypass carry adder to obtain the value of the register corresponding to the main key path after the current compression is finished.

7. The data compression method according to claim 6, wherein the registers include a first register, a second register, a third register, a fourth register and a fifth register, and the register corresponding to the main critical path is the second register;

the calculating, by using a bypass carry adder, an addition operation of a main critical path in the compression function to obtain a value of a register corresponding to the main critical path after the current round of compression is completed includes:

calculating the sum of the initial value of the first register which is shifted left by 12 bits and the initial value of the second register by using a first bypass carry adder to obtain a first summation result;

calculating the sum of a preset constant which is shifted to the left by a preset bit number and the first summation result by using a second bypass carry adder to obtain a second summation result;

performing Boolean function processing on the initial value of the second register, the initial value of the third register and the initial value of the fourth register to obtain a Boolean function processing result;

calculating the sum of the Boolean function processing result and the initial value of the fifth register by using a third bypass carry adder to obtain a third summation result;

calculating the sum of the message word and the third summation result by using a fourth bypass carry adder to obtain a fourth summation result;

calculating the sum of the second summation result which is shifted to the left by 7 bits and the fourth summation result by using a fifth bypass carry adder to obtain a fifth summation result;

and performing replacement operation on the fifth summation result to obtain the value of the second register after the current round of compression is finished.

8. A data compression apparatus, comprising:

the determining module is used for determining a compression function and initial values of registers of the current round of compression;

and the execution module is used for executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the execution process to obtain the value of each register after the current round of compression is finished.

9. An electronic device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the data compression method as claimed in any one of claims 1 to 7 when executing said computer program.

10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the data compression method as claimed in any one of claims 1 to 7.

Technical Field

The present application relates to the field of data processing technologies, and in particular, to a data compression method and apparatus, an electronic device, and a computer-readable storage medium.

Background

With the development and wide application of information technology and computer technology, people have higher and higher reliability requirements on information data. In high-speed cryptographic chips, cryptographic hash algorithms (SM 3) are increasingly used for digital signature and verification, generation and verification of message authentication codes, and generation of random numbers in commercial cryptographic applications.

The SM3 algorithm is used as a cipher hash algorithm designed by our country, the length of an output message digest value is 256 bits, the length of a message packet is 512 bits, and the number of iterative compression times is 64. In the hardware implementation of the algorithm, data generally needs to be subjected to processes of message grouping, filling, expansion to generate message words, 64 rounds of function iterative compression and the like, wherein the function iterative compression process is complex in calculation, most in resource consumption and most in time consumption.

Therefore, how to improve the computational efficiency of the compression function is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The application aims to provide a data compression method, a data compression device, an electronic device and a computer readable storage medium, and the calculation efficiency of a compression function is improved.

To achieve the above object, the present application provides a data compression method, including:

determining a compression function and initial values of registers of the current round of compression;

and executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the executing process to obtain the value of each register after the current round of compression is finished.

The compression function is an SM3 algorithm compression function, and the bypass carry adder is a two-input one-output 32-bit bypass carry adder.

The 32-bit bypass carry adder comprises 8 groups of cascaded 4-bit bypass carry adders.

And the initial value of each register is the value of each register or the initial value of each register after the previous round of compression is finished.

Wherein, still include:

and acquiring data to be compressed, and performing filling grouping and grouping expansion on the data to be compressed according to a preset rule to calculate message words required by the compression function and generate initial values of registers.

Wherein, the calculating the addition operation in the compression function by using the bypass carry adder to obtain the value of each register after the current round of compression is completed includes:

and calculating the addition operation of the main key path in the compression function by using a bypass carry adder to obtain the value of the register corresponding to the main key path after the current compression is finished.

The register comprises a first register, a second register, a third register, a fourth register and a fifth register, and the register corresponding to the main critical path is the second register;

the calculating, by using a bypass carry adder, an addition operation of a main critical path in the compression function to obtain a value of a register corresponding to the main critical path after the current round of compression is completed includes:

calculating the sum of the initial value of the first register which is shifted left by 12 bits and the initial value of the second register by using a first bypass carry adder to obtain a first summation result;

calculating the sum of a preset constant which is shifted to the left by a preset bit number and the first summation result by using a second bypass carry adder to obtain a second summation result;

performing Boolean function processing on the initial value of the second register, the initial value of the third register and the initial value of the fourth register to obtain a Boolean function processing result;

calculating the sum of the Boolean function processing result and the initial value of the fifth register by using a third bypass carry adder to obtain a third summation result;

calculating the sum of the message word and the third summation result by using a fourth bypass carry adder to obtain a fourth summation result;

calculating the sum of the second summation result which is shifted to the left by 7 bits and the fourth summation result by using a fifth bypass carry adder to obtain a fifth summation result;

and performing replacement operation on the fifth summation result to obtain the value of the second register after the current round of compression is finished.

To achieve the above object, the present application provides a data compression apparatus comprising:

the determining module is used for determining a compression function and initial values of registers of the current round of compression;

and the execution module is used for executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the execution process to obtain the value of each register after the current round of compression is finished.

To achieve the above object, the present application provides an electronic device including:

a memory for storing a computer program;

a processor for implementing the steps of the data compression method as described above when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the data compression method as described above.

According to the scheme, the data compression method provided by the application comprises the following steps: determining a compression function and initial values of registers of the current round of compression; and executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the executing process to obtain the value of each register after the current round of compression is finished.

Therefore, the data compression method provided by the application realizes the addition operation in the compression function through a Carry bypass Adder (CSA), and improves the calculation efficiency of the compression function. The method achieves the effects of shortening the key path and improving the overall performance of the algorithm in the hardware implementation. The application also discloses a data compression device, an electronic device and a computer readable storage medium, which can also realize the technical effects.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

FIG. 1 is a flow chart illustrating a method of data compression according to an exemplary embodiment;

fig. 2 is a block diagram illustrating an SM3 algorithm in accordance with an exemplary embodiment;

FIG. 3 is a diagram illustrating a single-pass compression function in the SM3 algorithm, according to an exemplary embodiment;

FIG. 4 is a diagram illustrating a primary critical path computation process in accordance with an exemplary embodiment;

FIG. 5 is a block diagram illustrating a 32-bit bypass carry adder in accordance with an exemplary embodiment;

FIG. 6 is a block diagram illustrating a 4-bit bypass carry adder in accordance with an exemplary embodiment;

FIG. 7 is a block diagram illustrating a data compression apparatus in accordance with an exemplary embodiment;

FIG. 8 is a block diagram illustrating an electronic device in accordance with an exemplary embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In addition, in the embodiments of the present application, "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a specific order or a sequential order.

The embodiment of the application discloses a data compression method, which improves the calculation efficiency of a compression function.

Referring to fig. 1, a flow chart of a method of data compression is shown according to an exemplary embodiment, as shown in fig. 1, including:

s101: determining a compression function and initial values of registers of the current round of compression;

in this embodiment, the compression function may be specifically an SM3 algorithm compression function. For the SM3 algorithm, the specific interface signal specification is shown in table 1:

TABLE 1

As a possible implementation, the present embodiment further includes: and acquiring data to be compressed, and performing filling grouping and grouping expansion on the data to be compressed according to a preset rule to calculate message words required by the compression function and generate initial values of registers.

The framework diagram of the SM3 algorithm is shown in fig. 2, and in the specific implementation, the data to be compressed in the plaintext is first padded and grouped, that is, the input data to be compressed in the plaintext is padded according to the rule and divided into 512bit groups. After receiving valid data of the port, the valid data is simultaneously cached in 8 double-port RAMs with the same bit width of 32 bits and the depth of 64, and the cache addresses are marked as RAM _ A, RAM _ B, RAM _ C, RAM _ D, RAM _ E, RAM _ F, RAM _ G and RAM _ H. When a group of 512-bit Data is received, the Data _ in _ last signal is still not received, which indicates that the number of the Data group is unnecessary to 512 bits and does not need to be filled. When a group of 512bit Data is not received, namely Data _ in _ last exists, padding processing is needed at this time, firstly adding bit "1" to the end of the message, and then adding "0" until 512bit is reached.

Second, packet expansion is performed, i.e. the message word W required in the compression function is generated_jAnd W_j’And sent to the designated location. Since the message word needs to be used for calculation in the iterative calculation of the subsequent compression function, the message word needs to be generated in advance in order to reduce the operation time of the iterative compression. In the stuffing packet process, 512-bit data has been written into 16 groups of data according to 32-bit width, denoted as W₀-W₁₅The purpose of packet expansion is to computationally generate additional 116 sets of data.

W_jThe calculation formula of (2) is as follows: w_j＝P1(W_j-16⊕W_j-9⊕(W_j-3<<15))⊕(W_j-13<<7)⊕W_j-6, wherein the sets of data are read out simultaneously via the RAM, in particular W via RAM _ a_j-16 read out, RAM _ B will W_j-9 read out, RAM _ C will W_j-3 read out, RAM _ D will W_j13 read out, RAM _ E will W_j-6 read-out. The read data is subjected to corresponding cyclic shift and XOR operation according to a calculation formula of the algorithm, and then W is calculated_jAnd writes it into RAM.

W_j’The calculation formula of (2) is as follows: w_j’＝W_j⊕W_j+4, where W is transferred through RAM _ F_jRead out, RAM _ G will W_j+4And reading, carrying out bitwise exclusive-or operation according to a formula, and writing the calculation result back to the RAM _ G.

In the iterative compression process of the SM3 algorithm, the initial values of the registers include the values of the registers or the initial values of the registers after the previous compression round is completed, and the single-round compression function is shown in fig. 3, where the registers include A, B, C, D, E, F, G and H.

S102: and executing the compression function based on the initial values of the registers, and calculating addition operation in the compression function by using a bypass carry adder in the executing process to obtain the value of each register after the current round of compression is finished.

In the step, the compression function of the current round of compression is executed based on the initial value of each register, the bypass carry adder is used for calculating addition operation in the execution process, the idea of the carry bypass adder is to accelerate the propagation of a carry chain, and under a certain condition, the carry reaching the ith bit does not need to wait for the carry of the (i-1) th bit, so that the calculation efficiency is improved.

As a preferred embodiment, the calculating, by a bypass carry adder, an addition operation in the compression function to obtain values of the registers after the current round of compression is completed includes: and calculating the addition operation of the main key path in the compression function by using a bypass carry adder to obtain the value of the register corresponding to the main key path after the current compression is finished. It can be understood that the bypass carry adder is used for calculating the addition operation of the main critical path, which is beneficial to improving the calculation efficiency of the main critical path. For the SM3 algorithm, the computed path of register E' is the main critical path.

Further, the registers include a first register, a second register, a third register, a fourth register, and a fifth register, where the first register corresponds to a in fig. 3, the second register corresponds to E in fig. 3, the third register corresponds to F in fig. 3, the fourth register corresponds to G in fig. 3, the fifth register corresponds to H in fig. 3, and the register corresponding to the main critical path is the second register, i.e., E' in fig. 3. The calculation process of the main critical path is shown in fig. 4, and the formula is:

SS1＝((A<<12)+E+(Tj<<j))<<7

TT2＝GGj(E；F；G)+H+SS1+W_j

E’＝P0(TT2)

that is, the calculating, by using the bypass carry adder, an addition operation of a main critical path in the compression function to obtain a value of a register corresponding to the main critical path after the current round of compression is completed includes: calculating the sum of the initial value of the first register which is shifted left by 12 bits and the initial value of the second register by using a first bypass carry adder to obtain a first summation result; calculating the sum of a preset constant which is shifted to the left by a preset bit number and the first summation result by using a second bypass carry adder to obtain a second summation result; performing Boolean function processing on the initial value of the second register, the initial value of the third register and the initial value of the fourth register to obtain a Boolean function processing result; calculating the sum of the Boolean function processing result and the initial value of the fifth register by using a third bypass carry adder to obtain a third summation result; calculating the sum of the message word and the third summation result by using a fourth bypass carry adder to obtain a fourth summation result; calculating the sum of the second summation result which is shifted to the left by 7 bits and the fourth summation result by using a fifth bypass carry adder to obtain a fifth summation result; and performing replacement operation on the fifth summation result to obtain the value of the second register after the current round of compression is finished.

In the above formula, GGj () is a Boolean function, Tj is a predetermined constant, j is a predetermined number of bits, P0() is a permutation function, W_jIs a message word.

As can be seen from fig. 4, the first bypass carry adder, the second bypass carry adder, the third bypass carry adder, the fourth bypass carry adder, and the fifth bypass carry adder are 32-bit bypass carry adders with two inputs and one output. The calculation mode divides the calculation process of the main critical path into two groups of parallel calculation, namely a first bypass carry adder and a second bypass carry adder are one group, a third bypass carry adder and a fourth bypass carry adder are the other group, and the two groups of parallel calculation improve the calculation efficiency of the main critical path.

Fig. 5 is a structural diagram of a 32-bit bypass carry adder, and it can be seen that in the 32-bit bypass carry adder, the longest carry chain is c0- > c1- > c2- > … - > c32, that is, each bit full adder has a carry, and this path is also the longest critical path.

In the SM3 algorithm, all involved addition operations are 32-bit data addition operations, so that 32-bit-CSA needs to be realized, and 8 groups of 4-bit bypass carry adders can be used for cascade generation. Fig. 6 is a structural diagram of a 4-bit bypass carry adder, and it can be seen that compared with a conventional full adder, the 4-bit bypass carry adder shortens this longest path by adding bypass logic, which is composed of a 2-to-1 data selector, a 4 th carry, and a0 th carry and carry bypass signal. The bypass is A0^ B0& A1^ B1& A2^ B2& A3^ B3, when the bypass signal is 1, c4 ^ c0, the 4 th level bit does not need to wait for the calculation result of the previous 4-level full adder at the moment, and the value of c0 is directly assigned to c4, so that the calculation process is simplified, and the time sequence is optimized.

Therefore, the data compression method provided by the embodiment of the application realizes the addition operation in the compression function through the carry bypass adder, and improves the calculation efficiency of the compression function. The method achieves the effects of shortening the key path and improving the overall performance of the algorithm in the hardware implementation.

In the following, a data compression apparatus provided by an embodiment of the present application is introduced, and a data compression apparatus described below and a data compression method described above may be referred to each other.

Referring to fig. 7, a block diagram of a data compression apparatus according to an exemplary embodiment is shown, as shown in fig. 7, including:

a determining module 701, configured to determine a compression function and initial values of registers for the current round of compression;

and the execution module 702 is configured to execute the compression function based on the initial values of the registers, and calculate, by using a bypass carry adder, an addition operation in the compression function during the execution process to obtain the values of the registers after the current round of compression is completed.

Therefore, the data compression device provided by the embodiment of the application realizes the addition operation in the compression function through the carry bypass adder, and improves the calculation efficiency of the compression function. The method achieves the effects of shortening the key path and improving the overall performance of the algorithm in the hardware implementation.

On the basis of the above embodiment, as a preferred implementation manner, the compression function is an SM3 algorithm compression function, and the bypass carry adder is a two-input one-output 32-bit bypass carry adder.

On the basis of the above embodiment, as a preferred implementation, the 32-bit bypass carry adder includes 8 sets of cascaded 4-bit bypass carry adders.

In addition to the above embodiments, as a preferred implementation, the initial value of each register is the value of each register or the initial value of each register after the previous round of compression is completed.

On the basis of the above embodiment, as a preferred implementation, the method further includes:

and the generating module is used for acquiring data to be compressed, filling and grouping expansion are carried out on the data to be compressed according to a preset rule so as to calculate message words required by the compression function, and initial values of registers are generated.

Based on the foregoing embodiment, as a preferred implementation manner, the executing module 702 is specifically a module that executes the compression function based on the initial values of the registers, and calculates an addition operation of a main critical path in the compression function by using a bypass carry adder during the execution process to obtain a value of a register corresponding to the main critical path after the current round of compression is completed.

On the basis of the foregoing embodiment, as a preferred implementation manner, the register includes a first register, a second register, a third register, a fourth register, and a fifth register, and the register corresponding to the main critical path is the second register;

the execution module 702 includes:

the first summing unit is used for calculating the sum of the initial value of the first register after being shifted left by 12 bits and the initial value of the second register by using a first bypass carry adder to obtain a first summing result;

the second summation unit is used for calculating the sum of a preset constant which is shifted left by a preset bit number and the first summation result by using a second bypass carry adder to obtain a second summation result;

the processing unit is used for performing Boolean function processing on the initial value of the second register, the initial value of the third register and the initial value of the fourth register to obtain a Boolean function processing result;

the third summing unit is used for calculating the sum of the Boolean function processing result and the initial value of the fifth register by using a third bypass carry adder to obtain a third summing result;

a fourth summing unit, configured to calculate a sum of the message word and the third summing result by using a fourth bypass carry adder, so as to obtain a fourth summing result;

a fifth summing unit, configured to calculate, by using a fifth bypass carry adder, a sum of the second summation result shifted left by 7 bits and the fourth summation result, so as to obtain a fifth summation result;

and the replacement unit is used for performing replacement operation on the fifth summation result to obtain the value of the second register after the current round of compression is finished.

With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.

Based on the hardware implementation of the program module, and in order to implement the method according to the embodiment of the present application, an embodiment of the present application further provides an electronic device, and fig. 8 is a structural diagram of an electronic device according to an exemplary embodiment, as shown in fig. 8, the electronic device includes:

a communication interface 1 capable of information interaction with other devices such as network devices and the like;

and the processor 2 is connected with the communication interface 1 to realize information interaction with other equipment, and is used for executing the data compression method provided by one or more technical schemes when running a computer program. And the computer program is stored on the memory 3.

In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For the sake of clarity, however, the various buses are labeled as bus system 4 in fig. 8.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 2 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the above embodiment of the present application may be applied to the processor 2, or implemented by the processor 2. The processor 2 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 2. The processor 2 described above may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 3, and the processor 2 reads the program in the memory 3 and in combination with its hardware performs the steps of the aforementioned method.

When the processor 2 executes the program, the corresponding processes in the methods according to the embodiments of the present application are realized, and for brevity, are not described herein again.

In an exemplary embodiment, the present application further provides a storage medium, i.e. a computer storage medium, specifically a computer readable storage medium, for example, including a memory 3 storing a computer program, which can be executed by a processor 2 to implement the steps of the foregoing method. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.

Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling an electronic device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.