阅读说明：本技术 一种可控电阻电路 (Controllable resistance circuit ) 是由 李旋 于 2021-07-15 设计创作，主要内容包括：本申请涉及一种可控电阻电路,包括：控制信号生成模块,包括第一晶体管和第一电阻,以及分别于所述第一晶体管和所述第一电阻耦合的电流镜所述控制信号生成模块配置为至少基于所述第一电阻产生使所述第一晶体管工作在深线性区的偏置信号；以及电阻调控模块,包括一个或多个并联的第二晶体管,所述电阻调控模块耦合至所述控制信号生成模块,配置为基于所述第一晶体管的偏置信号对所述第二晶体管进行控制以使所述第二晶体管同样工作在深线性区域,从而控制所述第二晶体管的导通电阻仅与多数第一电阻和所述电流镜的镜像系数相关；其中所述第一晶体管和第二晶体管尺寸相同,制造工艺相同。本申请进一步包括一种控制电路中电阻的方法和一种电子设备。(The application relates to a controllable resistance circuit, comprising: a control signal generation module comprising a first transistor and a first resistor, and a current mirror coupled to the first transistor and the first resistor, respectively, the control signal generation module configured to generate a bias signal to operate the first transistor in a deep linear region based on at least the first resistor; and a resistance regulation module comprising one or more second transistors connected in parallel, the resistance regulation module being coupled to the control signal generation module and configured to control the second transistors based on the bias signal of the first transistor so that the second transistors also operate in a deep linear region, thereby controlling the on-resistance of the second transistors to be related only to the majority of the first resistors and the mirror image coefficients of the current mirror; the first transistor and the second transistor have the same size and the same manufacturing process. The present application further includes a method of controlling a resistance in a circuit and an electronic device.)

1. A controllable resistance circuit comprising:

a control signal generation module comprising a first transistor and a first resistor, and a current mirror coupled to the first transistor and the first resistor, respectively, the control signal generation module configured to generate a bias signal for operating the first transistor in a deep linear region based on at least the first resistor; and

a resistance regulation module including one or more second transistors connected in parallel, the resistance regulation module being coupled to the control signal generation module and configured to control the second transistors based on the bias signal of the first transistor so that the second transistors also operate in a deep linear region, thereby controlling the on-resistance of the second transistors to be related only to the majority of the first resistors and the mirror image coefficients of the current mirror;

the first transistor and the second transistor have the same size and the same manufacturing process.

2. The controllable resistance circuit of claim 1, wherein the current mirror comprises:

a first current source having one end coupled to a power source and the other end grounded through the first resistor;

a second current source having one end coupled to a power source and the other end coupled to the first end of the first transistor, wherein the current generated by the second current source is N times the current generated by the first current source, N is a mirror coefficient of a current mirror and is an integer greater than 1;

the control signal generation module further includes:

an operational amplifier having a first input coupled to a first terminal of the first transistor, a second input coupled to a node between the first current source and the first resistor, an output coupled to a control terminal of the first transistor, and a second terminal of the first transistor coupled to ground.

3. The controllable resistance circuit of claim 2, wherein the control terminal of the first transistor is coupled to the control terminal of the second transistor.

4. A controllable resistance circuit as claimed in claim 2, wherein

The control signal generation module further includes a first voltage-dividing resistor and a second voltage-dividing resistor serially arranged between the first terminal of the first transistor and a ground level;

the resistance adjustment module further comprises an adder having a first input coupled to the control terminal of the first transistor, a second input coupled to a node between the first and second divider resistors and configured to receive an inverse of a signal at the node, and an output coupled to the control terminal of the second transistor.

5. A controllable resistance circuit as claimed in claim 4, wherein

The resistance adjustment module further comprises a third voltage dividing resistor and a fourth voltage dividing resistor coupled in series between the first terminal and the second terminal of the second transistor, a node between the third voltage dividing resistor and the fourth voltage dividing resistor being coupled to a body terminal of the second transistor;

the adder also includes a third input coupled to a body terminal of the second transistor.

6. A controllable resistance circuit as claimed in claim 2, wherein the second current source is a controllable current source comprising a plurality of controllable current cells in parallel mirroring the first current source current.

7. A method of controlling a resistance in a circuit, comprising:

generating an input signal of an operational amplifier by using a current mirror consisting of a first resistor and a current source;

determining signals of a first end and a control end of a first transistor by using an operational amplifier, so that the transistor to be tested works in a deep linear region;

and taking the control signal of the tested transistor as the control signal of a second transistor, and enabling the second transistor to work in a deep linear region, so that the on-resistance of the second transistor is only related to the mirror image proportion of the first resistor and the current mirror.

8. An electronic device comprising a controllable resistance circuit as claimed in any one of claims 1-6.

Technical Field

The present invention relates to a resistor circuit, and more particularly, to a controllable resistor circuit.

Background

In many applications, a precise variable resistance resistor needs to be realized, and in high frequency applications, it is particularly desirable that the parasitic capacitance of the variable resistor is as small as possible. The prior art methods for implementing variable resistance resistors typically employ an array of switched resistors, or metal-oxide-semiconductor field effect transistors (MOSFETs) operating in the linear region.

Fig. 1 is a schematic diagram of a conventional switch resistor array type controllable resistor circuit, as shown in fig. 1. The controllable resistor circuit may include a plurality of identical switch resistor structures connected in parallel, for example, the switch resistor structure 104 may include a resistor 101, which is an on-chip resistor connected in series with a transistor, for example, an NMOS transistor 102, and has a resistance value of R; the NMOS transistor 102, acting as a switch, determines whether the switch resistor structure 104 is operating. The control terminal 103 controls the switch 102 to be switched on or off.

Another resistive structure may include a transistor such as NMOS transistor 105. Transistor 105 is the same size and fabricated transistor as transistor 102. The control terminal 106 controls 105 to be turned on or off. The capacitor 107 is a parasitic capacitor across the drain and the source of the NMOS transistor 105. The capacitor 108 is the parasitic capacitance from the drain of the NMOS transistor 105 to the substrate (typically ground). The capacitor 109 is a parasitic capacitor across the drain and gate of the NMOS transistor 105. The resistor 1010 is an on-chip resistor connected in series with the NMOS transistor 105 and has a resistance of R. Ports 1011 and 1012 are input/output terminals of the array of controlled resistance resistors. Fig. 1 is comprised of a plurality of switched resistor structures 104 connected in parallel. The resistance across 1011 and 1012 equals:

wherein, R is the resistance of the resistors 101 and 1010 in FIG. 1; r is_onThe on-resistance of NMOS transistors such as NMOS transistor 102 and NMOS transistor 105 during conduction, and M is the number of parallel resistor structures included in the array in the controllable resistor circuit.

R_totalAnd R and R_onIn correlation, R can be relatively accurate as a resistive device, and R_onIs changed along with the control voltage of the control terminal 103, the production process of the transistor and the temperature change of the application environment, thereby easily influencing the total on-resistance value R of the controllable resistance circuit_total. If desired R_totalPrecision, then r is required_onFar less than R, the ratio of the width to the channel length of the NMOS transistor, such as NMOS 105 and NMOS 102, needs to be as large as possible under a suitable control voltage (certain semiconductor process, the minimum channel length of NMOS is certain, and the width needs to be as large as possible). However, the larger the width of the MOSFET, the larger the parasitic capacitance must be (i.e., the larger the parasitic capacitances 107, 108, 109 in the figure). Excessive parasitic capacitance is not suitable for high-speed circuit portions in practical applications, especially in high-frequency system applications (e.g., radio frequency systems, high-speed wired transmission systems, optical communication systems).

Fig. 2 is a schematic diagram of a conventional MOSFET structure operating in a deep linear region, as shown in fig. 2. The voltage of the control end of the NMOS is VG, the voltage of the drain end of the NMOS is VD, the grounding voltage of the source end of the NMOS is VS-0, and the grounding voltage of the body end of the NMOS is VB-0. Working in deep linear region, requiring NMOS tubes of (V)_dsVD-VS) is much smaller than (Vgs-Vth).

At this time, the on-resistance of the NMOS transistor is:

wherein r is_dsIs NMOS tube on-resistance; v_dsIs the drain-source voltage difference, I_dsIs the drain-source current, K' is the process parameter, W is the NMOS tube width, L is the channel length, V_gsIs the difference of gate-source voltages, V_thIs the threshold voltage.

With smaller sized MOSFETs (smaller parasitic capacitance), the on-resistance of MOSFETs operating in deep linear regions needs to be controlled for their gate-source voltage (Vgs). In addition, a factor affecting the on-resistance of the MOSFET in the linear region is also the threshold voltage (Vth) of the MOSFET. However, the threshold voltage varies greatly with the manufacturing process and temperature, meaning that the on-resistance varies greatly with the manufacturing process and temperature, and is difficult to control accurately.

Therefore, there is a need for a controllable resistance circuit that is independent of the manufacturing process, the temperature of the application environment, and the gate voltage.

Disclosure of Invention

To the technical problem that exists among the prior art, the present application provides a controllable resistance circuit, includes: a control signal generation module comprising a first transistor and a first resistor, and a current mirror coupled to the first transistor and the first resistor, respectively, the control signal generation module configured to generate a bias signal for operating the first transistor in a deep linear region based on at least the first resistor; and a resistance regulation module comprising one or more second transistors connected in parallel, the resistance regulation module being coupled to the control signal generation module and configured to control the second transistors based on the bias signal of the first transistor so that the second transistors also operate in a deep linear region, thereby controlling the on-resistance of the second transistors to be related only to the majority of the first resistors and the mirror image coefficients of the current mirror; the first transistor and the second transistor have the same size and the same manufacturing process.

In particular, wherein the current mirror comprises: a first current source having one end coupled to a power source and the other end grounded through the first resistor; a second current source having one end coupled to a power source and the other end coupled to the first end of the first transistor, wherein the current generated by the second current source is N times the current generated by the first current source, N is a mirror coefficient of a current mirror and is an integer greater than 1; the control signal generation module further includes: an operational amplifier having a first input coupled to a first terminal of the first transistor, a second input coupled to a node between the first current source and the first resistor, an output coupled to a control terminal of the first transistor, and a second terminal of the first transistor coupled to ground.

In particular, wherein a control terminal of the first transistor is coupled to a control terminal of the second transistor.

In particular, the control signal generating module further comprises a first voltage dividing resistor and a second voltage dividing resistor which are serially arranged between the first end of the first transistor and the ground level; the resistance adjustment module further comprises an adder having a first input coupled to the control terminal of the first transistor, a second input coupled to a node between the first and second divider resistors and configured to receive an inverse of a signal at the node, and an output coupled to the control terminal of the second transistor.

In particular, wherein the resistance adjustment module further comprises a third voltage dividing resistance and a fourth voltage dividing resistance coupled in series between the first terminal and the second terminal of the second transistor, a node between the third voltage dividing resistance and the fourth voltage dividing resistance being coupled to a body terminal of the second transistor; the adder also includes a third input coupled to a body terminal of the second transistor.

In particular, wherein the second current source is a controllable current source comprising a plurality of parallel controllable current cells mirroring the first current source current.

The present application also includes a method of controlling a resistance in a circuit, comprising: generating an input signal of an operational amplifier by using a current mirror consisting of a first resistor and a current source; determining signals of a first end and a control end of a first transistor by using an operational amplifier, so that the transistor to be tested works in a deep linear region; and taking the control signal of the tested transistor as the control signal of a second transistor, and enabling the second transistor to work in a deep linear region, so that the on-resistance of the second transistor is only related to the mirror image proportion of the first resistor and the current mirror.

The present application also includes an electronic device comprising a controllable resistance circuit as described in any of the preceding.

Drawings

Preferred embodiments of the present application will now be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a conventional switched resistor array type controllable resistor circuit;

FIG. 2 is a schematic diagram of a prior art MOSFET structure operating in a deep linear region;

FIG. 3 is a schematic diagram of a variable resistor circuit with a precisely controllable resistance value according to one embodiment of the present application;

FIG. 4 is a schematic diagram of a controllable proportional current mirror circuit according to an embodiment of the present application; and

FIG. 5 is a schematic diagram of a variable resistor circuit with a precisely controllable resistance according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.

The transistor referred to in the present application may be a MOS transistor or a bipolar transistor. When the transistor is a MOS transistor, the transistor can be NMOS or PMOS. The first terminal of the MOS transistor related to the present application may be a source or a drain, the second terminal may be a drain or a source, and the control terminal may be a gate. When the transistor in this application is a bipolar transistor, the control terminal may be a base, and the first terminal or the second terminal may be a collector or an emitter.

The following description will be given taking a MOS transistor as an example.

The application provides a controllable resistance circuit, includes:

the control signal generation module comprises a first transistor and a first resistor, and is configured to generate a bias signal for enabling the first transistor to work in a deep linear region at least based on the first resistor.

And the resistance regulation and control module comprises one or more second transistors connected in parallel, is coupled to the control signal generation module and is configured to control the second transistors based on the bias signals of the first transistors so that the second transistors also work in a deep linear region, thereby controlling the second transistors to be connected with the on-resistance.

Wherein the control signal generation module further comprises:

a current source module configured to generate a first current signal I₀And a second current signal I₁Wherein the first current signal I₀And a second current signal I₁Proportionally, the proportionality coefficient is N, i.e., I1 ═ N × I0. In some embodiments, the current source module may be implemented by a controllable ratio current mirror circuit.

A voltage generation module comprising a first transistor, the voltage generation module coupled to the current source module configured to generate a control voltage based on the first and second current signals.

The controllable resistance circuit described above may be implemented in a variety of ways, as will be exemplified below. The related transistor is an NMOS, for example, and the first terminal is a drain terminal and the second terminal is a source terminal. However, the present application is not limited thereto. In the present application, the first transistor and the second transistor may be transistors having the same size, or transistors having a relationship of multiple sizes. For convenience, the following description will be given taking transistors of the same size as an example.

In the present application, the transistor is in the deep linear region, for example, for an NMOS transistor, the gate-source voltage is much larger than the drain-source voltage, and much larger means more than 1 power larger than 10.

FIG. 3 is a schematic diagram of a variable resistor circuit with a precisely controllable resistance according to an embodiment of the present application, as shown in FIG. 3.

The left dotted frame portion of fig. 3 is a control signal generating module, and may include a first transistor 301 having a first terminal coupled to a second current source 305 (a variable current source, with a magnitude of I)₁) The second terminal and the body terminal are coupled to ground. Wherein the voltage at the control terminal of the first transistor 301 is V₃The first terminal voltage is V₂。

In some embodiments, the control signal generation module may further include:

an operational amplifier 302 with a gain of A has a first input terminal, e.g. a positive input terminal, coupled to a first terminal of the first transistor 301, and a second input terminal, e.g. a negative input terminal, coupled to a first current source 304 (a fixed current source, with a magnitude of I)₀) An output terminal coupled to the first transistor301 control terminal.

First resistor 303 (of size R)₀) Which is coupled between the first current source 305 and ground.

In some embodiments, the control signal generation module may further include: a first voltage dividing resistor 309 (of magnitude R) arranged in series between the second current source 305 and ground₁) And a second voltage-dividing resistor 3010 (of size R)₁') in which the reference voltage signal between the first voltage-dividing resistor 309 and the second voltage-dividing resistor 3010 is V₁. In some embodiments, R₁May be equal to R₁’。

The right dotted line of fig. 3 is a resistance regulation module, which may include a second transistor 3015 having a first terminal with a voltage V_DA second terminal and a body terminal thereof are grounded, and a control terminal is coupled to a control terminal of the first transistor 301. Wherein the voltage at the control terminal of the second transistor 3015 is V_G。

In some embodiments, the resistance adjustment module further includes an adder 3014, a first input terminal of the adder 3014 is coupled to the control terminal of the first transistor 301, and a second input terminal of the adder 3014 receives a reference voltage signal V between the resistor 309 and the resistor 3010₁And the output end of the adder 3014 is coupled to the control end of the second transistor 3015. The second input terminal of the adder 3014 multiplies the input signal by a negative 1 coefficient, that is, the adder functions to output V3 minus V1 as VG of the transistor 3015. In some embodiments, a plurality of second transistors (with control terminals coupled in common to 3015) may be connected in parallel for resistance regulation.

In the circuit of FIG. 3, the current source 304 has a current I₀Flows through the first resistor 303 to generate a voltage V₀. The operational amplifier 302 and the first transistor 301 together form a negative feedback loop. This negative feedback loop gain is very large (the operational amplifier gain a needs to be large enough) so that the voltages at the inputs of the operational amplifier 302 are very close to satisfy:

V₂≈V₀ (3)

can design I₀And R₀So that V₀And V₂Much less than V₃So that the first transistor 301 operates on a deep lineAnd (4) a zone of weakness. (e.g., design: I)₀＝10uA,R₀When the voltage is 5kOhm, then V₀50 mV; in addition, depending on the value of N and the size of MOS transistor 301, the feedback loop may stabilize V3 at, for example, 1.2V, with MOS transistor 301 in the deep linear region, and more generally, V₀Designed to be about several tens mV is a suitable value) of the resistances R of the first voltage-dividing resistor 309 and the second voltage-dividing resistor 3010 in the graph₁Large, the current flowing through the first resistor 309 and the second resistor 3010 can be considered to be small. At the same time, V is known through the partial pressure of the two₁＝0.5×V₂. From formula (3):

V₂＝I₁×r_ds1≈V₀＝I₀×R₀ (4)

wherein, because N is the proportionality coefficient of two current sources, r can be set according to requirements_ds1Is the on-resistance of the first transistor 301, r_ds1Also satisfy the formula simultaneously:

wherein Q is₁As the specification parameters of the first transistor 301, the following are satisfied:

where K' is a process parameter of the transistor 301, W is a width of the NMOS transistor 301, and L is a channel length of the transistor 301. In this embodiment, since the first transistor 301 and the second transistor 3015 have the same size, the specification parameters of the two transistors are the same.

The on-resistance of the NMOS transistor of the second transistor 3015 is:

the "approximately equal sign" in the formula (8) holds, and it is necessary that the second transistor 3015 operates in a deep linear region, i.e., V_DMuch less than (V)_G-V_th). Since the transistors 301 and 3015 have the same size and are manufactured by the same process, the specification parameters Q1 and Q2 are the same, and vth is also the same. Also, V1 is equal toTherefore, combining equation (6) and equation (8) shows that rds1 is equal to rds 2.

In recombination (4), the on-resistance of the second transistor 3015 is equal to:

the formula (9) shows that since R₀Is a fixed resistive element and can therefore be controlled by I₁And I₀The proportionality coefficient N of (1), the accurate control of the on-resistance r_ds2. According to one embodiment, control I₁And I₀The ratio of (c) can be achieved by the current mirror of fig. 4. R in the formula (9)₀The resistance type with small change along with the semiconductor process and the temperature on the chip can be adopted, and the resistance value is more accurate; in addition, a thin film resistor (thin film resistor) outside the chip can be adopted, and the common precision in the industry can reach an error of 1% to 0.1%.

In some embodiments, the resistor 309, the resistor 3010 and the adder 3014 are not necessary, and the voltage V at the control terminal of the transistor 301 may be directly connected to the control terminal₃Is electrically connected to the control terminal of the transistor 3015. Adding the resistor 309, the resistor 3010, and the adder 3014 can increase the accuracy of the resistor adjustment.

In some embodiments, the variable current source 305 may be implemented by a current mirror. Fig. 4 is a schematic diagram of a controllable proportional current mirror circuit according to an embodiment of the present application, as shown. The current source 401 is a dc current source, I0. Transistor 402 is a P-type metal-oxide-semiconductor field effect transistor (P-type MOSFET, also referred to as PMOS transistor). Transistor 403 is a PMOS transistor having the same size as transistor 402. Transistor 404 is a PMOS transistor having dimensions consistent with transistor 402. The switches 405 and 406 may be controlled to be turned on or off. Transistor 403, switch 405 and switch 406 together form a single controllable current unit 407. The plurality of controllable current units 407 together constitute a controllable current source 408. The controllable current source 408 has an output 409 outputting a current I1. The voltage at terminal 4010 is the control/first terminal voltage VX of transistor 402. The voltage at the terminal 4011 is the control terminal voltage of the transistor 403, the voltage value VY. The current between the second terminal and the first terminal of the transistor 403 is I2.

In fig. 4, current I0 of current source 401 flows through transistor 402, generating voltage VX at the control terminal of transistor 402. If the control switch 405 is turned on and the switch 406 is turned off, the voltage difference between the control terminal and the second terminal of the transistor 403 is equal to 0, the transistor 403 is turned off, and the current between the second terminal and the first terminal is 0; if the control switch 405 is turned off and 406 is turned on, the voltage of the control terminal and the second terminal of the transistor 403 is the same as that of the transistor 402, as long as both transistors operate in the saturation region, and as can be obtained from the related basic principle, the current between the second terminal and the first terminal of the transistor 403 is the same as the source-drain current I0 of the transistor 402, and the function of "current mirror" accurate copy is realized. The controllable current source 408 in fig. 4 is composed of a plurality of controllable current units 407, and the operation of N controllable current units 407 can be controlled by the above method, so that the generated current I1 is N × I0. Thereby, the functions required at 305 in fig. 3 are realized.

Of course, other known structures may be used to construct the current mirror circuit in the control signal generation module.

The present application has other embodiments. FIG. 5 is a schematic diagram of a variable resistor circuit with a precisely controllable resistance according to another embodiment of the present application, as shown. The same or similar parts in fig. 5 and fig. 3 are not repeated.

In the circuit shown in fig. 5, the resistance adjusting and controlling module is different from that shown in fig. 3. In the resistance regulation module, the voltage of the first end of the second transistor 5015 is V_DThe voltage at the second terminal is V_sAt a control terminal voltage of V_GBody end voltage of V_B。

The resistance regulation module further comprises:

third voltage dividing resistor 5021 (with size R)₂) And a fourth voltage dividing resistor 5020 (of size R)₂'), a first terminal of the third voltage dividing resistor 5021 is coupled to a first terminal of the second transistor 5015, a second terminal thereof is coupled to a first terminal of the fourth voltage dividing resistor 5020 and to a body terminal of the transistor 5015, and a second terminal of the fourth voltage dividing resistor 5020 is coupled to a second terminal of the second transistor 5015. In some embodiments, R₂＝R₂’。

An adder 5014 having a first input coupled to the control terminal of the first transistor 501 and a second input of the adder 5014 receiving the reference voltage signal V₁The third input terminal of the adder 5014 is coupled to the body terminal of the second transistor 5015 through the second terminal of the third voltage dividing resistor 5021, and the output terminal of the adder 5014 is coupled to the control terminal of the second transistor 5015.

The main differences between fig. 5 and fig. 3 are: the second and body terminals of the second transistor 5015 need not be grounded as in fig. 3. In FIG. 5 the second transistor 5015 is in the deep linear region, (VD-VS) is close to 0 and much smaller than (VG-VS). The bulk terminal voltage VB obtained by voltage division of the resistors 5020 and 5021 is approximately equal to the second terminal voltage VS and approximately equal to the first single voltage VD. VG output by the three-input analog adder is V3-V1+ VB. On-resistance r of the second transistor 5015 in fig. 5_ds3Can be marked as:

the transistor 5015 is a transistor having the same size and manufactured by the same manufacturing process as the transistor 501. Therefore, Q3 is the same as Q1, and Vth is also the same. In addition, V1 is equal toAnd since the potential VB at the body terminal of the transistor 5015 is substantially equal to the potential VS at the second terminal as described above, the voltage difference between the first terminal and the second terminal of the transistor 5015 is negligible. And thus may wait to equation (10). Combined formula (6)It can be seen that the on-resistance r of the transistor 5015_ds3And the on-resistance r of the transistor 501_ds1The same is true. Thus, formula (11) can be obtained. As can be seen from equation (11), the on-resistance of the transistor 5015 may be the first resistor R₀And the coefficient N is accurately controlled.

Compared with the prior art, the scheme of the application enables the on-resistance of the transistor to be independent of the property of the transistor, independent of the use environment such as temperature and independent of process errors. Therefore, when the transistor is used as a resistor, the on-resistance is more stable and reliable. Meanwhile, the size of a transistor applied in the circuit can be smaller, and parasitic capacitance is smaller. The scheme of the application is particularly suitable for system applications such as wireless radio frequency communication, high-speed wired communication, optical communication and the like.

The application also provides a method for controlling resistance between nodes in a circuit, comprising

The transistor working in a deep linear region is used as a switch resistor, in addition, a reference voltage is generated by generating a current mirror and a reference resistor, and the control end voltage of the transistor is generated by applying a feedback loop mode, so that the on-resistance of the transistor is only related to the mirror image proportionality coefficient of the reference resistor and the current mirror.

Specifically, the method may comprise:

the input signal of the operational amplifier is generated by a current mirror composed of a reference resistor and a current source.

And determining signals of the first end and the control end of the first transistor by using an operational amplifier, so that the tested transistor works in a deep linear region.

And taking the control signal of the transistor to be tested as the control signal of a second transistor, and enabling the second transistor to work in a deep linear region, so that the on-resistance of the second transistor is only related to the mirror image proportion of the reference resistor and the current mirror.

The application also relates to an electronic device comprising a controllable resistance circuit as described in any of the preceding.

The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.