阅读说明：本技术 动态调整偏压电流的通道运算放大器电路 (Channel operational amplifier circuit for dynamically adjusting bias current ) 是由 蔡水河 郭洲銘 于 2021-09-27 设计创作，主要内容包括：本发明公开了一种动态调整偏压电流的通道运算放大器电路,包括：输入级电路、第一晶体管、第二晶体管及辅助偏压电路。输入级电路分别耦接第一晶体管及第二晶体管的闸极。第一晶体管与第二晶体管串接于工作电压与接地端之间。输入级电路分别接收输入电压以及第一晶体管与第二晶体管之间的输出电压并分别输出第一闸极控制电压及第二闸极控制电压至第一晶体管及第二晶体管的闸极。辅助偏压电路耦接输入级电路,用以侦测输入电压及输出电压并选择性地输出辅助偏压至输入级电路。(The invention discloses a channel operational amplifier circuit for dynamically adjusting bias current, which comprises: the circuit comprises an input stage circuit, a first transistor, a second transistor and an auxiliary bias circuit. The input stage circuit is coupled to the gates of the first transistor and the second transistor respectively. The first transistor and the second transistor are connected in series between the working voltage and the grounding terminal. The input stage circuit respectively receives an input voltage and an output voltage between the first transistor and the second transistor and respectively outputs a first gate control voltage and a second gate control voltage to gates of the first transistor and the second transistor. The auxiliary bias circuit is coupled to the input stage circuit for detecting the input voltage and the output voltage and selectively outputting an auxiliary bias to the input stage circuit.)

1. A channel operational amplifier circuit for dynamically adjusting bias current, comprising:

the output stage circuit comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are connected between working voltage and a grounding terminal in series;

an input stage circuit, coupled to the gate of the first transistor and the gate of the second transistor, for receiving an input voltage and an output voltage between the first transistor and the second transistor, and outputting a first gate control voltage and a second gate control voltage to the gates of the first transistor and the second transistor; and

an auxiliary bias circuit coupled to the input stage circuit and the output stage circuit, respectively, for detecting the input voltage and the output voltage and selectively outputting an auxiliary bias to the input stage circuit;

when the difference between the output voltage and the target output voltage exceeds 1V, the auxiliary bias circuit outputs the auxiliary bias to the input stage circuit, thereby increasing the bias current and shortening the settling time required by charging/discharging.

2. The circuit of claim 1, wherein the auxiliary bias circuit comprises:

a comparator for receiving the input voltage and the output voltage and generating a comparison result of the input voltage and the output voltage;

a control unit coupled to the comparator for generating a control signal according to the comparison result; and

the bias unit is coupled to the control unit and the input stage circuit and is used for selectively outputting the auxiliary bias to the input stage circuit according to the control signal.

3. The circuit of claim 1, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor.

4. The circuit of claim 1, wherein the input stage circuit comprises an operational amplifier, two input terminals of the operational amplifier respectively receive the input voltage and the output voltage, and two output terminals of the operational amplifier respectively output the first gate control voltage and the second gate control voltage to gates of the first transistor and the second transistor.

5. The circuit of claim 1, wherein the input stage circuit comprises a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first auxiliary circuit and a second auxiliary circuit; the gate of the first N-type transistor is coupled to the input voltage; the gate of the second N-type transistor is coupled to the output voltage; the third N-type transistor is coupled between the first voltage and the ground terminal; the gate of the third N-type transistor is coupled to the first bias voltage; the first auxiliary circuit is coupled between the first voltage and the grounding terminal; one end of the first N-type transistor and one end of the second N-type transistor are coupled with the first voltage; the gate of the first P-type transistor is coupled to the input voltage; the gate of the second P-type transistor is coupled to the output voltage; the third P-type transistor is coupled between the working voltage and a second voltage; the second auxiliary circuit is coupled between the working voltage and the second voltage; the gate of the third P-type transistor is coupled to a second bias voltage; one end of the first P-type transistor and one end of the second P-type transistor are coupled with the second voltage.

6. The circuit of claim 5, wherein the first auxiliary circuit comprises a fourth N-type transistor and a gate of the fourth N-type transistor is coupled to the first auxiliary bias voltage.

7. The circuit of claim 5, wherein the second auxiliary circuit comprises a fourth P-type transistor and a gate of the fourth P-type transistor is coupled to a second auxiliary bias voltage.

Technical Field

The invention belongs to the technical field of amplifiers, and particularly relates to a channel operational amplifier circuit for dynamically adjusting bias current.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of a conventional channel operational amplifier (CHOP) circuit. As shown in fig. 1, the conventional channel operational amplifier circuit includes an Input stage circuit INS and an output stage circuit OS. The input stage circuit INS includes a differential operational amplifier OP. The output stage circuit OS includes a first transistor M1 and a second transistor M2. The differential operational amplifier OP has a positive input terminal receiving the input voltage VIN and a negative input terminal receiving the output voltage VOUT. The differential operational amplifier OP provides a first gate control voltage VP to the gate of the first transistor M1 at a first output terminal thereof and provides a second gate control voltage VN to the gate of the second transistor M2 at a second output terminal thereof. The first transistor M1 and the second transistor M2 are connected in series between the operating voltage AVDD and the ground GND. The junction between the first transistor M1 and the second transistor M2 has an output voltage VOUT.

Referring to fig. 2, fig. 2 is a schematic diagram of an embodiment of an input stage circuit of a conventional channel operational amplifier circuit. As shown in fig. 2, the input stage circuit of the conventional channel operational amplifier circuit includes a first N-type transistor MN 1-a third N-type transistor MN3 and a first P-type transistor MP 1-a third P-type transistor MP 3. The gate of the first N-type transistor MN1 is coupled to the input voltage VIN. The gate of the second N-type transistor MN2 is coupled to the output voltage VOUT. The gate of the third N-type transistor MN3 is coupled to the first bias voltage VBN. The third N-type transistor MN3 is coupled between the first voltage V1 and the ground GND. One end of the first N-type transistor MN1 and one end of the second N-type transistor MN2 are also coupled to the first voltage V1. The gate of the first P-type transistor MP1 is coupled to the input voltage VIN. The gate of the second P-type transistor MP2 is coupled to the output voltage VOUT. The gate of the third P-type transistor MP3 is coupled to the second bias voltage VBP. The third P-type transistor MP3 is coupled between the working voltage AVDD and the second voltage V2. One end of the first P-type transistor MP1 and one end of the second P-type transistor MP2 are also coupled to the second voltage V2.

Conventionally, to obtain good stability, the input stage circuit of the conventional channel operational amplifier circuit is usually designed to have a Low bias current (Low bias current), i.e. to lower the first bias voltage VBN and the second bias voltage VBP. However, this also causes a long Settling time (Settling time) required for charge/discharge, and therefore, the problem is in need of improvement.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art.

Therefore, the invention provides a channel operational amplifier circuit for dynamically adjusting bias current, which has the advantages of micro-shaping a carrier tape and solving the problem of natural warping of the carrier tape.

The channel operational amplifier circuit for dynamically adjusting the bias current according to the embodiment of the invention comprises: the output stage circuit comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are connected between working voltage and a grounding terminal in series; an input stage circuit, coupled to the gate of the first transistor and the gate of the second transistor, for receiving an input voltage and an output voltage between the first transistor and the second transistor, and outputting a first gate control voltage and a second gate control voltage to the gates of the first transistor and the second transistor; and an auxiliary bias circuit coupled to the input stage circuit and the output stage circuit, respectively, for detecting the input voltage and the output voltage and selectively outputting an auxiliary bias to the input stage circuit.

According to an embodiment of the present invention, when the difference between the output voltage and the target output voltage exceeds 1V, the auxiliary bias circuit outputs the auxiliary bias to the input stage circuit, thereby increasing the bias current to shorten the settling time required for charging/discharging.

According to one embodiment of the present invention, the auxiliary bias circuit includes: a comparator for receiving the input voltage and the output voltage and generating a comparison result of the input voltage and the output voltage; a control unit coupled to the comparator for generating a control signal according to the comparison result; and a bias unit coupled to the control unit and the input stage circuit for selectively outputting the auxiliary bias to the input stage circuit according to the control signal.

According to an embodiment of the present invention, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

According to an embodiment of the present invention, the input stage circuit includes an operational amplifier, two input terminals of the operational amplifier respectively receive the input voltage and the output voltage, and two output terminals of the operational amplifier respectively output the first gate control voltage and the second gate control voltage to gates of the first transistor and the second transistor.

According to an embodiment of the present invention, the input stage circuit includes a first N-type transistor, a second N-type transistor, a third N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first auxiliary circuit and a second auxiliary circuit; the gate of the first N-type transistor is coupled to the input voltage; the gate of the second N-type transistor is coupled to the output voltage; the third N-type transistor is coupled between the first voltage and the ground terminal; the gate of the third N-type transistor is coupled to the first bias voltage; the first auxiliary circuit is coupled between the first voltage and the grounding terminal; one end of the first N-type transistor and one end of the second N-type transistor are coupled with the first voltage; the gate of the first P-type transistor is coupled to the input voltage; the gate of the second P-type transistor is coupled to the output voltage; the third P-type transistor is coupled between the working voltage and a second voltage; the second auxiliary circuit is coupled between the working voltage and the second voltage; the gate of the third P-type transistor is coupled to a second bias voltage; one end of the first P-type transistor and one end of the second P-type transistor are coupled with the second voltage.

According to an embodiment of the present invention, the first auxiliary circuit includes a fourth N-type transistor and a gate of the fourth N-type transistor is coupled to the first auxiliary bias voltage.

According to an embodiment of the present invention, the second auxiliary circuit includes a fourth P-type transistor and a gate of the fourth P-type transistor is coupled to a second auxiliary bias voltage.

The invention has the beneficial effect that the channel operational amplifier circuit for dynamically adjusting the bias current can dynamically adjust the bias current. When the difference between the output voltage and the target output voltage is detected to exceed 1V, the input stage circuit is designed to be low bias current for obtaining good stability, therefore, the channel operational amplifier circuit for dynamically adjusting the bias current immediately outputs additional auxiliary bias to the input stage circuit through the auxiliary bias circuit, thereby effectively increasing the magnitude of the bias current and shortening the stabilization time required by charging/discharging.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic diagram of a conventional channel operational amplifier circuit;

FIG. 2 is a schematic diagram of one embodiment of an input stage circuit of a conventional channel operational amplifier circuit;

FIG. 3 is a schematic diagram of a channel operational amplifier circuit for dynamically adjusting bias current in accordance with the present invention;

FIG. 4 is a schematic diagram of an input stage circuit in a channel operational amplifier circuit for dynamically adjusting bias current according to the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention. Furthermore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The channel operational amplifier circuit 3 for dynamically adjusting the bias current according to the embodiment of the present invention will be described in detail with reference to the drawings.

As shown in fig. 3 to 4, the channel operational amplifier circuit 3 for dynamically adjusting a bias current according to an embodiment of the present invention includes: an input stage circuit INS, an output stage circuit OS, and an auxiliary bias circuit 30.

The output stage circuit OS includes a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 are connected in series between the operating voltage AVDD and the ground GND, and the first transistor M1 is a P-type transistor and the second transistor M2 is an N-type transistor, but not limited thereto.

The input stage circuit INS is coupled to the gates of the first transistor M1 and the second transistor M2, respectively. The input stage circuit INS receives the input voltage VIN and the output voltage VOUT between the first transistor M1 and the second transistor M2, and outputs the first gate control voltage VP and the second gate control voltage VN to the gates of the first transistor M1 and the second transistor M2, respectively. The input stage circuit INS includes a differential operational amplifier OP, two input terminals of which respectively receive an input voltage VIN and an output voltage VOUT, and two output terminals of which respectively output a first gate control voltage VP and a second gate control voltage VN.

The auxiliary bias circuit 30 is coupled to the input stage circuit INS and the output stage circuit OS, respectively, for detecting the input voltage VIN and the output voltage VOUT and selectively outputting an auxiliary bias to the input stage circuit INS. For example, when the difference between the detected output voltage VOUT and the target output voltage exceeds 1V, it represents that the input stage circuit INS is designed to be a low bias current for good stability, and therefore, the auxiliary bias circuit 30 outputs an auxiliary bias to the input stage circuit INS, so as to increase the charge/discharge current and shorten the settling time required for charge/discharge.

In one embodiment, the auxiliary bias circuit 30 may include a comparator 301, a control unit 302 and a bias unit 303. The comparator 301 is coupled to the control unit 302 for generating a comparison result between the input voltage VIN and the output voltage VOUT to the control unit 302. The control unit 302 is coupled to the bias unit 303, and generates a control signal to the bias unit 303 according to the comparison result. The bias unit 303 is coupled to the input stage circuit INS for selectively outputting an auxiliary bias to the input stage circuit INS according to a control signal.

As shown in fig. 4, the input stage circuit 4 includes a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a first auxiliary circuit 40, and a second auxiliary circuit 42.

The gate of the first N-type transistor MN1 is coupled to the input voltage VIN. The gate of the second N-type transistor MN2 is coupled to the output voltage VOUT. The third N-type transistor MN3 is coupled between the first voltage V1 and the ground GND. The gate of the third N-type transistor MN3 is coupled to the first bias voltage VBN. The first auxiliary circuit 40 is coupled between the first voltage V1 and the ground GND. One end of the first N-type transistor MN1 and one end of the second N-type transistor MN2 are coupled to the first voltage V1.

In this embodiment, the first auxiliary circuit 40 includes a fourth N-type transistor MN3B, and the gate thereof is coupled to a first auxiliary bias voltage VBND, and the first auxiliary bias voltage VBND is provided by the auxiliary bias circuit 30 in fig. 3 when detecting that the difference between the output voltage VOUT and the target output voltage exceeds 1V, so as to compensate the input stage circuit 4 with low bias current, thereby increasing the charge/discharge current and shortening the settling time required for charge/discharge. The voltage value of the first auxiliary bias voltage VBND provided by the auxiliary bias circuit 30 is not particularly limited as long as the settling time can be shortened to a desired value.

The gate of the first P-type transistor MP1 is coupled to the input voltage VIN. The gate of the second P-type transistor MP2 is coupled to the output voltage VOUT. The third P-type transistor MP3 is coupled between the working voltage AVDD and the second voltage V2. The second auxiliary circuit 42 is coupled between the working voltage AVDD and the second voltage V2. The gate of the third P-type transistor MP3 is coupled to the second bias voltage VBP. One end of the first P-type transistor MP1 and one end of the second P-type transistor MP2 are coupled to the second voltage V2.

In this embodiment, the second auxiliary circuit 42 includes a fourth P-type transistor MP3B having a gate coupled to the second auxiliary bias voltage VBPD, and the second auxiliary bias voltage VBPD is provided by the auxiliary bias circuit 30 in fig. 3 when detecting that the difference between the output voltage VOUT and the target output voltage exceeds 1V, so as to compensate the input stage circuit 4 with low bias current, thereby increasing the charge/discharge current and shortening the settling time required for charge/discharge. The magnitude of the second auxiliary bias voltage VBPD provided by the auxiliary bias circuit 30 is not particularly limited, as long as the settling time can be reduced to a desired value.

Compared with the prior art, the channel operational amplifier circuit for dynamically adjusting the bias current can dynamically adjust the bias current. When the difference between the output voltage and the target output voltage is detected to exceed 1V, the input stage circuit is designed to be low bias current for obtaining good stability, therefore, the channel operational amplifier circuit for dynamically adjusting the bias current outputs additional auxiliary bias to the input stage circuit through the auxiliary bias circuit immediately, thereby effectively increasing the magnitude of the bias current and shortening the Settling time (Settling time) required by charging/discharging.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.