阅读说明：本技术 驱动电路、驱动方法和显示装置 (Driving circuit, driving method and display device ) 是由 王铸 闫政龙 石领 丁彦红 郑爽 于 2021-06-23 设计创作，主要内容包括：本发明提供一种驱动电路、驱动方法和显示装置。所述驱动电路包括第一时钟信号端、第二时钟信号端、输出端、第一节点控制电路、第二节点控制电路和输出电路；第一节点控制电路在起始电压信号的控制下,将第一电压信号写入所述第一节点,在第二时钟信号的控制下,将第二电压信号写入所述第一节点,在第二节点的电位的控制下,将第一电压信号写入第一节点；输出电路在第一节点的电位的控制下,控制输出端输出第一电压信号,在第三节点的电位的控制下,控制输出端输出第一时钟信号,并根据第三节点的电位控制输出端的电位。本发明能为采用IGZO(铟镓锌氧化物)晶体管和NMOS晶体管(N型金属-半导体-氧化物晶体管)的像素电路提供扫描信号。(The invention provides a driving circuit, a driving method and a display device. The driving circuit comprises a first clock signal end, a second clock signal end, an output end, a first node control circuit, a second node control circuit and an output circuit; the first node control circuit writes a first voltage signal into the first node under the control of the initial voltage signal, writes a second voltage signal into the first node under the control of the second clock signal, and writes the first voltage signal into the first node under the control of the potential of the second node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node, controls the output end to output a first clock signal under the control of the potential of the third node, and controls the potential of the output end according to the potential of the third node. The present invention can provide a scan signal to a pixel circuit using an IGZO (indium gallium zinc oxide) transistor and an NMOS transistor (N-type metal-semiconductor-oxide transistor).)

1. A driving circuit is characterized by comprising a first clock signal end, a second clock signal end, an output end, a first node control circuit, a second node control circuit and an output circuit;

the first node control circuit is respectively electrically connected with the starting voltage end, the first node, the second clock signal end, the second voltage end and the second node, and is used for writing a first voltage signal provided by the first voltage end into the first node under the control of the starting voltage signal provided by the starting voltage end, writing a second voltage signal provided by the second voltage end into the first node under the control of the second clock signal provided by the second clock signal end, and writing the first voltage signal into the first node under the control of the potential of the second node and maintaining the potential of the first node;

the second node control circuit is respectively electrically connected with the initial voltage end, the second node, the first voltage end and the second voltage end, and is used for writing a second voltage signal into the second node under the control of the initial voltage signal and writing a first voltage signal into the second node under the control of the potential of the first node;

the output circuit is respectively electrically connected with the first node, the third node, the first voltage end, the first clock signal end and the output end, and is used for controlling the output end to output a first voltage signal under the control of the potential of the first node, controlling the output end to output a first clock signal under the control of the potential of the third node, and controlling the potential of the output end according to the potential of the third node; the first clock signal terminal is used for providing the first clock signal.

2. The drive circuit according to claim 1, wherein the second node and the third node are the same node; or, the driving circuit comprises an on-off control circuit; the on-off control circuit is respectively electrically connected with a third voltage end, a second node and a third node and is used for controlling the communication between the second node and the third node under the control of a third voltage signal provided by the third voltage end.

3. The drive circuit according to claim 1, wherein the first node control circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor;

a control electrode of the first transistor is electrically connected with the initial voltage end, a first electrode of the first transistor is electrically connected with the first voltage end, and a second electrode of the first transistor is electrically connected with the first node;

a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with a second voltage end, and a second electrode of the second transistor is electrically connected with the first node;

a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the first node;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the first voltage end.

4. The drive circuit according to claim 1, wherein the second node control circuit includes a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is electrically connected with the starting voltage end, a first electrode of the fourth transistor is electrically connected with the second voltage end, and a second electrode of the fourth transistor is electrically connected with the second node;

a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

5. The drive circuit according to claim 1, wherein the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor;

a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the sixth transistor is electrically connected to the output terminal;

a control electrode of the seventh transistor is electrically connected with the third node, a first electrode of the seventh transistor is electrically connected with the output end, and a second electrode of the seventh transistor is electrically connected with the first clock signal end;

and the first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the output end.

6. The drive circuit according to claim 2, wherein the on-off control circuit includes an eighth transistor;

a control electrode of the eighth transistor is electrically connected to the third voltage terminal, a first electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the third node.

7. A driving method applied to the driving circuit according to any one of claims 1 to 6, wherein the driving period includes an input phase, an output phase and a reset phase; the driving method includes:

in the input stage, a first node control circuit controls to write a first voltage signal into a first node under the control of an initial voltage signal, a second node control circuit controls to write a second voltage signal into a second node under the control of the initial voltage signal, the first node control circuit controls to write a first voltage signal into the first node under the control of the potential of the second node, and an output circuit controls an output end to output a first clock signal under the control of the potential of a third node;

in the output stage, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first clock signal under the control of the electric potential of the third node;

in a reset stage, the first node control circuit controls to write a second voltage signal into the first node under the control of a second clock signal, and the second node control circuit controls to write a first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

8. The driving method according to claim 7, wherein the driving period further includes an output off hold phase provided after the reset phase; the output cutoff holding phase comprises a plurality of holding periods, the holding periods comprising a first holding period, a second holding period, and a third period; the driving method includes:

in a first holding time period and a second holding time period, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first voltage signal under the control of the electric potential of the first node;

in a third holding time period, the first node control circuit controls writing of the second voltage signal into the first node under the control of the second clock signal, and the second node control circuit controls writing of the first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

9. The driving method according to claim 7 or 8, wherein the second node and the third node are the same node;

or, the driving circuit comprises an on-off control circuit; the driving method further includes: the on-off control circuit controls the second node to be communicated with the third node under the control of a third voltage signal provided by the third voltage end.

10. A display device comprising a driving module, wherein the driving module comprises a plurality of stages of the driving circuit according to any one of claims 1 to 6.

11. The display device according to claim 10, further comprising a pixel circuit; the driving circuit is used for providing driving signals for the pixel circuit;

the pixel circuit comprises a light-emitting element, a driving circuit, a light-emitting control circuit, a compensation control circuit, an energy storage circuit, a data writing circuit, a reset circuit and a potential control circuit;

the light-emitting control circuit is respectively electrically connected with a light-emitting control line, a fourth voltage end, the first end of the driving circuit, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the fourth voltage end and the first end of the driving circuit and the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control line; the second pole of the light-emitting element is electrically connected with a fifth voltage end;

the compensation control circuit is respectively electrically connected with the scanning line, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a scanning signal provided by the scanning line;

the data writing circuit is respectively electrically connected with the scanning line, the data line and the first end of the driving circuit and is used for writing the data voltage on the data line into the first end of the driving circuit under the control of the scanning signal;

the reset circuit is respectively electrically connected with a reset control line, a reset voltage end and the second end of the drive circuit and is used for writing the reset voltage provided by the reset voltage end into the second end of the drive circuit under the control of a reset control signal provided by the reset control line;

the potential control circuit is respectively electrically connected with the reset control line, the fourth voltage end and the control end of the driving circuit, and is used for writing a fourth voltage signal into the control end of the driving circuit under the control of the reset control signal;

the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the second end of the driving circuit, and the energy storage circuit is used for storing electric energy.

12. The display device according to claim 11, wherein the light emission control circuit includes a first light emission control transistor and a second light emission control transistor; the compensation control circuit comprises a compensation control transistor, the data writing circuit comprises a data writing transistor, the reset circuit comprises a reset transistor, the driving circuit comprises a driving transistor, the potential control circuit comprises a potential control transistor, and the energy storage circuit comprises a storage capacitor; the light-emitting element is an organic light-emitting diode;

a control electrode of the first light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected with a fourth voltage end, and a second electrode of the first light-emitting control transistor is electrically connected with the first electrode of the driving transistor;

a control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the second light-emitting control transistor is electrically connected with a second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected with an anode of the organic light-emitting diode;

a control electrode of the compensation control transistor is electrically connected with the scanning line, a first electrode of the compensation control transistor is electrically connected with the control electrode of the driving transistor, and a second electrode of the compensation control transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the data writing transistor is electrically connected with the scanning line, a first electrode of the data writing transistor is electrically connected with the data line, and a second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor;

the control electrode of the reset transistor is electrically connected with the reset control line, the first electrode of the reset transistor is electrically connected with the reset voltage end, and the second electrode of the reset transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the potential control transistor is electrically connected with the reset control line, a first electrode of the potential control transistor is electrically connected with the fourth voltage end, and a second electrode of the potential control transistor is electrically connected with a control electrode of the driving transistor;

a first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor.

13. The display device according to claim 12, wherein the potential control transistor and the reset transistor are Indium Gallium Zinc Oxide (IGZO) transistors;

the driving transistor, the first light emission control transistor, the second light emission control transistor, the data writing transistor, and the compensation control transistor are all N-type metal-oxide-semiconductor transistors.

Technical Field

The invention relates to the technical field of display, in particular to a driving circuit, a driving method and a display device.

Background

The existing pixel circuit adopting an IGZO (indium gallium zinc oxide) transistor and an NMOS transistor (N-type metal-semiconductor-oxide transistor) is mainly applied to watch display driven by 1Hz, and the pixel circuit needs an N-type scanning signal for driving.

Disclosure of Invention

The invention mainly aims to provide a driving circuit, a driving method and a display device.

The embodiment of the invention provides a driving circuit, which comprises a first clock signal end, a second clock signal end, an output end, a first node control circuit, a second node control circuit and an output circuit, wherein the first clock signal end is connected with the first node control circuit;

the first node control circuit is respectively electrically connected with the starting voltage end, the first node, the second clock signal end, the second voltage end and the second node, and is used for writing a first voltage signal provided by the first voltage end into the first node under the control of the starting voltage signal provided by the starting voltage end, writing a second voltage signal provided by the second voltage end into the first node under the control of the second clock signal provided by the second clock signal end, and writing the first voltage signal into the first node under the control of the potential of the second node and maintaining the potential of the first node;

the second node control circuit is respectively electrically connected with the initial voltage end, the second node, the first voltage end and the second voltage end, and is used for writing a second voltage signal into the second node under the control of the initial voltage signal and writing a first voltage signal into the second node under the control of the potential of the first node;

the output circuit is respectively electrically connected with the first node, the third node, the first voltage end, the first clock signal end and the output end, and is used for controlling the output end to output a first voltage signal under the control of the potential of the first node, controlling the output end to output a first clock signal under the control of the potential of the third node, and controlling the potential of the output end according to the potential of the third node; the first clock signal terminal is used for providing the first clock signal.

Optionally, the second node and the third node are the same node; or, the driving circuit comprises an on-off control circuit; the on-off control circuit is respectively electrically connected with a third voltage end, a second node and a third node and is used for controlling the communication between the second node and the third node under the control of a third voltage signal provided by the third voltage end.

Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor;

a control electrode of the first transistor is electrically connected with the initial voltage end, a first electrode of the first transistor is electrically connected with the first voltage end, and a second electrode of the first transistor is electrically connected with the first node;

a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with a second voltage end, and a second electrode of the second transistor is electrically connected with the first node;

a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the first node;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the first voltage end.

Optionally, the second node control circuit includes a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is electrically connected with the starting voltage end, a first electrode of the fourth transistor is electrically connected with the second voltage end, and a second electrode of the fourth transistor is electrically connected with the second node;

a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

Optionally, the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor;

a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the sixth transistor is electrically connected to the output terminal;

a control electrode of the seventh transistor is electrically connected with the third node, a first electrode of the seventh transistor is electrically connected with the output end, and a second electrode of the seventh transistor is electrically connected with the first clock signal end;

and the first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the output end.

Optionally, the on-off control circuit includes an eighth transistor;

a control electrode of the eighth transistor is electrically connected to the third voltage terminal, a first electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the third node.

The invention also provides a driving method, which is applied to the driving circuit, wherein the driving cycle comprises an input stage, an output stage and a reset stage; the driving method includes:

in the input stage, a first node control circuit controls to write a first voltage signal into a first node under the control of an initial voltage signal, a second node control circuit controls to write a second voltage signal into a second node under the control of the initial voltage signal, the first node control circuit controls to write a first voltage signal into the first node under the control of the potential of the second node, and an output circuit controls an output end to output a first clock signal under the control of the potential of a third node;

in the output stage, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first clock signal under the control of the electric potential of the third node;

in a reset stage, the first node control circuit controls to write a second voltage signal into the first node under the control of a second clock signal, and the second node control circuit controls to write a first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

Optionally, the driving period further includes an output cut-off holding phase arranged after the reset phase; the output cutoff holding phase comprises a plurality of holding periods, the holding periods comprising a first holding period, a second holding period, and a third period; the driving method includes:

in a first holding time period and a second holding time period, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first voltage signal under the control of the electric potential of the first node;

in a third holding time period, the first node control circuit controls writing of the second voltage signal into the first node under the control of the second clock signal, and the second node control circuit controls writing of the first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

Optionally, the second node and the third node are the same node;

or, the driving circuit comprises an on-off control circuit; the driving method further includes: the on-off control circuit controls the second node to be communicated with the third node under the control of a third voltage signal provided by the third voltage end.

The invention also provides a display device which comprises a driving module, wherein the driving module comprises the multistage driving circuit.

Optionally, the display device according to the embodiment of the present invention further includes a pixel circuit; the driving circuit is used for providing driving signals for the pixel circuit;

the pixel circuit comprises a light-emitting element, a driving circuit, a light-emitting control circuit, a compensation control circuit, an energy storage circuit, a data writing circuit, a reset circuit and a potential control circuit;

the light-emitting control circuit is respectively electrically connected with a light-emitting control line, a fourth voltage end, the first end of the driving circuit, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the fourth voltage end and the first end of the driving circuit and the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control line; the second pole of the light-emitting element is electrically connected with a fifth voltage end;

the compensation control circuit is respectively electrically connected with the scanning line, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a scanning signal provided by the scanning line;

the data writing circuit is respectively electrically connected with the scanning line, the data line and the first end of the driving circuit and is used for writing the data voltage on the data line into the first end of the driving circuit under the control of the scanning signal;

the reset circuit is respectively electrically connected with a reset control line, a reset voltage end and the second end of the drive circuit and is used for writing the reset voltage provided by the reset voltage end into the second end of the drive circuit under the control of a reset control signal provided by the reset control line;

the potential control circuit is respectively electrically connected with the reset control line, the fourth voltage end and the control end of the driving circuit, and is used for writing a fourth voltage signal into the control end of the driving circuit under the control of the reset control signal;

the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the second end of the driving circuit, and the energy storage circuit is used for storing electric energy.

Optionally, the light emission control circuit includes a first light emission control transistor and a second light emission control transistor; the compensation control circuit comprises a compensation control transistor, the data writing circuit comprises a data writing transistor, the reset circuit comprises a reset transistor, the driving circuit comprises a driving transistor, the potential control circuit comprises a potential control transistor, and the energy storage circuit comprises a storage capacitor; the light-emitting element is an organic light-emitting diode;

a control electrode of the first light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected with a fourth voltage end, and a second electrode of the first light-emitting control transistor is electrically connected with the first electrode of the driving transistor;

a control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the second light-emitting control transistor is electrically connected with a second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected with an anode of the organic light-emitting diode;

a control electrode of the compensation control transistor is electrically connected with the scanning line, a first electrode of the compensation control transistor is electrically connected with the control electrode of the driving transistor, and a second electrode of the compensation control transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the data writing transistor is electrically connected with the scanning line, a first electrode of the data writing transistor is electrically connected with the data line, and a second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor;

the control electrode of the reset transistor is electrically connected with the reset control line, the first electrode of the reset transistor is electrically connected with the reset voltage end, and the second electrode of the reset transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the potential control transistor is electrically connected with the reset control line, a first electrode of the potential control transistor is electrically connected with the fourth voltage end, and a second electrode of the potential control transistor is electrically connected with a control electrode of the driving transistor;

a first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor.

Optionally, the potential control transistor and the reset transistor are Indium Gallium Zinc Oxide (IGZO) transistors;

the driving transistor, the first light emission control transistor, the second light emission control transistor, the data writing transistor, and the compensation control transistor are all N-type metal-oxide-semiconductor transistors.

The driving circuit, the driving method and the display device according to the embodiments of the present invention can provide a scan signal to a pixel circuit using an IGZO (indium gallium zinc oxide) transistor and an NMOS transistor (N-type metal-semiconductor-oxide transistor).

Drawings

Fig. 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a driving circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a driving circuit according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating operation of the driving circuit shown in FIG. 3 according to the present invention;

FIG. 5 is a diagram illustrating a driving module of a display device according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating operation of the driving module shown in FIG. 5;

FIG. 7 is a circuit diagram of an embodiment of a pixel circuit in a display device according to the invention;

fig. 8 is an operation timing diagram of the embodiment of the pixel circuit shown in fig. 7.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The driving circuit comprises a first node control circuit, a second node control circuit and an output circuit;

the first node control circuit is respectively electrically connected with the starting voltage end, the first node, the second clock signal end, the second voltage end and the second node, and is used for writing a first voltage signal provided by the first voltage end into the first node under the control of the starting voltage signal provided by the starting voltage end, writing a second voltage signal provided by the second voltage end into the first node under the control of the second clock signal provided by the second clock signal end, and writing the first voltage signal into the first node under the control of the potential of the second node and maintaining the potential of the first node;

the second node control circuit is respectively electrically connected with the initial voltage end, the second node, the first voltage end and the first voltage end, and is used for writing a second voltage signal into the second node under the control of the initial voltage signal and writing a first voltage signal into the first node under the control of the potential of the first node;

the output circuit is respectively electrically connected with the first node, the third node, the first voltage end, the first clock signal end and the output end, and is used for controlling the output end to output a first voltage signal under the control of the potential of the first node, controlling the output end to output a first clock signal under the control of the potential of the third node, and controlling the potential of the output end according to the potential of the third node; the first clock signal terminal is used for providing the first clock signal.

The driving circuit according to the embodiment of the present invention can provide a scanning signal to a pixel circuit using an IGZO (indium gallium zinc oxide) transistor and an NMOS transistor (N-type metal-semiconductor-oxide transistor).

In the embodiment of the present invention, the second node and the third node are the same node; or, the driving circuit comprises an on-off control circuit; the on-off control circuit is respectively electrically connected with a third voltage end, a second node and a third node and is used for controlling the communication between the second node and the third node under the control of a third voltage signal provided by the third voltage end.

As shown in fig. 1, the driving circuit according to the embodiment of the present invention includes a first clock signal terminal CK1, a second clock signal terminal CK2, a first node control circuit 11, a second node control circuit 12, and an output circuit 10;

the first node control circuit 11 is electrically connected to the start voltage terminal NSTV, the first voltage terminal V1, the first node N1, the second clock signal terminal CK2, the second voltage terminal V2, and the second node N2, respectively, and is configured to write a first voltage signal provided by the first voltage terminal V1 into the first node N1 under control of the start voltage signal provided by the start voltage terminal NSTV, write a second voltage signal provided by the second voltage terminal V2 into the first node N1 under control of the second clock signal provided by the second clock signal terminal CK2, and write the first voltage signal into the first node N1 under control of the potential of the second node N2, and maintain the potential of the first node N1;

the second node control circuit 12 is electrically connected to the start voltage terminal NSTV, the second node N2, the first node N1, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is configured to write a second voltage signal into the second node N2 under the control of the start voltage signal and write a first voltage signal into the second node N2 under the control of the potential of the first node N1;

the second node N2 is the same node as the third node;

the output circuit 10 is electrically connected to a first node N1, a second node N2, a first voltage terminal V1, a first clock signal terminal CK1 and an output terminal O1, respectively, and is configured to control the output terminal O1 to output a first voltage signal under the control of the potential of a first node N1, control the output terminal O1 to output a first clock signal under the control of the potential of a second node N2, and control the potential of the output terminal according to the potential of a second node N2; the first clock signal terminal CK1 is used for providing the first clock signal.

When the embodiment of the driving circuit shown in fig. 1 of the present invention works, the driving cycle may include an input stage, an output stage, a reset stage, and an output cut-off holding stage, which are sequentially set; the output cutoff holding phase comprises a plurality of holding periods, the holding periods comprising a first holding period, a second holding period, and a third holding period;

in the input stage, the first node control circuit 11 controls the writing of the first voltage signal into the first node N1 under the control of the start voltage signal, the second node control circuit 12 controls the writing of the second voltage signal into the second node N2 under the control of the start voltage signal, the first node control circuit 11 controls the writing of the first voltage signal into the first node N1 under the control of the potential of the second node N2, and the output circuit 10 controls the output terminal O1 to output the first clock signal under the control of the potential of the third node;

in the output stage, the first node control circuit 11 maintains the potential of the first node N1, the second node control circuit 12 maintains the potential of the second node N2, and the output circuit 10 controls the output terminal to output the first clock signal under the control of the potential of the third node;

in the reset phase, the first node control circuit 11 controls writing of the second voltage signal to the first node N1 under the control of the second clock signal, and the second node control circuit 12 writes the first voltage signal to the second node N2 under the control of the potential of the first node N1; the output circuit 10 controls the output terminal O1 to output a first voltage signal under the control of the potential of the first node N1;

in the first holding period and the second holding period, the first node control circuit 11 maintains the potential of the first node N1, the second node control circuit 12 maintains the potential of the second node N2, and the output circuit 10 controls the output terminal O1 to output the first voltage signal under the control of the first node N1;

in the third holding period, the first node control circuit 11 controls writing of the second voltage signal to the first node N1 under the control of the second clock signal, and the second node control circuit 12 writes the first voltage signal to the second node N2 under the control of the potential of the first node N1; the output circuit controls the output terminal to output the first voltage signal under the control of the potential of the first node N1.

As shown in fig. 2, on the basis of the embodiment of the driving circuit shown in fig. 1, the embodiment of the driving circuit further includes an on-off control circuit 20;

the on-off control circuit 20 is electrically connected to a third voltage terminal V3, a second node N2 and a third node N3, respectively, and is configured to control communication between the second node N2 and the third node N3 under control of a third voltage signal provided by the third voltage terminal V3.

In actual operation, the on-off control circuit 20 may include a normally-on transistor. When the transistor included in the on-off control circuit 20 is an n-type transistor, the third voltage terminal may be a high voltage terminal.

The driving circuit according to the embodiment of the present invention can stabilize the potential of N3 by adding the on-off control circuit 20.

Optionally, the first node control circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor;

a control electrode of the first transistor is electrically connected with the initial voltage end, a first electrode of the first transistor is electrically connected with the first voltage end, and a second electrode of the first transistor is electrically connected with the first node;

a control electrode of the second transistor is electrically connected with the second clock signal end, a first electrode of the second transistor is electrically connected with a second voltage end, and a second electrode of the second transistor is electrically connected with the first node;

a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the first node;

the first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with the first voltage end.

Optionally, the second node control circuit includes a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is electrically connected with the starting voltage end, a first electrode of the fourth transistor is electrically connected with the second voltage end, and a second electrode of the fourth transistor is electrically connected with the second node;

a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

Optionally, the output circuit includes a sixth transistor, a seventh transistor, and a second capacitor;

a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the sixth transistor is electrically connected to the output terminal;

a control electrode of the seventh transistor is electrically connected with the third node, a first electrode of the seventh transistor is electrically connected with the output end, and a second electrode of the seventh transistor is electrically connected with the first clock signal end;

and the first end of the second capacitor is electrically connected with the third node, and the second end of the second capacitor is electrically connected with the output end.

Optionally, the on-off control circuit includes an eighth transistor;

a control electrode of the eighth transistor is electrically connected to the third voltage terminal, a first electrode of the eighth transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the third node.

As shown in fig. 3, on the basis of the embodiment of the driving circuit shown in fig. 2, the first node control circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1;

a gate of the first transistor T1 is electrically connected to the start voltage terminal NSTV, a source of the first transistor T1 is electrically connected to the low voltage terminal, and a drain of the first transistor T1 is electrically connected to the first node N1; the low voltage end is used for providing a low voltage signal VGL;

a gate of the second transistor T2 is electrically connected to the second clock signal terminal CK2, a source of the second transistor T2 is electrically connected to a high voltage terminal, and a drain of the second transistor T2 is electrically connected to the first node N1; the high voltage end is used for providing a high voltage signal VGH;

a gate of the third transistor T3 is electrically connected to the second node N2, a source of the third transistor T3 is electrically connected to the low voltage terminal, and a drain of the third transistor T3 is electrically connected to the first node N1;

a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal;

the second node control circuit 12 includes a fourth transistor T4 and a fifth transistor T5;

a gate of the fourth transistor T4 is electrically connected to the start voltage terminal NSTV, a source of the fourth transistor T4 is electrically connected to the high voltage terminal, and a drain of the fourth transistor T4 is electrically connected to the second node N2;

a gate of the fifth transistor T5 is electrically connected to the first node N1, a source of the fifth transistor T5 is electrically connected to the low voltage terminal, and a drain of the fifth transistor T5 is electrically connected to the second node N2;

the output circuit 10 includes a sixth transistor T6, a seventh transistor T7, and a second capacitor C2;

a gate of the sixth transistor T6 is electrically connected to the first node N1, a source of the sixth transistor T6 is electrically connected to the low voltage terminal, and a drain of the sixth transistor T6 is electrically connected to the output terminal O1;

a gate of the seventh transistor T7 is electrically connected to the third node N3, a source of the seventh transistor T7 is electrically connected to the output terminal O1, and a drain of the seventh transistor T7 is electrically connected to the first clock signal terminal CK 1;

a first end of the second capacitor C2 is electrically connected with the third node N3, and a second end of the second capacitor C2 is electrically connected with the output terminal O1;

the on-off control circuit 20 comprises an eighth transistor T8;

the gate of the eighth transistor T8 is electrically connected to the high voltage terminal, the source of the eighth transistor T8 is electrically connected to the second node N2, and the drain of the eighth transistor T8 is electrically connected to the third node N3.

In the embodiment of the driving circuit shown in fig. 3, all transistors are NMOS transistors (N-type metal-oxide-semiconductor transistors).

In the embodiment of the drive circuit shown in fig. 3, T8 is provided to stabilize the potential of N3.

As shown in fig. 4, the driving cycle may include an input stage S1, an output stage S2, a reset stage S3, and an output off hold stage, which are sequentially arranged; the output cutoff holding phase includes a plurality of holding periods including a first holding period S41, a second holding period S42, and a third holding period S43;

in an input stage S1, NSTV provides a high voltage signal, CK2 provides a low voltage signal, CK1 provides a low voltage signal, T1 is turned on, T4 is turned on, T2 is turned off, the potential of N1 is a low voltage, T5 is turned off, the potential of N2 is a high voltage, T3 is turned on, N1 is connected to VGL, the potential of N3 is a high voltage, T6 is turned off, T7 is turned on, and O1 outputs a low voltage signal;

in the output stage S2, NSTV provides a low voltage signal, CK2 provides a low voltage signal, CK1 provides a high voltage signal, T1 is turned off, T2 is turned off, T4 is turned off, T5 is turned off, the potential of N1 is maintained at a low voltage, the potential of N2 is maintained at a high voltage, T8 is turned on, the potential of N3 is maintained at a high voltage, T6 is turned off, T7 is turned on, and O1 outputs a high voltage signal;

in a reset stage S3, NSTV provides a low voltage signal, CK2 provides a high voltage signal, CK1 provides a low voltage signal, T2 is turned on, the potential of N1 is high voltage, T5 is turned on, N2 is connected to VGL, T8 is turned on, the potential of N3 is low voltage, T6 is turned on, T7 is turned off, and O1 outputs a low voltage signal;

in a first holding period S41, NSTV provides a low voltage signal, CK2 provides a low voltage signal, CK1 provides a low voltage signal, T1 is turned off, T4 is turned off, T2 is turned off, the potential of N1 is maintained at a high voltage, the potential of N2 is maintained at a low voltage, the potential of N3 is a low voltage, T6 is turned on, T7 is turned off, and O1 outputs a low voltage signal;

in a second holding period S42, NSTV provides a low voltage signal, CK2 provides a low voltage signal, CK1 provides a high voltage signal, T1 is turned off, T4 is turned off, T2 is turned off, the potential of N1 is maintained at a high voltage, the potential of N2 is maintained at a low voltage, the potential of N3 is a low voltage, T6 is turned on, T7 is turned off, and O1 outputs a low voltage signal;

in a third holding period S43, NSTV provides a low voltage signal, CK2 provides a high voltage signal, CK1 provides a low voltage signal, T1 is off, T4 is off, T2 is on, the potential of N1 is a high voltage, T5 is on, N2 is turned on to VGL, the potential of N2 is a low voltage, T8 is on, the potential of N3 is a low voltage, T6 is on, T7 is off, and O1 outputs a low voltage signal.

The driving method provided by the embodiment of the invention is applied to the driving circuit, and the driving cycle comprises an input stage, an output stage and a reset stage; the driving method includes:

in the input stage, a first node control circuit controls to write a first voltage signal into a first node under the control of an initial voltage signal, a second node control circuit controls to write a second voltage signal into a second node under the control of the initial voltage signal, the first node control circuit controls to write a first voltage signal into the first node under the control of the potential of the second node, and an output circuit controls an output end to output a first clock signal under the control of the potential of a third node;

in the output stage, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first clock signal under the control of the electric potential of the third node;

in a reset stage, the first node control circuit controls to write a second voltage signal into the first node under the control of a second clock signal, and the second node control circuit controls to write a first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

In the driving method according to the embodiment of the present invention, in the output stage, the output circuit controls the output terminal to output the first clock signal, and in the reset stage, the output circuit controls the output terminal to output the first voltage signal.

In specific implementation, the driving period may further include an output cut-off holding phase disposed after the reset phase; the output cutoff holding phase comprises a plurality of holding periods, the holding periods comprising a first holding period, a second holding period, and a third holding period; the driving method includes:

in a first holding time period and a second holding time period, the first node control circuit maintains the electric potential of the first node, the second node control circuit maintains the electric potential of the second node, and the output circuit controls the output end to output a first voltage signal under the control of the electric potential of the first node;

in a third holding time period, the first node control circuit controls writing of the second voltage signal into the first node under the control of the second clock signal, and the second node control circuit controls writing of the first voltage signal into the second node under the control of the potential of the first node; the output circuit controls the output end to output a first voltage signal under the control of the potential of the first node.

In an embodiment of the present invention, the driving period may include an output off hold phase which is set after the reset phase, and the output circuit controls the output terminal to output the first voltage signal under the control of the potential of the first node at the output off hold node.

Optionally, the second node and the third node are the same node;

or, the driving circuit comprises an on-off control circuit; the driving method further includes: the on-off control circuit controls the second node to be communicated with the third node under the control of a third voltage signal provided by the third voltage end.

The display device comprises a driving module, wherein the driving module comprises a plurality of stages of driving circuits.

In an embodiment of the present invention, the driving circuit may be included in a driving module, the driving module includes a plurality of stages of driving circuits, a start voltage signal provided by a start voltage terminal of a first stage of driving circuit is a predetermined start voltage signal provided externally, and other start voltage terminals except the first stage of driving circuit are driving signal terminals of adjacent previous stage of driving circuits.

As shown in fig. 5, the driving module includes a first stage driving circuit P1 having a first clock signal terminal connected to a first clock signal K1, and a second stage driving circuit P1 having a second clock signal terminal connected to a second clock signal K2;

the first clock signal terminal of a second-stage driving circuit P2 included in the driving module is connected to a second clock signal K2, and the second clock signal terminal of the second-stage driving circuit P2 is connected to a third clock signal K3;

the first clock signal terminal of a third-stage driving circuit P3 included in the driving module is connected to a third clock signal K3, and the second clock signal terminal of the third-stage driving circuit P3 is connected to a first clock signal K1;

the driving module comprises a fourth stage driving circuit P4 with a first clock signal terminal connected to the first clock signal K1 and a second clock signal terminal connected to the second clock signal K2, wherein the fourth stage driving circuit P4 is provided with a second clock signal terminal connected to the second clock signal K2.

In fig. 5, an output terminal denoted by O1(1) is P1, an output terminal denoted by O1(2) is P2, an output terminal denoted by O1(3) is P3, and an output terminal denoted by O1(4) is P4.

In the display device according to the embodiment of the present invention, a first clock signal terminal of a 4n-3 th-level driving circuit included in the driving module is connected to a first clock signal K1, and a second clock signal terminal of the 4 n-3-level driving circuit is connected to a second clock signal K2;

the first clock signal end of a 4n-2 level driving circuit included in the driving module is connected to a second clock signal K2, and the second clock signal end of the 4n-2 level driving circuit is connected to a third clock signal K3;

the first clock signal terminal of the 4n-1 level driving circuit included in the driving module is connected to the third clock signal K3, and the second clock signal terminal of the 4n-1 level driving circuit P3 is connected to the first clock signal K1;

n is a positive integer.

As shown in fig. 6, a period of the first clock signal K1, a period of the second clock signal K2, and a period of the third clock signal K3 are all T, and a duty ratio of the first clock signal K1, a duty ratio of the second clock signal K2, and a duty ratio of the third clock signal K3 may be 1/3;

k2 is delayed by T/3 from K1, and K3 is delayed by T/3 from K2.

FIG. 6 is a simulation timing diagram of the operation of the embodiment of the driving module shown in FIG. 5.

In specific implementation, the display device according to the embodiment of the present invention further includes a pixel circuit; the driving circuit is used for providing driving signals for the pixel circuit;

the pixel circuit comprises a light-emitting element, a driving circuit, a light-emitting control circuit, a compensation control circuit, an energy storage circuit, a data writing circuit, a reset circuit and a potential control circuit;

the light-emitting control circuit is respectively electrically connected with a light-emitting control line, a fourth voltage end, the first end of the driving circuit, the second end of the driving circuit and the first pole of the light-emitting element, and is used for controlling the communication between the fourth voltage end and the first end of the driving circuit and the communication between the second end of the driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal provided by the light-emitting control line; the second pole of the light-emitting element is electrically connected with a fifth voltage end;

the compensation control circuit is respectively electrically connected with the scanning line, the control end of the driving circuit and the second end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a scanning signal provided by the scanning line;

the data writing circuit is respectively electrically connected with the scanning line, the data line and the first end of the driving circuit and is used for writing the data voltage on the data line into the first end of the driving circuit under the control of the scanning signal;

the reset circuit is respectively electrically connected with a reset control line, a reset voltage end and the second end of the drive circuit and is used for writing the reset voltage provided by the reset voltage end into the second end of the drive circuit under the control of a reset control signal provided by the reset control line;

the potential control circuit is respectively electrically connected with the reset control line, the fourth voltage end and the control end of the driving circuit, and is used for writing a fourth voltage signal into the control end of the driving circuit under the control of the reset control signal;

the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with the second end of the driving circuit, and the energy storage circuit is used for storing electric energy.

Optionally, the light emission control circuit includes a first light emission control transistor and a second light emission control transistor; the compensation control circuit comprises a compensation control transistor, the data writing circuit comprises a data writing transistor, the reset circuit comprises a reset transistor, the driving circuit comprises a driving transistor, the potential control circuit comprises a potential control transistor, and the energy storage circuit comprises a storage capacitor; the light-emitting element is an organic light-emitting diode;

a control electrode of the first light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected with a fourth voltage end, and a second electrode of the first light-emitting control transistor is electrically connected with the first electrode of the driving transistor;

a control electrode of the second light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the second light-emitting control transistor is electrically connected with a second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is electrically connected with an anode of the organic light-emitting diode;

a control electrode of the compensation control transistor is electrically connected with the scanning line, a first electrode of the compensation control transistor is electrically connected with the control electrode of the driving transistor, and a second electrode of the compensation control transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the data writing transistor is electrically connected with the scanning line, a first electrode of the data writing transistor is electrically connected with the data line, and a second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor;

the control electrode of the reset transistor is electrically connected with the reset control line, the first electrode of the reset transistor is electrically connected with the reset voltage end, and the second electrode of the reset transistor is electrically connected with the second electrode of the driving transistor;

a control electrode of the potential control transistor is electrically connected with the reset control line, a first electrode of the potential control transistor is electrically connected with the fourth voltage end, and a second electrode of the potential control transistor is electrically connected with a control electrode of the driving transistor;

a first terminal of the storage capacitor is electrically connected to the control electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second electrode of the driving transistor.

In the embodiment of the present invention, the potential control transistor and the reset transistor may be indium gallium zinc oxide IGZO transistors;

the driving transistor, the first light emission control transistor, the second light emission control transistor, the data writing transistor, and the compensation control transistor may be N-type metal-oxide-semiconductor transistors.

As shown in fig. 7, an embodiment of the pixel circuit includes a first light emission controlling transistor M5, a second light emission controlling transistor M6, a compensation controlling transistor T7, a reset transistor M1, a potential controlling transistor M2, a driving transistor M3, a data writing transistor M4, and a storage capacitor CST; the light-emitting element is an organic light-emitting diode (OLED);

the grid electrode of the M1 is electrically connected with a reset control line GateN _ n-1, the source electrode of the M1 is electrically connected with a reset voltage end, and the drain electrode of the M1 is electrically connected with the drain electrode of the T3; the reset voltage end is used for providing a reset voltage Vinit;

the gate of M2 is electrically connected with a reset control line GateN _ n-1, the source of M2 is electrically connected with a high level end VDD, and the drain of M2 is electrically connected with the gate of M3;

the grid electrode of the M4 is electrically connected with a scanning line GateN _ n, the source electrode of the M4 is connected with a data voltage Vdata, and the drain electrode of the M4 is electrically connected with the source electrode of the M3;

a gate of the M5 is electrically connected to the emission control line EM, a source of the M5 is electrically connected to the high level terminal VDD, and a drain of the M5 is electrically connected to a source of the M3;

the gate of the M6 is electrically connected with the emission control line EM, the source of the M6 is electrically connected with the drain of the M3, and the drain of the M6 is electrically connected with the anode of the OLED;

the grid electrode of the M7 is electrically connected with a scanning line GateN _ n, the source electrode of the M7 is electrically connected with the grid electrode of the T3, and the drain electrode of the M7 is electrically connected with the drain electrode of the T3;

the cathode of the OLED is electrically connected to the low level terminal VSS.

In the embodiment shown in fig. 7, M1 and M2 are IGZO thin film transistors, and M3, M4, M5, M6, and M7 are NMOS transistors (N-type metal-oxide-semiconductor transistors).

Fig. 8 is an operation timing diagram of the embodiment of the pixel circuit shown in fig. 7.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.