阅读说明：本技术 基于浮栅电荷泄漏的信息记录方法及装置 (Information recording method and device based on floating gate charge leakage ) 是由 刘林 原顺 于 2021-08-26 设计创作，主要内容包括：本发明实施例公开了基于浮栅电荷泄漏的信息记录方法及装置,应用于电子设备计时,所述设备包括由浮栅晶体管组成存储单元的存储器,方法包括以下步骤：响应于关闭电源指令或设备断电,对所述存储器中预设的存储单元进行编程操作,并进行第一ADC采样所述存储单元的电荷量,记为第一电荷量；电源开启后,对所述存储单元进行第二ADC采样所述存储单元的电荷量,记为第二电荷量；根据所述第一电荷量和所述第二电荷量,基于所述浮栅晶体管的电荷泄漏速度计算关闭电源操作和开启电源操作的时间间隔。本发明实施例能够在关闭电源时仍然可以记录信息如时间/温度等。(The embodiment of the invention discloses an information recording method and a device based on floating gate charge leakage, which are applied to electronic equipment timing, wherein the equipment comprises a memory with a storage unit consisting of floating gate transistors, and the method comprises the following steps: in response to a power-off instruction or power-off of equipment, performing programming operation on a preset storage unit in the memory, and sampling the charge quantity of the storage unit by using a first ADC (analog to digital converter) and recording as a first charge quantity; after the power supply is turned on, carrying out second ADC on the storage unit to sample the charge quantity of the storage unit, and recording the charge quantity as a second charge quantity; calculating a time interval between a power-off operation and a power-on operation based on a charge leakage speed of the floating gate transistor according to the first charge amount and the second charge amount. The embodiment of the invention can still record information such as time/temperature and the like when the power supply is turned off.)

1. An information recording method based on floating gate charge leakage is applied to electronic equipment timing, the equipment comprises a memory with a memory cell consisting of floating gate transistors, and the method is characterized by comprising the following steps:

in response to a power-off instruction or power-off of equipment, performing programming operation on a preset storage unit in the memory, and sampling the charge quantity of the storage unit by using a first ADC (analog to digital converter) and recording as a first charge quantity;

after the power supply is turned on, carrying out second ADC on the storage unit to sample the charge quantity of the storage unit, and recording the charge quantity as a second charge quantity;

calculating a time interval between a power-off operation and a power-on operation based on a charge leakage speed of the floating gate transistor according to the first charge amount and the second charge amount.

2. The floating gate charge leakage based information recording method according to claim 1, further comprising:

before programming operation, a floating gate transistor array is preset in the memory unit, the floating gate transistor array is formed by a plurality of transistors with floating gate structures, a grid electrode is shared, and the transistors in the same row are cascaded;

when programming operation is carried out, injecting charges from the drain electrode of the floating gate transistor array;

when the first ADC sampling and the second ADC sampling are carried out, ADC sampling is carried out from the source electrode of the transistor.

3. The floating gate charge leakage based information recording method according to claim 1, further comprising:

before programming operation, floating gate transistors with different floating gate thicknesses are preset in the memory unit, and charge leakage speeds corresponding to the different floating gate thicknesses are recorded;

and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation.

4. The floating gate charge leakage based information recording method according to claim 1, further comprising:

before programming operation, floating gate transistors with different gate structures are preset in the memory unit, and charge leakage speeds corresponding to the different gate structures are recorded;

and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation.

5. An information recording device based on floating gate charge leakage, which is applied to electronic equipment timing, is characterized by comprising:

a first memory having a memory cell composed of floating gate transistors;

the ADC sampling module is electrically connected with the first memory;

a processor;

a second memory storing a computer program;

the processor executes the computer program, implementing the method of claim 1.

6. The floating gate charge leakage-based information recording device according to claim 5, wherein the floating gate transistors constitute a floating gate transistor array, the floating gate transistor array is a plurality of floating gate structure transistors sharing one gate, and the transistors in the same row are cascaded;

the floating gate transistor comprises a first transistor and a second transistor, and floating gate thicknesses of the first transistor and the second transistor are different.

7. The floating gate charge leakage-based information recording device according to claim 5, wherein said floating gate transistor includes a third transistor and a fourth transistor, and a gate structure of said third transistor is different from a gate structure of said fourth transistor.

Technical Field

The present invention relates to an information recording method, and more particularly, to an information recording method and apparatus based on floating gate charge leakage.

Background

In a system, usually, a timer needs to be electrified, and the timer cannot record time information after the power supply is turned off. In some scenarios, the integrated circuit is unable to record any information if there is no external power source and the battery is depleted.

There is therefore a need for a method that can still record information such as time/temperature when the power is turned off, and that can provide a timing requirement with a certain accuracy after calibration.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an information recording method based on floating gate charge leakage, which can still record information such as time/temperature and the like when the power supply is turned off.

The invention also provides an information recording device based on floating gate charge leakage.

The information recording method based on floating gate charge leakage according to the embodiment of the first aspect of the invention is applied to electronic equipment timing, the equipment comprises a memory with a memory cell consisting of floating gate transistors, and the method comprises the following steps: in response to a power-off instruction or power-off of equipment, performing programming operation on a preset storage unit in the memory, and sampling the charge quantity of the storage unit by using a first ADC (analog to digital converter) and recording as a first charge quantity; after the power supply is turned on, carrying out second ADC on the storage unit to sample the charge quantity of the storage unit, and recording the charge quantity as a second charge quantity; calculating a time interval between a power-off operation and a power-on operation based on a charge leakage speed of the floating gate transistor according to the first charge amount and the second charge amount.

The information recording method based on floating gate charge leakage provided by the embodiment of the invention at least has the following beneficial effects: the information recording method based on floating gate charge leakage of the embodiment of the invention realizes that time information can be recorded when a power supply is turned off or no external power supply is available and a battery is exhausted by virtue of the charge leakage characteristic of the floating gate transistor.

According to some embodiments of the invention, the method further comprises: before programming operation, a floating gate transistor array is preset in the memory unit, the floating gate transistor array is formed by a plurality of transistors with floating gate structures, a grid electrode is shared, and the transistors in the same row are cascaded; when programming operation is carried out, injecting charges from the drain electrode of the floating gate transistor array; when the first ADC sampling and the second ADC sampling are carried out, ADC sampling is carried out from the source electrode of the transistor.

According to some embodiments of the invention, the method further comprises: before programming operation, floating gate transistors with different floating gate thicknesses are preset in the memory unit, and charge leakage speeds corresponding to the different floating gate thicknesses are recorded; and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation.

According to some embodiments of the invention, the method further comprises: before programming operation, floating gate transistors with different gate structures are preset in the memory unit, and charge leakage speeds corresponding to the different gate structures are recorded; and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation.

The information recording method based on floating gate charge leakage according to the embodiment of the second aspect of the invention is applied to an electronic device for recording temperature, the device comprises a memory of a memory unit consisting of floating gate transistors, an insulating layer of the floating gate transistors is made of a material sensitive to temperature, and when the temperature exceeds a specified value, the characteristics of the insulating layer change, and the method comprises the following steps: presetting insulating layers with different temperature characteristics, and recording corresponding temperature thresholds of the insulating layers; selecting one or more floating gate transistors corresponding to the temperature threshold, injecting charges, and performing first ADC (analog to digital converter) sampling to be recorded as a first charge amount; performing second ADC sampling on the floating gate transistor and recording as a second charge amount; recording a temperature change based on the temperature threshold according to the first and second amounts of charge.

The information recording method based on floating gate charge leakage provided by the embodiment of the invention at least has the following beneficial effects: the information recording method based on floating gate charge leakage of the embodiment of the invention realizes that temperature information can be recorded when a power supply is turned off or no external power supply is available and a battery is exhausted by virtue of the charge leakage characteristic of the floating gate transistor.

According to some embodiments of the invention, the floating gate transistor comprises a first transistor and a second transistor, the insulating layer under the floating gate of the first transistor corresponds to a first temperature threshold, the insulating layer on the floating gate of the second transistor corresponds to a second temperature threshold, the first temperature threshold is smaller than the second temperature threshold, and the method of recording the temperature change when the second ADC sampling is performed comprises: performing second ADC sampling on the source electrodes of the first transistor and the second transistor to obtain a first transistor charge amount and a second transistor charge amount; determining whether characteristics of an insulating layer of the first transistor and an insulating layer of the second transistor are changed according to a first charge amount of the first transistor and the second transistor, a first transistor charge amount, and a second transistor charge amount; if the characteristics of the insulating layer of the first transistor are not changed, the current temperature is lower than the first temperature threshold value; if the characteristics of the insulating layer of the first transistor are changed and the characteristics of the insulating layer of the second transistor are not changed, the current temperature is greater than the first temperature threshold and less than the second temperature threshold; if the insulating layer characteristic of the first transistor and the insulating layer characteristic of the second transistor both change, the current temperature is greater than the second temperature threshold.

An information recording device based on floating gate charge leakage according to a third aspect of the present invention is applied to electronic device timing, and includes: a first memory having a memory cell composed of floating gate transistors; the ADC sampling module is electrically connected with the first memory; a processor; a second memory storing a computer program; the processor executes the computer program to implement the method as described in the embodiments of the first aspect of the present invention.

The information recording device based on floating gate charge leakage according to the embodiment of the invention at least has the following beneficial effects: the information recording device based on floating gate charge leakage of the embodiment of the invention can still record time information when a power supply is turned off or an external power supply is not provided and a battery is exhausted.

According to some embodiments of the present invention, the floating gate transistors constitute a floating gate transistor array, the floating gate transistor array is a plurality of floating gate structure transistors, sharing one gate, and transistors in the same row are cascaded; the floating gate transistor comprises a first transistor and a second transistor, and floating gate thicknesses of the first transistor and the second transistor are different.

According to some embodiments of the present invention, the floating gate transistor includes a third transistor and a fourth transistor, and a gate structure of the third transistor and a gate structure of the fourth transistor are different.

An information recording apparatus based on floating gate charge leakage according to a fourth aspect of the present invention, applied to an electronic device for recording temperature, includes: a first memory having a memory cell composed of floating gate transistors; the insulating layer of the floating gate transistor is made of a material sensitive to temperature, and when the temperature exceeds a specified value, the characteristics of the insulating layer are changed; the ADC sampling module is electrically connected with the first memory; a processor; a second memory storing a computer program; the processor executes the computer program to implement the method according to the embodiment of the second aspect of the present invention.

The information recording device based on floating gate charge leakage according to the embodiment of the invention at least has the following beneficial effects: the information recording device based on floating gate charge leakage of the embodiment of the invention can still record temperature information when a power supply is turned off or an external power supply is not provided and a battery is exhausted.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a flow chart illustrating a method according to a first embodiment of the present invention.

FIG. 2 is a flow chart illustrating a method according to a second embodiment of the present invention.

Fig. 3 is a schematic diagram of a floating gate transistor structure according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a transistor array structure according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a transistor array structure according to another embodiment of the invention.

Fig. 6 is a schematic diagram of a gate structure of a transistor according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a gate structure of a transistor according to another embodiment of the invention.

FIG. 8 is a diagram of a transistor structure with an insulating layer of temperature sensitive material according to the present invention.

Fig. 9 is a block diagram schematically illustrating the structure of the apparatus according to the third or fourth embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

The embodiment of the invention provides an information recording method, which can still record information such as time/temperature and the like when a power supply is turned off by utilizing the leakage characteristic of a semiconductor device, and can provide a timing requirement with certain precision after calibration. The basic mechanism is similar to that of the judgment of the age of the radioactive element by detecting the half-life period of the radioactive element in the substance.

Referring to fig. 3, in the embodiment of the present invention, information is recorded by a floating gate transistor, and the principle is as follows: after storing charges on the floating gate, the charges in the floating gate will leak slowly with time. As with the set alarm clock, charge is programmed into the gate at the beginning of the timer, and then its initial charge is recorded via ADC sampling. Over time, the charge will gradually drop. If sampling is performed with an ADC, time can be calculated from the curve. The intermediate process is not power-on.

Referring to fig. 1, the method of the first embodiment of the present invention is applied to an electronic device including a memory having memory cells formed of floating gate transistors, and includes the steps of:

a100, in response to a power-off instruction or equipment power failure, programming a preset storage unit in a memory, and sampling the charge quantity of the storage unit by using a first ADC (analog-to-digital converter) to be recorded as a first charge quantity;

a200, after the power supply is turned on, carrying out second ADC sampling on the charge quantity of the storage unit for the storage unit, and marking as a second charge quantity;

and A300, calculating the time interval of the power-off operation and the power-on operation based on the charge leakage speed of the floating gate transistor according to the first charge quantity and the second charge quantity.

In some embodiments, referring to fig. 4 and 5, methods of embodiments of the invention further comprise: presetting a floating gate transistor array, wherein the floating gate transistor array is formed by a plurality of transistors with floating gate structures, a grid electrode is shared, and the transistors in the same row are cascaded; injecting charge from the transistor drain for the floating gate transistor array; ADC sampling is performed from the transistor source. This embodiment constructs an array for calibration of device characteristics (a simple algorithm could be averaging). As shown in fig. 4, the transistor array of the floating gate structure in fig. 4 shares a gate, and charges are injected into each transistor when injecting charges, and the amount of charges injected into the floating gate by each transistor is difficult to be consistent due to manufacturing accuracy and the like, which is also one of the reasons affecting accuracy. The embodiment of the invention adopts a common floating gate structure, and although the injected charges of each transistor are possibly more or less, the charges tend to be evenly distributed in the floating gate along with the time, as shown in fig. 5. In fig. 5, transistors in the same row are cascaded, a voltage is applied to the drain and the source after the cascade, and because the gate has a charge (the charge is continuously reduced along with the time lapse), the transistors are in a semi-conducting state, which is equivalent to a resistor, and the magnitude of the current can be measured by an ADC, so that data of the residual charge of the gate can be obtained. The same row of transistor cascades can average errors of single transistors caused by manufacturing accuracy problems, so that the measurement accuracy is increased.

In some embodiments, the method of embodiments of the present invention further comprises: presetting floating gate transistors with different floating gate thicknesses, and recording charge leakage speeds corresponding to the different floating gate thicknesses; and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation. In the embodiment, by designing the thickness of the floating gate, gate units with different leakage speeds can be constructed, and the combination of the gate units can realize the control of time precision.

In some embodiments, referring to fig. 6 and 7, methods of embodiments of the present invention further comprise: presetting floating gate transistors with different gate structures, and recording charge leakage speeds corresponding to the different gate structures; and selecting a corresponding floating gate transistor according to the required timing precision, and performing programming operation. The conventional transistor structure is a planar structure, and for example, the gate is desirably a thin layer with equal thickness, so that the uniformity is good. The present embodiment is intended to control the leakage speed of charges in the floating gate by a controllable technique, and can solve the problem by controlling the thickness of the gate as in the above embodiments, but the thickness of the gate is usually not uniform and has a certain deviation. To overcome this problem, the present embodiment achieves controlled charge leakage by controlling the shape of the gate. As shown in fig. 6 and 7, if the structure of the gate in fig. 6 is changed into a T-shaped step gate structure (fig. 7), two sides of the step gate structure are insulating SiO2, and the middle T-shaped part is conductive polysilicon, the leakage rate of the structure is different from that of the structure shown in fig. 6.

Studies have shown that with increasing temperature, electrons in the floating gate structure leak more easily, and therefore temperature changes can also be recorded by this property by how much floating gate charge remains. If the insulating layer is made of a material sensitive to temperature, when the temperature exceeds a predetermined value, the characteristics of the insulating layer change, causing a rapid loss of charge in the floating gate.

Referring to fig. 2 and 8, the method of the second embodiment of the present invention is applied to an electronic device for recording temperature, the device including a memory having memory cells formed of floating gate transistors, the insulating layer (insulating layer b shown in fig. 8) of the floating gate transistors being made of a material sensitive to temperature, and the characteristics of the insulating layer being changed when the temperature exceeds a specified value, the method of the present embodiment including the steps of:

b100, presetting insulating layers with different temperature characteristics, and recording corresponding temperature thresholds of the insulating layers;

b200, selecting one or more floating gate transistors corresponding to temperature thresholds, injecting charges, carrying out first ADC sampling, and marking as a first charge amount;

b300, performing second ADC sampling on the floating gate transistor, and recording as a second charge amount;

and B400, recording the temperature change based on the temperature threshold according to the first charge amount and the second charge amount.

In some embodiments, the floating gate transistor of this embodiment includes a first transistor and a second transistor, where an insulating layer under a floating gate of the first transistor corresponds to a first temperature threshold, an insulating layer on a floating gate of the second transistor corresponds to a second temperature threshold, and the first temperature threshold is smaller than the second temperature threshold, and the method for recording a temperature of this embodiment includes: performing ADC (analog-to-digital converter) sampling on the source electrodes of the first transistor and the second transistor to obtain the charge amount of the first transistor and the charge amount of the second transistor; determining whether or not characteristics of an insulating layer of the first transistor and an insulating layer of the second transistor are changed, based on the first transistor charge amount and the second transistor charge amount; if the characteristics of the insulating layer of the first transistor are not changed, the current temperature is lower than a first temperature threshold value; if the characteristics of the insulating layer of the first transistor change and the characteristics of the insulating layer of the second transistor do not change, the current temperature is greater than a first temperature threshold and less than a second temperature threshold; if the insulating layer characteristic of the first transistor and the insulating layer characteristic of the second transistor both change, then the current temperature is greater than the second temperature threshold.

In a specific embodiment, the insulating layers under the floating gates of the 3 transistors are respectively designed by using insulating layers with characteristics of 60 degrees, 80 degrees and 100 degrees, when the temperature exceeds 60 degrees, the charge of the transistor with the characteristic of 60 is firstly leaked, and if the temperature exceeds 100 degrees, the charge of the floating gates of the 3 transistors is completely leaked.

Referring to fig. 9, an information recording apparatus based on floating gate charge leakage according to a third embodiment of the present invention is applied to an electronic device timer, and includes: a first memory having a memory cell composed of floating gate transistors; the ADC sampling module is electrically connected with the first memory; a processor; a second memory storing a computer program; the processor executes the computer program to implement the timing method of the first embodiment described above.

Referring to fig. 5, in some embodiments, the floating gate transistors constitute a floating gate transistor array, the floating gate transistor array is formed by a plurality of transistors with floating gate structures, one gate is shared, and the transistors in the same row are cascaded; this embodiment constructs an array for calibration of device characteristics (a simple algorithm could be averaging). As shown in fig. 4, the transistor array of the floating gate structure in fig. 4 shares a gate, and charges are injected into each transistor when injecting charges, and the amount of charges injected into the floating gate by each transistor is difficult to be consistent due to manufacturing accuracy and the like, which is also one of the reasons affecting accuracy. The embodiment of the invention adopts a common floating gate structure, and although the injected charges of each transistor are possibly more or less, the charges tend to be evenly distributed in the floating gate along with the time, as shown in fig. 5. In fig. 5, transistors in the same row are cascaded, a voltage is applied to the drain and the source after the cascade, and because the gate has a charge (the charge is continuously reduced along with the time lapse), the transistors are in a semi-conducting state, which is equivalent to a resistor, and the magnitude of the current can be measured by an ADC, so that data of the residual charge of the gate can be obtained. The same row of transistor cascades can average errors of single transistors caused by manufacturing accuracy problems, so that the measurement accuracy is increased.

In some embodiments, the floating gate transistors include a first transistor and a second transistor, the floating gate thickness of the first transistor and the floating gate thickness of the second transistor being different. In the embodiment, by designing the thickness of the floating gate, gate units with different leakage speeds can be constructed, and the combination of the gate units can realize the control of time precision.

Referring to fig. 6 and 7, in some embodiments, the floating gate transistor includes a third transistor and a fourth transistor, and a gate structure of the third transistor and a gate structure of the fourth transistor are different. The conventional transistor structure is a planar structure, and for example, the gate is desirably a thin layer with equal thickness, so that the uniformity is good. The present embodiment is intended to control the leakage speed of charges in the floating gate by a controllable technique, and can solve the problem by controlling the thickness of the gate as in the above embodiments, but the thickness of the gate is usually not uniform and has a certain deviation. To overcome this problem, the present embodiment achieves controlled charge leakage by controlling the shape of the gate. As shown in fig. 6 and 7, if the structure of the gate in fig. 6 is changed into a T-shaped step gate structure (fig. 7), two sides of the step gate structure are insulating SiO2, and the middle T-shaped part is conductive polysilicon, the leakage rate of the structure is different from that of the structure shown in fig. 6.

Referring to fig. 8 and 9, an information recording apparatus based on floating gate charge leakage according to a fourth embodiment of the present invention, applied to an electronic device for recording temperature, includes: a first memory having a memory cell composed of floating gate transistors; the insulating layer of the floating gate transistor is made of a material sensitive to temperature, and when the temperature exceeds a specified value, the characteristics of the insulating layer are changed; the ADC sampling module is electrically connected with the first memory; a processor; a second memory storing a computer program; the processor executes the computer program to implement the method of recording temperature of the second embodiment described above.

It should be recognized that the method steps in embodiments of the present invention may be embodied or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.

Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or combinations thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more microprocessors. The computer program includes a plurality of instructions executable by one or more microprocessors.

Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.

A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display. The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.