阅读说明：本技术 一种基于动态相位选择的数字控制振荡器及其时钟产生方法 (Digital control oscillator based on dynamic phase selection and clock generation method thereof ) 是由 张�林 宋红东 于 2021-09-16 设计创作，主要内容包括：本发明的目的在于提供一种基于动态相位选择的数字控制振荡器及其时钟产生方法。本发明所提供的数字控制振荡器可以接收非多相的时钟信号,这个时钟信号可以是一个差分时钟信号,通过数字控制字向数字控制振荡器分配时钟调节要求,数字控制振荡器根据数字控制字可以动态地调节接收到的差分时钟信号的相位,以输出目标时钟信号。本发明减少了对芯片面积、功耗以及设计要求,降低了制造成本,具有优异的市场应用前景。(The invention aims to provide a digital control oscillator based on dynamic phase selection and a clock generation method thereof. The numerically controlled oscillator provided by the invention can receive a non-multiphase clock signal, the clock signal can be a differential clock signal, the clock adjustment requirement is distributed to the numerically controlled oscillator through the numerical control word, and the numerically controlled oscillator can dynamically adjust the phase of the received differential clock signal according to the numerical control word so as to output a target clock signal. The invention reduces the requirements on chip area, power consumption and design, reduces the manufacturing cost and has excellent market application prospect.)

1. A digital control oscillator comprises a first input end, a second input end and an output end, and is characterized by further comprising a phase adjusting module and a dynamic phase calculating and clock edge control module, wherein the dynamic phase calculating and clock edge control module

The phase adjusting module is connected with the first input end and the output end, is used for receiving a first clock input from the first input end, and is also used for receiving a second clock input from the second input end

Adjusting the phase of the first clock according to the control signal generated by the dynamic phase calculation and clock edge control module to obtain a second clock, and outputting the second clock through the output end,

the dynamic phase calculation and clock edge control module is connected with the second input end and the output end, is used for receiving a digital control word input from the second input end and a second clock output from the output end, and is further used for generating a control signal according to the digital control word and the second clock and sending the control signal to the phase adjustment module.

2. The numerically controlled oscillator of claim 1,

the dynamic phase calculation and clock edge control module is further configured to read first position information of a latest clock edge in the second clock, calculate second position information of a next clock edge according to the first position information and the digital control word, and generate a control signal including the second position information.

3. The numerically controlled oscillator of claim 1,

the dynamic phase calculation and clock edge control module is further configured to read rising edge position information of a latest clock edge in the second clock, calculate rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generate a control signal including the rising edge position information,

the phase adjusting module is further configured to adjust the phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, calculate falling edge position information according to a preset signal delay policy and the rising edge position information, and adjust the phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.

4. The numerically controlled oscillator of claim 1,

when the numerically controlled oscillator is in an initial condition,

the phase adjusting module is used for generating a clock edge of a second clock at the first secondary clock edge position according to the position information of the preset first secondary clock edge position, and outputting the second clock through the output end.

5. The numerically controlled oscillator of claim 1, further comprising

An output stage connected to the output for shaping the second clock output by the output.

6. The numerically controlled oscillator of claim 1,

the phase adjusting module comprises a current mode phase adjusting unit or a voltage mode phase adjusting unit.

7. The numerically controlled oscillator of claim 1, further comprising

And the clock adjusting module is connected to the first input end and used for receiving and adjusting the frequency of an original clock so as to generate the first clock and input the first clock to the phase adjusting module through the first input end.

8. The numerically controlled oscillator of claim 7,

the clock adjusting module comprises a phase-locked loop, a clock frequency division module or a clock frequency multiplication module.

9. The numerically controlled oscillator of claim 1, further comprising

The calibration module is used for calibrating the calibration module,

the calibration module is connected between the output end of the digital control oscillator and the phase adjustment module and used for receiving a calibration clock and a second clock, judging whether the second clock has a phase error or not by comparing the calibration clock with the second clock, and generating a phase adjustment strategy according to a comparison result to inform the phase adjustment module to adjust the second clock.

10. The numerically controlled oscillator of claim 9,

the calibration module comprises a measuring unit and a calibration unit connected to the measuring unit, wherein

The measuring unit is further connected to the output end and used for receiving the calibration clock and the second clock, and comparing the calibration clock with the second clock to judge whether a phase error exists in the second clock.

11. The numerically controlled oscillator of claim 9,

the phase adjustment strategy is an error look-up table comprising at least one adjustment strategy corresponding to clock information of the second clock,

the calibration module also comprises a lookup table unit used for generating an error lookup table according to the phase adjustment strategy and the clock information of the second clock corresponding to the phase adjustment strategy and sending the error lookup table to the phase adjustment module, the phase adjustment module comprises a storage unit, a retrieval unit and an adjustment unit,

the storage unit is used for storing the error lookup table,

the retrieval unit is configured to retrieve a corresponding adjustment strategy from the error lookup table according to the clock information of the second clock,

the adjusting unit is used for adjusting the second clock according to the adjusting strategy.

12. The numerically controlled oscillator according to any of claims 1 to 11, wherein the numerically controlled oscillator is applied to a phase locked loop,

the phase-locked loop is connected to the output end and the second input end, and the phase-locked loop generates the digital control word according to the second clock and the reference clock.

13. The numerically controlled oscillator of claim 12,

the phase-locked loop is a digital phase-locked loop comprising a digital phase frequency detector, a digital filter and a digital frequency divider, wherein the digital frequency divider is connected with the digital phase frequency detector and the output end and is used for generating a feedback clock according to a second clock output by the output end,

the digital phase frequency detector is further connected to the digital filter and used for receiving a reference clock and the feedback clock, calculating the frequency and/or phase difference between the feedback clock and the reference clock and sending the frequency and/or phase difference to the digital filter, and the digital filter is further connected to the second input end and used for generating the digital control word according to the frequency and/or phase difference and sending the digital control word to the second input end.

14. The numerically controlled oscillator of claim 12,

the phase-locked loop is a digital-analog mixed phase-locked loop comprising a phase frequency detector, an analog filter, an analog-digital converter and a frequency divider, wherein

The frequency divider is connected with the phase frequency detector and the output end and used for generating a feedback clock according to the second clock output by the output end,

the phase frequency detector is also connected with the analog filter and used for receiving a reference clock and the feedback clock and calculating the frequency and/or phase difference between the feedback clock and the reference clock so as to send the frequency and/or phase difference to the analog filter, the analog filter is also connected with the analog-digital converter and used for filtering the frequency and/or phase difference,

the analog-to-digital converter is also connected to the second input end and is used for generating a digital control word according to the frequency and/or the phase difference so as to send the digital control word to the second input end.

15. A method for clock generation based on a digitally controlled oscillator, comprising the steps of:

the phase adjusting module receives a first clock from a first input end and adjusts the first clock according to a control signal to obtain a second clock;

the dynamic phase calculation and clock edge control module receives a digital control word from the second input terminal;

the dynamic phase calculation and clock edge control module receives the second clock from an output;

the dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock and sends the control signal to the phase adjustment module;

the phase adjusting module adjusts the phase of the first clock according to the control signal to obtain a second clock; outputting the second clock through the output terminal.

16. The clock generation method of claim 15,

the step of generating a control signal by the dynamic phase calculation and clock edge control module according to the digital control word and the second clock comprises:

and the dynamic phase calculation and clock edge control module reads first position information of the latest clock edge in the second clock, calculates second position information of the next clock edge according to the first position information and the digital control word, and generates a control signal containing the second position information.

17. The clock generation method of claim 15,

the dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock, and the step of adjusting the phase of the first clock to obtain the second clock according to the control signal by the phase adjustment module comprises,

the dynamic phase calculation and clock edge control module reads the rising edge position information of the latest clock edge in the second clock, calculates the rising edge position information of the next clock edge according to the rising edge position information and the digital control word, and generates a control signal containing the rising edge position information,

the phase adjusting module adjusts the phase of the first clock to generate the rising edge of the second clock at the rising edge position corresponding to the rising edge position information according to the control signal,

the phase adjusting module is further configured to calculate falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjust the phase of the first clock to generate a falling edge of a second clock at a falling edge position corresponding to the falling edge position information.

18. The clock generation method of claim 15,

when the numerically controlled oscillator is in an initial condition,

and the phase adjusting module generates a clock edge of a second clock at the first clock edge position according to the preset position information of the first clock edge position, and outputs the second clock through the output end.

19. The clock generation method of claim 15, further comprising

The output stage receives the second clock output from the output terminal and performs a shaping process on the second clock.

20. The clock generation method of claim 15, further comprising

The phase adjusting module comprises a current mode phase adjusting unit or a voltage mode phase adjusting unit, and the phase of the clock signal is adjusted through current or voltage adjustment.

21. The clock generation method of claim 15, further comprising

The clock adjusting module receives and adjusts the frequency of an original clock to generate the first clock and inputs the first clock to the phase adjusting module through the first input end.

22. The clock generation method of claim 15,

the clock adjusting module comprises a phase-locked loop, a clock frequency division module or a clock frequency multiplication module.

23. The clock generation method of claim 15, further comprising the clock calibration step of:

the calibration module receives a calibration clock and a second clock, judges whether the second clock has a phase error by comparing the calibration clock with the second clock, and generates a phase adjustment strategy according to a comparison result to inform the phase adjustment module to adjust the second clock.

24. The clock generation method of claim 23,

the phase adjustment strategy is an error look-up table comprising at least one adjustment strategy corresponding to clock information of the second clock,

the phase adjustment module stores the error lookup table therein,

the phase adjustment module retrieves a corresponding adjustment strategy from the error lookup table based on clock information of the second clock,

the phase adjustment module also adjusts the second clock according to the adjustment strategy.

25. The clock generation method of claim 23, wherein the clock calibration comprises the steps of:

s001: the calibration module obtains a second clock and a calibration clock,

s002: acquiring and recording the clock information of the second clock, inquiring whether to traverse all the second clocks to be calibrated,

s003: when all the second clocks to be calibrated are traversed, generating an error lookup table;

when all the second clocks to be calibrated are not traversed, step S004 is executed,

s004: comparing the calibration clock with the second clock, determining whether the second clock has a phase error,

s005: when there is no phase error in the second clock, step S001 is performed,

when the second clock has phase error, generating an adjusting strategy and sending the adjusting strategy to the phase adjusting module, recording and associating the adjusting strategy and the second clock information,

s006: acquiring a second clock adjusted by the phase adjusting module according to the adjusting strategy,

s007: comparing the calibration clock with the adjusted second clock, determining whether the adjusted second clock has a phase error,

s008: when the adjusted second clock has no phase error, storing the recorded adjustment strategy associated with the second clock information, and executing step S001;

and when the adjusted second clock has a phase error, updating the adjustment strategy and sending the adjustment strategy to the phase adjustment module, updating and recording the adjustment strategy associated with the second clock information, and executing step S006.

26. The clock generation method of claim 23,

when the second clock or the adjusted second clock has a phase difference compared with the standard clock, judging that the second clock or the adjusted second clock has no phase error when the phase difference is not greater than a threshold value,

and when the phase difference is larger than a threshold value, judging that the second clock or the adjusted second clock has a phase error.

Technical Field

The invention relates to the technical field of oscillators, in particular to a digital control oscillator based on dynamic phase selection and a clock generation method thereof.

Background

Numerically Controlled Oscillators (NCO) are important components of software defined radio, direct data frequency synthesizers (DDS), Fast Fourier Transforms (FFT), etc., and are also one of the main factors that determine their performance, for generating controllable sine or cosine waves. Along with the improvement of the integration level of the chip, the chip is widely applied to the fields of signal processing, digital communication, modulation and demodulation, frequency conversion and speed regulation, guidance control, power electronics and the like.

Digitally controlled oscillators of the prior art typically require the generation of multi-phase clock inputs to a phase selection means by means of a multi-phase clock generator and a combination of e.g. a delay locked loop, a phase locked loop, an oscillator, or other generating means where multi-phase clocks can be generated to generate the target clock signal. Therefore, the chip carrying the digitally controlled oscillator has large workload, large power consumption, large required chip area and high design and manufacturing costs.

Disclosure of Invention

In order to overcome the technical defects, the invention aims to provide a digital control oscillator based on dynamic phase selection and a clock generation method thereof. The numerically controlled oscillator provided by the invention can receive a non-multiphase clock signal, the clock signal can be a differential clock signal, the clock adjustment requirement is distributed to the numerically controlled oscillator through the numerical control word, and the numerically controlled oscillator can adjust the phase of the received differential clock signal according to the numerical control word so as to output a target clock signal. In addition, the numerically controlled oscillator of the present invention further comprises a calibration device, which can calibrate the clock signal generated by the numerically controlled oscillator in real time and inform the numerically controlled oscillator to adjust the clock signal with errors, and can also generate an error lookup table to be provided to the numerically controlled oscillator.

One aspect of the present invention provides a digitally controlled oscillator, including a first input terminal, a second input terminal, an output terminal, a phase adjustment module, and a dynamic phase calculation and clock edge control module, where the phase adjustment module is connected to the first input terminal and the output terminal, and is configured to receive a first clock input from the first input terminal, and further configured to adjust a phase of the first clock according to a control signal generated by the dynamic phase calculation and clock edge control module to obtain a second clock, and output the second clock through the output terminal; the dynamic phase calculation and clock edge control module is connected with the second input end and the output end, is used for receiving a digital control word input from the second input end and a second clock output from the output end, and is further used for generating a control signal according to the digital control word and the second clock and sending the control signal to the phase adjustment module.

In some preferred embodiments, in the dco, the dynamic phase calculation and clock edge control module is further configured to read first position information of a latest clock edge in the second clock, calculate second position information of a next clock edge according to the first position information and the digital control word, and generate a control signal including the second position information.

In some preferred embodiments, in the numerically controlled oscillator, the dynamic phase calculation and clock edge control module is further configured to read rising edge position information of a latest clock edge in the second clock, calculate rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generate a control signal including the rising edge position information, and the phase adjustment module is further configured to adjust a phase of the first clock to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, calculate falling edge position information according to a preset signal delay policy and the rising edge position information, and adjust a phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.

In some preferred embodiments, when the dco is in the initial condition, the phase adjustment module is configured to generate a clock edge of a second clock at a position of a first secondary clock edge according to preset position information of the position of the first secondary clock edge, and output the second clock through the output terminal.

In some preferred embodiments, the digitally controlled oscillator further comprises an output stage, connected to the output terminal, for shaping the second clock output by the output terminal.

In some preferred embodiments, in the digitally controlled oscillator, the phase adjustment module includes a current-mode phase adjustment unit or a voltage-mode phase adjustment unit.

In some preferred embodiments, the digitally controlled oscillator further includes a clock adjusting module, connected to the first input terminal, for receiving and adjusting the frequency of the original clock, so as to generate the first clock and input the first clock to the phase adjusting module through the first input terminal.

In some preferred embodiments, the clock adjusting module in the numerically controlled oscillator comprises a phase-locked loop, a clock dividing module or a clock multiplying module.

In some preferred embodiments, the digitally controlled oscillator further includes a calibration module, connected between the output end of the digitally controlled oscillator and the phase adjustment module, for receiving a calibration clock and a second clock, comparing the calibration clock with the second clock to determine whether a phase error exists in the second clock, and generating a phase adjustment policy according to a comparison result to notify the phase adjustment module to adjust the second clock.

In some preferred embodiments, in the numerically controlled oscillator, the calibration module includes a measurement unit and a calibration unit connected to the measurement unit, where the measurement unit is further connected to the output end, and is configured to receive the calibration clock and the second clock, compare the calibration clock and the second clock to determine whether a phase error exists in the second clock, and the calibration unit is further connected to the phase adjustment module, and is configured to generate a phase adjustment policy according to a comparison result of the measurement unit, and send the phase adjustment policy to the phase adjustment module.

In some preferred embodiments, in the digitally controlled oscillator, the phase adjustment policy is an error lookup table including at least one adjustment policy corresponding to clock information of a second clock, and the calibration module further includes a lookup table unit configured to generate an error lookup table according to the phase adjustment policy and the clock information of the second clock corresponding to the phase adjustment policy, and send the error lookup table to the phase adjustment module; the phase adjusting module comprises a storage unit, a retrieval unit and an adjusting unit, the storage unit is used for storing the error lookup table, the retrieval unit is used for retrieving a corresponding adjusting strategy from the error lookup table according to the clock information of the second clock, and the adjusting unit is used for adjusting the second clock according to the adjusting strategy.

In some preferred embodiments, the digitally controlled oscillator is applied to a phase locked loop, the phase locked loop being connected to the output and the second input, the phase locked loop generating the digital control word according to the second clock and a reference clock.

In some preferred embodiments, the phase-locked loop is a digital phase-locked loop including a digital phase frequency detector, a digital filter, and a digital frequency divider, where the digital frequency divider is connected to the digital phase frequency detector and the output terminal, and is configured to generate a feedback clock according to a second clock output by the output terminal, the digital phase frequency detector is further connected to the digital filter, and is configured to receive a reference clock and the feedback clock, and calculate a frequency and/or a phase difference between the feedback clock and the reference clock, so as to send the frequency and/or the phase difference to the digital filter, and the digital filter is further connected to the second input terminal, and is configured to generate the digital control word according to the frequency and/or the phase difference, so as to send the digital control word to the second input terminal.

In some preferred embodiments, the phase-locked loop is a digital-analog hybrid phase-locked loop including a phase frequency detector, an analog filter, an analog-to-digital converter, and a frequency divider, where the frequency divider is connected to the phase frequency detector and the output terminal, and configured to generate a feedback clock according to a second clock output by the output terminal, the phase frequency detector is further connected to the analog filter, and configured to receive a reference clock and the feedback clock, and calculate a frequency and/or a phase difference between the feedback clock and the reference clock, so as to send the frequency and/or the phase difference to the analog filter, the analog filter is further connected to the analog-to-digital converter, and configured to filter the frequency and/or the phase difference, and the analog-to-digital converter is further connected to the second input terminal, and configured to generate a digital control word according to the frequency and/or the phase difference, to be sent to the second input.

In another aspect of the present invention, there is also provided a clock generation method based on a numerically controlled oscillator, including the steps of: the phase adjusting module receives a first clock from a first input end and adjusts the first clock according to a control signal to obtain a second clock; the dynamic phase calculation and clock edge control module receives a digital control word from the second input terminal; the dynamic phase calculation and clock edge control module receives the second clock from an output; the dynamic phase calculation and clock edge control module generates a control signal according to the digital control word and the second clock and sends the control signal to the phase adjustment module; the phase adjusting module adjusts the phase of the first clock according to the control signal to obtain a second clock; outputting the second clock through the output terminal.

In some preferred embodiments, in the clock generation method, the step of generating the control signal according to the digital control word and the second clock by the dynamic phase calculation and clock edge control module includes: and the dynamic phase calculation and clock edge control module reads first position information of the latest clock edge in the second clock, calculates second position information of the next clock edge according to the first position information and the digital control word, and generates a control signal containing the second position information.

In some preferred embodiments, in the clock generating method, the step of generating a control signal by the dynamic phase calculation and clock edge control module according to the digital control word and the second clock, and the step of adjusting the phase of the first clock to obtain the second clock by the phase adjustment module according to the control signal includes reading rising edge position information of a latest clock edge in the second clock by the dynamic phase calculation and clock edge control module, calculating rising edge position information of a next clock edge according to the rising edge position information and the digital control word, and generating the control signal including the rising edge position information, adjusting the phase of the first clock according to the control signal to generate a rising edge of the second clock at a rising edge position corresponding to the rising edge position information, and generating the control signal including the rising edge position information by the phase adjustment module according to a preset signal delay policy and the rising edge position information, and calculating falling edge position information, and adjusting the phase of the first clock to enable the falling edge of the second clock to occur at the falling edge position corresponding to the falling edge position information.

In some preferred embodiments, in the clock generation method, when the dco is in the initial condition, the phase adjustment module generates a clock edge of a second clock at a first secondary clock edge position according to preset position information of the first secondary clock edge position, and outputs the second clock through the output terminal.

In some preferred embodiments, the clock generation method further includes that the output stage receives a second clock output from the output terminal and shapes the second clock.

In some preferred embodiments, the clock generation method further includes that the phase adjustment module includes a current-mode phase adjustment unit or a voltage-mode phase adjustment unit, and the phase adjustment of the clock signal is implemented by current or voltage adjustment.

In some preferred embodiments, the clock generation method further includes that the clock adjustment module receives and adjusts a frequency of an original clock to generate the first clock and inputs the first clock to the phase adjustment module through the first input terminal.

In some preferred embodiments, in the clock generation method, the clock adjustment module includes a phase-locked loop, a clock division module, or a clock multiplication module.

In some preferred embodiments, the clock generation method further includes a clock calibration step, in which a calibration module receives a calibration clock and a second clock, compares the calibration clock with the second clock to determine whether a phase error exists in the second clock, and generates a phase adjustment policy according to a comparison result to notify the phase adjustment module to adjust the second clock.

In some preferred embodiments, in the clock generation method, the phase adjustment policy is an error lookup table including at least one adjustment policy corresponding to clock information of a second clock, the phase adjustment module stores the error lookup table, the phase adjustment module retrieves a corresponding adjustment policy from the error lookup table according to the clock information of the second clock, and the phase adjustment module further adjusts the second clock according to the adjustment policy.

In some preferred embodiments, in the clock generation method, the clock calibration method includes the following steps:

s001: the calibration module obtains a second clock and a calibration clock,

s002: acquiring and recording the clock information of the second clock, inquiring whether to traverse all the second clocks to be calibrated,

s003: when all the second clocks to be calibrated are traversed, generating an error lookup table;

when all the second clocks to be calibrated are not traversed, step S004 is executed,

s004: comparing the calibration clock with the second clock, determining whether the second clock has a phase error,

s005: when there is no phase error in the second clock, step S001 is performed,

when the second clock has phase error, generating an adjusting strategy and sending the adjusting strategy to the phase adjusting module, recording and associating the adjusting strategy and the second clock information,

s006: acquiring a second clock adjusted by the phase adjusting module according to the adjusting strategy,

s007: comparing the calibration clock with the adjusted second clock, determining whether the adjusted second clock has a phase error,

s008: storing the recorded clock and the second clock when there is no phase error in the adjusted second clock

The adjustment strategy associated with the information is executed, and step S001 is executed;

and when the adjusted second clock has a phase error, updating the adjustment strategy and sending the adjustment strategy to the phase adjustment module, updating and recording the adjustment strategy associated with the second clock information, and executing step S006.

In some preferred embodiments, in the clock calibration method, when a phase difference exists between the second clock or the adjusted second clock and the standard clock, when the phase difference is not greater than a threshold, it is determined that there is no phase error in the second clock or the adjusted second clock, and when the phase difference is greater than the threshold, it is determined that there is a phase error in the second clock or the adjusted second clock.

After the technical scheme is adopted, compared with the prior art, the method has the following beneficial effects:

1. the digital control oscillator and the clock generating method thereof can dynamically adjust the clock phase based on the non-multiphase clock signal, thereby meeting various application requirements;

2. the calibration device and the clock calibration method thereof can dynamically calibrate the clock signal and also can generate the error lookup table, thereby improving the calibration efficiency;

3. the digitally controlled oscillator and the calibration device thereof reduce the requirements on chip area and design, reduce the manufacturing cost and have excellent market application prospect.

Drawings

FIG. 1 is a schematic diagram of a numerically controlled oscillator in accordance with a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of a current-mode phase adjustment circuit according to a preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a voltage mode phase adjustment circuit according to a preferred embodiment of the present invention;

FIG. 4 is a schematic diagram of another digitally controlled oscillator according to a preferred embodiment of the present invention;

FIG. 5 is a block diagram of a numerically controlled oscillator including a calibration block in accordance with a preferred embodiment of the present invention;

FIG. 6 is a schematic diagram of a digitally controlled oscillator for use in a phase locked loop, in accordance with a preferred embodiment of the present invention;

FIG. 7 is a schematic diagram of another digitally controlled oscillator for use in a phase locked loop, in accordance with a preferred embodiment of the present invention;

FIG. 8 is a flow chart illustrating a clock generation method for a numerically controlled oscillator according to a preferred embodiment of the present invention;

FIG. 9 is a schematic diagram of dynamically selecting phase generated clock signals in accordance with a preferred embodiment of the present invention;

FIG. 10 is a flow chart illustrating a method for clock calibration of a numerically controlled oscillator in accordance with a preferred embodiment of the present invention;

fig. 11 is a flow chart illustrating another clock calibration method for a dco according to a preferred embodiment of the invention.

Detailed Description

The advantages of the invention are further illustrated in the following description of specific embodiments in conjunction with the accompanying drawings.

It should be understood, however, that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather these embodiments are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". Other explicit and implicit definitions are also possible below.

Fig. 1 is a schematic diagram of a digitally controlled oscillator according to a preferred embodiment of the present invention. As can be seen from the figure, the digitally controlled oscillator provided in this embodiment mainly includes: the dynamic phase calculation and clock edge control module is also connected with the output end and the second input end. Based on the above structural design, a first clock can be input to the dco through the first input terminal, where the first clock is a non-multiphase clock, and may be preferably a differential clock, which includes a pair of clock signals with opposite phases and has excellent external interference resistance; the phase adjustment module may receive the first clock from the first input terminal, and in addition, the phase adjustment module may receive a control signal from the dynamic phase calculation and clock edge control module, so that the phase adjustment module may adjust the phase of the first clock according to the control signal to obtain a second clock having a target frequency and a phase; in this embodiment, a digital control word including target frequency and/or phase information may be input to the dco through the second input terminal, and the dynamic phase calculation and clock edge control module connected to the second input terminal may receive the digital control word from the second input terminal and receive the second clock from the output terminal, and generate the control signal according to the digital control word and the second clock to send the control signal to the phase adjustment module for adjusting the first clock. Preferably, when the dco is in an initial condition, that is, when the dco is powered on, the phase adjustment module adjusts the phase of the received first clock according to a preset control instruction to generate the second clock. Wherein, preferably, the first clock and the second clock may have the same or different frequencies.

It should be understood that the term "first clock" mentioned in this embodiment and other embodiments of the present invention refers to a clock that is not output from the numerically controlled oscillator, and the term "second clock" refers to a clock that is output from the numerically controlled oscillator. Based on the digitally controlled oscillator provided in this embodiment, the "first clock" can be adjusted in a cumulative, overlapping manner, and the "second clock" can be any one of the clocks obtained by adjusting the "first clock" any one time. In some embodiments of the present invention, there are cases where "the second clock" is used to represent "the first clock", and a person skilled in the art can fully distinguish between the cases according to the description of the specific embodiments.

Based on the above embodiments, it can be seen that the digitally controlled oscillator provided by the invention can implement multiple controllable phase adjustments of a non-multiphase clock based on a controllable digital control word and a fed-back second clock, so as to obtain a target clock meeting requirements. Therefore, the calculation workload loaded by the chip for bearing the digital control oscillator is reduced, the power consumption of the chip is reduced, the requirement on the area of the chip can be further reduced, and the design and manufacturing cost of the chip is reduced.

In some embodiments, the dynamic phase calculation and clock edge control module in the numerically controlled oscillator is further configured to read first position information of a last clock edge in the second clock, calculate second position information of a next clock edge according to the first position information and the numerical control word, and generate a control signal including the second position information. The last clock edge here refers to the clock edge of the second clock generated before this clock phase adjustment of the numerically controlled oscillator. The clock edge refers to a signal state generated due to a level transition of the digital clock signal, and comprises a rising edge which represents the transition of the clock signal from a low level to a high level; the falling edge indicates that the clock signal transits from a high level to a low level, so the last clock edge may be the last rising edge or the last falling edge. The digital control word can be a clock frequency control word of a required clock, and can be defined into an integer or decimal format according to actual requirements.

In an embodiment of the present invention, the precision control parameter of the numerically controlled oscillator may be set as M, where the precision control parameter M may be set by a person skilled in the art according to an actual application environment, the minimum period factor of the clock generated by the numerically controlled oscillator is a phase step P, which depends on the precision control parameter M and the frequency of the input first clock, that is, P is 1/(M Fin), the period Tout of the second clock is P DCW, if the first position information of the latest clock edge is edge (n), the second position information of the next clock edge is edge (n +1), edge (n +1) edge (n) + K DCW, where K is a constant, and K is an operation parameter of the numerically controlled oscillator according to actual needs, and if K is 1, edge (n) is position information of a rising edge, edge (n +1) is the rising edge position information in the next clock cycle, and if edge (n) is the falling edge position information, edge (n +1) is the falling edge position information in the next clock cycle; when K is equal to a decimal, if edge (n) is rising edge position information, edge (n +1) is falling edge position information (edge' (n)) in the same clock cycle, and if edge (n) is falling edge position information, edge (n +1) is rising edge position information in the next clock cycle. Based on the above strategy, the dynamic phase calculation and clock edge control module in the digitally controlled oscillator of the present invention can calculate the first position information edge (n) of the latest clock edge from the second clock received by the output terminal, and receive the digital control word from the second input terminal, and calculate the position information edge (n +1) of the next clock edge, so as to obtain the clock signal with the required frequency and phase.

In order to better understand the implementation manner of the above technical solution of the present invention, some more specific embodiments are provided herein, for example, the precision control parameter M of the numerically controlled oscillator may be set to 32, the operating parameter K may be set to 1, the frequency Fin of the first clock may be set to 1Ghz, in this case, the phase step P of the clock generated by the numerically controlled oscillator may be 1/(M Fin) 0.03125ns, and when the digital control word DCW is input to 40, the clock period Tout of the second clock generated by the numerically controlled oscillator may be 1.25ns, and the clock frequency Fout may be 1/Tout 800Mhz, which may be used in any scenario requiring the clock frequency of 800 Mhz. It should be understood that, according to actual needs, a person skilled in the art may set the precision control parameter M and the digital control word to be any values that satisfy the actual needs, for example, M is 1000, 80, 40, 32, 30, 20, 10, 1, 0.8, 0.4, 0.2, 0.01, 0.001, etc., and DCW is 100, 80, 40, 20.5, 9, 3, 1, 0.5, 0.01, etc.

In some embodiments, the dynamic phase calculation and clock edge control module in the numerically controlled oscillator is further configured to read rising edge position information of a latest clock edge in the second clock, calculate rising edge position information of a next clock edge according to the rising edge position information and the numerical control word, and generate a control signal including the rising edge position information; and the phase adjustment module is further used for adjusting the phase of the first clock to generate the rising edge of the second clock at the rising edge position corresponding to the rising edge position information, calculating the falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjusting the phase of the first clock to generate the falling edge of the second clock at the falling edge position corresponding to the falling edge position information.

For example, referring to fig. 9, the position information of the rising edge of the latest clock edge is edge (n), and the received digital control word is DCW, the position information of the rising edge of the next clock edge may be edge (n +1) ═ edge (n) + K × DCW × P, at this time, K ═ 1, and edge (n +1) is always the position information of the rising edge in the next clock cycle, that is, the position information of the falling edge is not calculated in this embodiment. In the embodiment, the position information of the falling edge does not need to be calculated, and the calculation can be carried out according to a signal delay strategy, so that the workload of a dynamic phase calculation and clock edge control module is reduced, and the design and manufacturing cost is reduced.

In some embodiments, when the dco is in the initial condition, the phase adjustment module is configured to generate a clock edge of the second clock at the first clock edge position according to the preset position information of the first clock edge position, and output the second clock through the output terminal. The numerically controlled oscillator may thus be enabled to enter into a dynamic, cyclic phase adjustment to obtain a clock signal that meets frequency and/or phase requirements.

In some embodiments, the digitally controlled oscillator further comprises an output stage, the output stage is connected to the output terminal, and the output stage can shape the second clock output by the output terminal to obtain a clock signal having a waveform meeting application requirements, so that the application field and the application range of the generated clock signal can be improved. Preferably, the output stage in the present embodiment may be any output stage circuit capable of realizing the above-described function.

In some embodiments, the phase adjustment module of the digitally controlled oscillator may include a current mode phase adjustment unit or a voltage mode phase adjustment unit, and preferably, referring to fig. 2 and 3, the current mode phase adjustment unit or the voltage mode phase adjustment unit may be a current mode phase adjustment circuit or a voltage mode phase adjustment circuit, based on which the present embodiment may implement the adjustment of the phase of the clock signal through current or voltage adjustment.

Referring to fig. 4, in some embodiments, the digitally controlled oscillator further includes a clock adjusting module, preferably, the clock adjusting module includes a phase-locked loop, a clock dividing module or a clock multiplying module, and the clock adjusting module is connected to the first input terminal, so that the original clock generated by the clock generating device is first input to the clock adjusting module before being input to the first input terminal, and the clock adjusting module adjusts the frequency of the original clock to obtain a first clock with a required frequency, and the first clock is input to the phase adjusting module through the first input terminal to be used by subsequent phase adjustment.

Referring to fig. 5, in some embodiments, the dco further includes a calibration module, connected between the output of the dco and the phase adjustment module, for receiving a calibration clock and a second clock generated by the dco, comparing the calibration clock and the second clock, determining whether a phase error exists in the second clock generated by the dco, and generating a phase adjustment policy according to a comparison result to notify the phase adjustment module to adjust the second clock. Preferably, when the comparison result shows that a phase difference exists between the second clock and the standard clock, and the phase difference is not greater than a threshold, the phase difference can be ignored, and the second clock is considered to have no phase error; and when the phase difference between the second clock and the standard clock is greater than the threshold, the second clock is considered to have a phase error, and in this case, the calibration module generates a phase adjustment strategy according to the phase difference between the second clock and the standard clock, and the phase adjustment strategy can enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy, so as to obtain the second clock with the phase error eliminated.

In some embodiments, the calibration module includes a measurement unit and a calibration unit connected to the measurement unit, wherein the measurement unit is further connected to an output terminal of the dco, so that the measurement unit can receive a second clock generated by the dco and a calibration clock, and the measurement unit can determine whether a phase error exists in the second clock by comparing the calibration clock with the second clock; the calibration unit is further connected to a phase adjustment module of the digitally controlled oscillator, and the calibration unit can generate a phase adjustment strategy according to the comparison result of the measurement unit, and the phase adjustment strategy can enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy, so as to obtain a second clock with the phase error eliminated.

In some embodiments, the phase adjustment policy is an error lookup table including at least one adjustment policy corresponding to clock information of the second clock, in which case, the calibration module further includes a lookup table unit, and the lookup table unit may generate an error lookup table according to the phase adjustment policy generated by the phase calibration unit and the clock information of the second clock corresponding to the phase adjustment policy, and may send the error lookup table to the phase adjustment module. And when the phase adjusting module stores the error lookup table and adjusts the first clock to obtain the second clock, the phase adjusting module searches the error lookup table according to the clock information of the second clock, judges whether the second clock has a phase error, and can adjust the first clock again according to the corresponding adjusting strategy searched from the error lookup table to obtain the second clock without the phase error. Preferably, the phase adjustment module in the numerically controlled oscillator further includes a storage unit, a retrieval unit, and an adjustment unit, where the storage unit may store the error lookup table, the retrieval unit may retrieve the corresponding adjustment strategy from the error lookup table according to the clock information of the second clock, and the adjustment unit may adjust the second clock according to the adjustment strategy retrieved by the retrieval unit to obtain the second clock with the phase error removed.

In some embodiments, the digitally controlled oscillator in the above embodiments may be applied to a phase-locked loop, where the phase-locked loop is connected to the output terminal of the digitally controlled oscillator and the second input terminal, and the phase-locked loop may be implemented to generate a corresponding digital control word according to the second clock generated by the digitally controlled oscillator and a reference clock received, for example, from a clock source with a fixed frequency and phase, where the digital control word reflects the required clock frequency and/or phase, and is input to the digitally controlled oscillator, and may be implemented to control the digitally controlled oscillator to generate the second clock signal according to the frequency and/or phase requirement according to the method in the above embodiments. Therefore, the numerically controlled oscillator provided by the invention can dynamically generate specific clock signals according to specific applications in application, and is flexible in application and controllable in cost.

Referring to fig. 6, in some embodiments, the phase-locked loop may be a digital phase-locked loop including a digital phase frequency detector, a digital filter, and a digital frequency divider, wherein the digital frequency divider is connected to the output terminals of the digital phase frequency detector and the digitally controlled oscillator, and the digital frequency divider generates the feedback clock according to the second clock output by the output terminals; the digital phase frequency detector is also connected with the digital filter, receives the reference clock and the feedback clock, calculates the frequency and/or phase difference between the feedback clock and the reference clock, and sends the calculated frequency and/or phase difference to the digital filter, and the digital filter is also connected with the second input end of the digital control oscillator, so that a digital control word can be generated according to the received frequency and/or phase difference and sent to the second input end, and the digital control oscillator is controlled to generate a second clock signal meeting the frequency and/or phase requirements.

Referring to fig. 7, in some embodiments, the phase-locked loop may be a digital-analog hybrid phase-locked loop including a phase frequency detector, an analog filter, a digital-analog-digital converter, and a frequency divider, where the frequency divider is connected to the output ends of the phase frequency detector and the digitally controlled oscillator, and may generate a feedback clock according to a second clock output by the output ends; the phase frequency detector is also connected to the analog filter, can receive the reference clock and the feedback clock, and calculates the frequency and/or the phase difference between the feedback clock and the reference clock, so as to send the frequency and/or the phase difference to the analog filter, the analog filter is also connected to the analog-digital converter, and can perform filtering processing on the frequency and/or the phase difference, the analog-digital converter is also connected to the second input end of the digital control oscillator, and the analog-digital converter can generate a digital control word according to the frequency and/or the phase difference after filtering processing, so as to send the digital control word to the second input end, so that the digital control oscillator is controlled to generate a second clock signal meeting the frequency and/or phase requirements.

In another aspect of the present invention, a clock generation method based on a numerically controlled oscillator is also provided, and the method can be applied to the numerically controlled oscillator described in the above embodiments. Referring to fig. 8, which is a schematic flow chart of a clock generation method according to a preferred embodiment of the present invention, it can be seen that the clock generation method of the present embodiment includes the following steps:

-a phase adjustment module receiving a first clock from a first input, adjusting said first clock in accordance with a control signal to obtain a second clock;

-the dynamic phase calculation and clock edge control module receives the digital control word from the second input;

-said dynamic phase calculation and clock edge control module receiving said second clock from an output;

-the dynamic phase calculation and clock edge control module generates a control signal from the digital control word and the second clock and sends it to the phase adjustment module;

-the phase adjustment module adjusts the phase of the first clock to obtain a second clock according to the control signal;

-outputting the second clock through the output.

The first clock is a non-multiphase clock, and may preferably be a differential clock.

In some implementations, the step of the dynamic phase calculation and clock edge control module generating a control signal from the digital control word and the second clock comprises:

-the dynamic phase calculation and clock edge control module reads first position information of a last clock edge in the second clock;

-said dynamic phase calculation and clock edge control module calculating second position information of a next clock edge from said first position information and said digital control word and generating a control signal comprising said second position information.

The last clock edge here refers to the clock edge of the second clock generated before this clock phase adjustment of the numerically controlled oscillator. The clock edge refers to a signal state generated due to a level transition of the digital clock signal, and comprises a rising edge which represents the transition of the clock signal from a low level to a high level; the falling edge indicates that the clock signal transits from a high level to a low level, so the last clock edge may be the last rising edge or the last falling edge. The digital control word is a clock frequency control word of a required clock and can be defined into an integer or decimal format according to actual requirements. For an example of a specific working principle and a specific implementation manner of the dynamic phase calculation and clock edge control module in this embodiment, reference may be made to the detailed description of the digitally controlled oscillator portion, which is not described herein again.

In some embodiments, the step of generating a control signal by the dynamic phase calculation and clock edge control module according to the digital control word and the second clock, and the step of adjusting the phase of the first clock to obtain the second clock by the phase adjustment module according to the control signal comprises:

-the dynamic phase calculation and clock edge control module reads the rising edge position information of the latest clock edge in the second clock and calculates the rising edge position information of the next clock edge from the rising edge position information and the digital control word and generates a control signal comprising the rising edge position information;

the phase adjusting module adjusts the phase of the first clock according to the control signal, and a rising edge of a second clock occurs at a rising edge position corresponding to the rising edge position information;

the phase adjusting module further calculates falling edge position information according to a preset signal delay strategy and the rising edge position information, and adjusts the phase of the first clock to generate a falling edge of the second clock at a falling edge position corresponding to the falling edge position information.

For an example of a specific working principle and a specific implementation manner of the dynamic phase calculation and clock edge control module in this embodiment, reference may be made to the detailed description of the digitally controlled oscillator portion, which is not described herein again.

In some embodiments, when the dco is in the initial condition, the phase adjustment module generates a clock edge of a second clock at a first clock edge position according to position information of a preset first clock edge position, and outputs the second clock through the output terminal. The numerically controlled oscillator may thus be enabled to enter into a dynamic, cyclic phase adjustment to obtain a clock signal that meets frequency and/or phase requirements.

In some embodiments, the clock generation method further includes the step of receiving a second clock output from the output terminal by using the output stage, and shaping the second clock to obtain a clock signal having a waveform meeting the application requirement, so that the applicability and range of the generated clock signal can be improved.

In some embodiments, the phase adjustment module in the digitally controlled oscillator includes a current-mode phase adjustment unit or a voltage-mode phase adjustment unit, and the adjustment of the phase of the clock signal can be realized through current or voltage adjustment.

In some embodiments, the clock generation method further includes a step of receiving and adjusting a frequency of an original clock by using a clock adjustment module to generate the first clock meeting the application requirement and inputting the first clock to the phase adjustment module through the first input terminal. Preferably, the clock adjusting module may include a phase locked loop, a clock dividing module, or a clock multiplying module.

Referring to fig. 10, in some embodiments, the clock generation method further includes a step of receiving a calibration clock and a second clock by using a calibration module, comparing the calibration clock and the second clock to determine whether a phase error exists in the second clock, and generating a phase adjustment policy according to a comparison result to notify the phase adjustment module to adjust the second clock. Preferably, when the comparison result shows that a phase difference exists between the second clock and the standard clock, and the phase difference is not greater than a threshold, the phase difference can be ignored, and the second clock is considered to have no phase error; and when the phase difference between the second clock and the standard clock is greater than the threshold, the second clock is considered to have a phase error, and in this case, the calibration module generates a phase adjustment strategy according to the phase difference between the second clock and the standard clock, and the phase adjustment strategy can enable the phase adjustment module to adjust the first clock according to the phase adjustment strategy, so as to obtain the second clock with the phase error eliminated.

In some embodiments, the phase adjustment strategy is an error lookup table including at least one adjustment strategy corresponding to clock information of a second clock, and based on this, if the phase adjustment module stores the error lookup table, the phase adjustment module may retrieve a corresponding adjustment strategy from the error lookup table according to the clock information of the second clock, and adjust the second clock again according to the adjustment strategy to obtain the second clock with the phase error eliminated.

Referring to fig. 11, which is a flowchart illustrating a clock calibration method according to a preferred embodiment of the present invention, it can be seen that, in some embodiments, the clock calibration method may further include the following steps:

s001: the calibration module acquires a second clock and a calibration clock;

s002: acquiring and recording clock information of the second clock, and inquiring whether to traverse all the second clocks to be calibrated;

s003: when all the second clocks to be calibrated are traversed, generating an error lookup table;

when all the second clocks to be calibrated are not traversed, executing step S004;

s004: comparing the calibration clock with the second clock, and judging whether the second clock has a phase error;

s005: when the second clock has no phase error, performing step S001;

when the second clock has phase error, generating an adjusting strategy and sending the adjusting strategy to the phase adjusting module, recording and associating the adjusting strategy and the second clock information,

s006: acquiring a second clock adjusted by the phase adjusting module according to the adjusting strategy,

s007: comparing the calibration clock with the adjusted second clock, determining whether the adjusted second clock has a phase error,

s008: when the adjusted second clock has no phase error, storing the recorded adjustment strategy associated with the second clock information, and executing step S001;

and when the adjusted second clock has a phase error, updating the adjustment strategy and sending the adjustment strategy to the phase adjustment module, updating and recording the adjustment strategy associated with the second clock information, and executing step S006.

Based on the above embodiments, it can be seen that the calibration method provided by this embodiment can also implement pre-calibration of all clock signals generated by the digitally controlled oscillator, and generate an error lookup table for storage in the phase adjustment module of the digitally controlled oscillator, so that, in operation, the phase adjustment module can calibrate and adjust the generated second clock in real time, so that the second clock of the digitally controlled oscillator has no phase error, and meets the requirements of practical applications.

In some embodiments, when the second clock or the adjusted second clock has a phase difference compared with the standard clock, it is determined that there is no phase error in the second clock or the adjusted second clock when the phase difference is not greater than a threshold, and it is determined that there is a phase error in the second clock or the adjusted second clock when the phase difference is greater than a threshold. The threshold value can be adjusted according to the actual application requirements to meet different requirements for clock precision in different applications.

It should be noted that the embodiments of the present invention have been described in terms of preferred embodiments, and not by way of limitation, and that those skilled in the art can make modifications and variations of the embodiments described above without departing from the spirit of the invention.