阅读说明：本技术 频率计测装置、微控制器和电子设备 (Frequency measuring device, microcontroller, and electronic apparatus ) 是由 桥本敬介 于 2021-06-22 设计创作，主要内容包括：频率计测装置、微控制器和电子设备。能够低成本地扩大频率的计测范围的频率计测装置。频率计测装置具有：计测期间设定电路,其根据基准时钟信号设定计测期间；第1计数器电路,其对所述计测期间中的基于输入信号的期间的所述基准时钟信号的脉冲数进行计数；第2计数器电路,其对所述计测期间中的所述输入信号的脉冲数进行计数；第1频率计算电路,设所述基准时钟信号的频率为f-(R)、所述计测期间中的所述基准时钟信号的脉冲数为n-(R)、所述第2计数器电路的计数值为n-(IN)、所述第1计数器电路的计数值为n-(E),通过f-(R)×n-(IN)/n-(R)计算第1频率；第2频率计算电路,其通过f-(R)×n-(IN)/n-(E)计算第2频率；频率选择电路,其选择第1频率或第2频率作为所述输入信号的频率。(Frequency measurement device, microcontroller and electronic equipment. A frequency measuring device capable of extending the frequency measuring range at low cost. The frequency measuring device includes: a measurement period setting circuit that sets a measurement period based on the reference clock signal; a 1 st counter circuit that counts the number of pulses of the reference clock signal in a period based on an input signal in the measurement period; a 2 nd counter circuit that counts the number of pulses of the input signal in the measurement period; a 1 st frequency calculation circuit for setting the frequency of the reference clock signal to f R And the number of pulses of the reference clock signal in the measurement period is n R The count value of the 2 nd counter circuit is n IN The count value of the 1 st counter circuit is n E Through f R ×n IN /n R Calculating a 1 st frequency; 2 nd frequency calculation circuit which passes f R ×n IN /n E Calculating the 2 nd frequency; a frequency selection circuit that selects either a 1 st frequency or a 2 nd frequency as a frequency of the input signal.)

1. A frequency measuring device for measuring the frequency of an input signal,

the frequency measurement device includes:

a measurement period setting circuit that sets a measurement period of the frequency of the input signal based on a reference clock signal;

a 1 st counter circuit that counts the number of pulses of the reference clock signal in a period based on the input signal in the measurement period;

a 2 nd counter circuit that counts the number of pulses of the input signal in the measurement period;

a 1 st frequency calculation circuit for setting the frequency of the reference clock signal to f_RAnd the number of pulses of the reference clock signal in the measurement period is n_RThe count value of the 2 nd counter circuit is n_INThe count value of the 1 st counter circuit is n_EThe 1 st frequency calculation circuit passes through f₁＝f_R×n_IN/n_RCalculating the 1 st frequency f₁；

2 nd frequency calculation circuit which passes f₂＝f_R×n_IN/n_ECalculating the 2 nd frequency f₂(ii) a And

a frequency selection circuit for selecting the 1 st frequency f₁Or the 2 nd frequency f₂As the frequency of the input signal.

2. The frequency measurement device according to claim 1,

the frequency measuring device includes a measurement error calculating circuit for calculating a measurement error based on the count value of the 2 nd counter circuit,

the frequency selection circuit selects the 1 st frequency f according to the measurement error₁Or the 2 nd frequency f₂As the frequency of the input signal.

3. The frequency measurement device according to claim 2,

the measurement error is + -1/n_IN。

4. The frequency measuring device according to any one of claims 1 to 3,

the 1 st counter circuit has a reference count value holding circuit,

the reference count value holding circuit samples the input signal with the reference clock signal during the measurement period, detects a rising edge or a falling edge of the input signal, and holds the number of pulses of the reference clock signal from a start point of the measurement period to a detection point of the rising edge or the falling edge of the input signal.

5. The frequency measuring device according to any one of claims 1 to 3,

the frequency measuring device includes a reference clock signal generating circuit that generates the reference clock signal.

6. The frequency measuring device according to any one of claims 1 to 3,

the 1 st frequency calculation circuit, the 2 nd frequency calculation circuit, and the frequency selection circuit are processed by a CPU in software.

7. The frequency measuring device according to any one of claims 1 to 3,

the 1 st frequency calculation circuit, the 2 nd frequency calculation circuit, and the frequency selection circuit are processed by a logic circuit.

8. A microcontroller having the frequency measurement device according to any one of claims 1 to 7.

9. An electronic device comprising the frequency measuring device according to any one of claims 1 to 7 or the microcontroller according to claim 8.

Technical Field

The invention relates to a frequency measuring device, a microcontroller and an electronic apparatus.

Background

As methods for measuring the frequency of an input signal using a clock signal serving as a reference, a direct count method and a countdown method are known. The direct counting method is as follows: the number of pulses of an input signal in a measurement period corresponding to a predetermined period of a clock signal is counted, and the frequency of the input signal is directly measured. In the direct counting method, there is an advantage that the maximum measurement error becomes smaller as the frequency of the input signal becomes higher, but in other words, there is a disadvantage that the maximum measurement error becomes larger as the frequency of the input signal becomes lower. By extending the measurement period, the measurement error can be reduced even when the frequency of the input signal is low, but the time required for measurement becomes long.

On the other hand, the countdown method is a method in which the number of pulses of a clock signal in a measurement period corresponding to a predetermined cycle of an input signal is counted, the time of 1 cycle of the input signal is measured, and the frequency of the input signal is indirectly measured by taking the reciprocal thereof. In the reciprocal counting method, there is an advantage that the lower the frequency of the input signal, the smaller the maximum measurement error, but in other words, there is a disadvantage that the higher the frequency of the input signal, the larger the maximum measurement error. By extending the measurement period, the measurement error can be reduced even when the frequency of the input signal is high, but the time required for measurement becomes long.

Therefore, in both the direct count method and the countdown method, there is a problem in that the measurable range of the frequency of the input signal is limited. In order to solve such a problem, patent document 1 describes a frequency measuring device as follows: the direct count method and the countdown method are switched according to the frequency of the input signal, whereby the frequency measurement range can be expanded.

Patent document 1: japanese patent laid-open publication No. 2005-9916

However, in the frequency measurement device described in patent document 1, it is necessary to switch 2 kinds of clock signals according to the frequency of the input signal. Therefore, there is a problem that: the circuit of the measuring apparatus is complicated, resulting in an increase in the cost of the apparatus.

Disclosure of Invention

One aspect of the frequency measurement device according to the present invention is a frequency measurement device that measures a frequency of an input signalThe frequency measuring device includes: a measurement period setting circuit that sets a measurement period of the frequency of the input signal based on a reference clock signal; a 1 st counter circuit that counts the number of pulses of the reference clock signal in a period based on the input signal in the measurement period; a 2 nd counter circuit that counts the number of pulses of the input signal in the measurement period; a 1 st frequency calculation circuit for setting the frequency of the reference clock signal to f_RAnd the number of pulses of the reference clock signal in the measurement period is n_RThe count value of the 2 nd counter circuit is n_INThe count value of the 1 st counter circuit is n_EThe 1 st frequency calculation circuit passes through f₁＝f_R×n_IN/n_RCalculating the 1 st frequency f₁(ii) a 2 nd frequency calculation circuit which passes f₂＝f_R×n_IN/n_ECalculating the 2 nd frequency f₂(ii) a And a frequency selection circuit for selecting the 1 st frequency f₁Or the 2 nd frequency f₂As the frequency of the input signal.

One embodiment of the microcontroller according to the present invention includes one embodiment of the frequency measurement device.

One embodiment of the electronic device according to the present invention includes one embodiment of the frequency measuring apparatus or one embodiment of the microcontroller.

Drawings

Fig. 1 is a diagram showing a configuration of a frequency measuring device according to the present embodiment.

Fig. 2 is a diagram showing a specific configuration example of the 1 st counter circuit.

Fig. 3 is a flowchart showing an example of the operation procedure of the frequency measuring device.

Fig. 4 is a timing chart showing an example of waveforms of various signals in the frequency measuring device.

Fig. 5 is a diagram showing the configuration of the microcontroller according to the present embodiment.

Fig. 6 is a flowchart showing an example of the operation sequence of the microcontroller.

Fig. 7 is a timing chart showing an example of waveforms of various signals in the microcontroller.

Fig. 8 is a functional block diagram showing a configuration example of the electronic apparatus of the present embodiment.

Fig. 9 is a functional block diagram showing another configuration example of the electronic apparatus of the present embodiment.

Fig. 10 is a diagram showing an example of the configuration of a digital multimeter as an example of an electronic device.

Description of the reference symbols

1: a frequency measuring device; 10: a measurement period setting circuit; 20: 1 st counter circuit; 21: a reference clock counting circuit; 22: a reference count value holding circuit; 23: an input signal edge detection circuit; 24: a reference clock initial count value holding circuit; 25: a reference clock update count value holding circuit; 30: a 2 nd counter circuit; 40: 1 st frequency calculation circuit; 50: a 2 nd frequency calculation circuit; 60: a frequency selection circuit; 70: a reference clock signal generation circuit; 80: a measurement error calculation circuit; 100: a microcontroller; 110: a reference clock signal generation circuit; 120: 1, a timer; 121: a comparison value register; 122: a counter; 123: a comparator; 124: an output control section; 125: a capture register; 126: an edge detection unit; 130: a 2 nd timer; 131: a counter; 132: a capture register; 133: an edge detection unit; 140: a memory; 141: timer 1 capture value 1; 142: timer 1, capture value 2; 143: timer 2, capture value 1; 144: timer 2 capture value 2; 145: a frequency calculation program; 150: a CPU; 160: a bus; 200: a vibrator; 300: an electronic device; 301: a digital multimeter; 310: a frequency measuring device; 320: a vibrator; 330: a microcontroller; 331: a reference clock signal generation circuit; 332: a comparator; 333: a measurement circuit; 334: a CPU; 335: a memory; 336: an LCD drive circuit; 337: a bus; 340: an operation section; 350: a communication unit; 360: a display unit; 370: and an audio output unit.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below do not limit the contents of the present invention described in the claims. It should be noted that all the configurations described below are not necessarily essential to the present invention.

1. Frequency measuring device

Fig. 1 is a diagram showing a configuration of a frequency measuring device according to the present embodiment. As shown IN fig. 1, the frequency measuring device 1 of the present embodiment includes a measurement period setting circuit 10, a 1 st counter circuit 20, a 2 nd counter circuit 30, a 1 st frequency calculating circuit 40, a 2 nd frequency calculating circuit 50, and a frequency selecting circuit 60, and measures the frequency of an input signal IN. The frequency measuring device 1 may be implemented by a single-chip Integrated circuit such as an asic (application Specific Integrated circuit), may be implemented by a multi-chip Integrated circuit, or may include discrete components.

The measurement period setting circuit 10 sets a measurement period T of the frequency of the input signal IN based on the reference clock signal CK, and outputs a measurement period signal TS indicating the measurement period T. In the present embodiment, the number of pulses n of the reference clock signal CK in the period T is measured_RIs predetermined. The measurement period setting circuit 10 changes the measurement period signal TS from low level to high level at a predetermined rising edge of the reference clock signal CK, and sets the pulse number n of the reference clock signal CK to be equal to the pulse number n_RWhen the signals coincide with each other, the measurement period signal TS is changed from the high level to the low level at the next rising edge of the reference clock signal CK. The measurement period T is a period during which the measurement period signal TS is at a high level.

The frequency measuring device 1 may include a reference clock signal generating circuit 70 that generates a reference clock signal CK. The reference clock signal CK is a clock signal serving as a reference for measuring the frequency of the input signal IN. Therefore, in the present embodiment, the reference clock signal CK is a clock signal with high frequency accuracy, and the reference clock signal generation circuit 70 may oscillate a quartz resonator to generate the reference clock signal CK, for example. In the present embodiment, the reference clock signal CK is a clock signal having a relatively low frequency of 1MHz or less, such as 32.768 kHz. Hereinafter, the frequency of the reference clock signal CK is denoted by f_R. Using the frequency f of the reference clock signal CK_RAnd measuring the number of pulses n of the reference clock signal CK in the period T_RThe measurement period T is expressed by equation (1). That is, the measurement period T is n of 1 cycle of the reference clock signal CK_RA period of multiple length.

The 1 st counter circuit 20 counts the number of pulses of the reference clock signal CK IN a period T' based on the input signal IN the measurement period T. For example, the period T' may be a period between the first rising edge and the last rising edge of the input signal IN the measurement period T, or may be a period between the first falling edge and the last falling edge of the input signal IN the measurement period T. Next, the count value CN1 of the 1 st counter circuit 20, that is, the pulse number of the reference clock signal CK in the period T', is set to n_E。

The 2 nd counter circuit 30 counts the number of pulses of the input signal IN the measurement period T. Next, the count value CN2 of the 2 nd counter circuit 30, i.e., the number of pulses of the input signal IN the measurement period T is represented by n_IN。

The 1 st frequency calculation circuit 40 calculates the 1 st frequency f by equation (2)₁. Frequency 1 f₁Is obtained by applying a voltage to n of 1 cycle of the reference clock signal CK_RThe measurement period T of multiple length is n_R/f_RThe number n of pulses of the input signal IN_INAnd a frequency obtained by a frequency measurement method for counting and measuring the frequency of the input signal IN. The measurement period T corresponds to n of the reference clock signal CK_RPeriod, as described above, n_RThis frequency measurement method is the same as the direct counting method because it is a predetermined fixed value.

The 2 nd frequency calculation circuit 50 calculates the 2 nd frequency f by equation (3)₂. Frequency 2 f₂Is a frequency obtained by a period measurement method as follows: for counting n in the measurement period T_INThe pulse number n of the reference clock signal CK IN the pulse number period T' of the next input signal IN_EThe time of 1 cycle of the input signal IN is counted, and the frequency of the input signal IN is measured by taking the reciprocal thereof. This cycle measurement method is the same as the countdown method IN that the cycle of the input signal IN is measured, but the countdown method measures a time of 1 cycle of the input signal IN, whereas the cycle measurement method measures a time of not only 1 cycle of the input signal IN. I.e. the number n of pulses of the input signal IN_INThis is different from the above-described countdown method because it varies depending on the frequency of the input signal IN.

The frequency selection circuit 60 selects the 1 st frequency f₁Or 2 nd frequency f₂As the frequency f of the input signal IN.

The frequency measuring device 1 may have a measurement error calculation circuit 80. The measurement error calculation circuit 80 calculates the number of pulses n of the input signal IN the measurement period T based on the count value CN2 of the 2 nd counter circuit 30, i.e., the count value n_INThe measurement error Err is calculated. In the present embodiment, the measurement error Err is the 1 st frequency f₁The maximum error Err1 of (a) is calculated by equation (4).

In the present embodiment, the frequency selection circuit 60 selects the 1 st frequency f based on the measurement error Err calculated by the measurement error calculation circuit 80₁Or 2 nd frequency f₂As the frequency f of the input signal IN. Specifically, if the absolute value of the measurement error Err is equal to or less than a predetermined threshold value VTE, the frequency selection circuit 60 selects the 1 st frequency f₁If the absolute value of the measurement error Err is larger than the threshold value VTE, the frequency selection circuit 60 selects the 2 nd frequency f₂。

Here, the 2 nd frequency f₂Maximum error ofThe difference Err2 is represented by formula (5).

Here, the number of pulses n of the reference clock signal CK in the measurement period T is measured_RIs predetermined, therefore, the 2 nd frequency f₂The maximum error Err2 is a fixed value regardless of the frequency of the input signal IN. Therefore, when the absolute value of the measurement error Err is smaller than the absolute value of the maximum error Err2, the 1 st frequency f₁Is more accurate than the 2 nd frequency f₂Has high accuracy, and the 2 nd frequency f is higher than the absolute value of the maximum error Err2 when the absolute value of the measurement error Err is larger than the absolute value of the maximum error Err2₂Is more accurate than the 1 st frequency f₁The precision of (2) is high. Therefore, for example, the frequency selection circuit 60 can select the 1 st frequency f by setting the threshold VTE to the absolute value of the maximum error Err2₁And 2 nd frequency f₂The frequency f is set as the higher precision of the frequency. Here, the threshold VTE may be a value other than the absolute value of the maximum error Err 2. For example, for simplicity, a constant approximating Err2 may be used.

The 1 st frequency calculation circuit 40, the 2 nd frequency calculation circuit 50, and the frequency selection circuit 60 may be processed by a logic circuit in a hardware manner. Thus, the frequency measuring device 1 can perform the 1 st frequency f at high speed₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂Selection of (2). Alternatively, the Processing of the 1 st frequency calculation circuit 40, the 2 nd frequency calculation circuit 50, and the frequency selection circuit 60 may be performed by a cpu (central Processing unit) in a software manner. Thus, the frequency measuring device 1 can easily change the 1 st frequency f₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂The manner of selection of (a).

Fig. 2 is a diagram showing a specific configuration example of the 1 st counter circuit 20. As shown in fig. 2, the 1 st counter circuit 20 has a reference clock count circuit 21 and a reference count value holding circuit 22.

The reference clock counting circuit 21 counts the number of pulses of the reference clock signal CK in the measurement period T indicated by the measurement period signal TS, and outputs a count value CT.

The reference count value holding circuit 22 samples the input signal IN with the reference clock signal CK during the measurement period T, detects a rising edge or a falling edge of the input signal IN, and holds the count value CT, which is the number of pulses of the reference clock signal CK from the start point of the measurement period T to the detection point of the rising edge or the falling edge of the input signal IN.

In the present embodiment, the reference count value holding circuit 22 includes an input signal edge detection circuit 23, a reference clock initial count value holding circuit 24, and a reference clock updated count value holding circuit 25.

The input signal edge detection circuit 23 samples the input signal IN with the reference clock signal CK during the measurement period T, detects a rising edge or a falling edge of the input signal IN, and outputs an edge detection signal ED. IN the present embodiment, the edge detection signal ED is a signal that transitions from a low level to a high level at the detection time of a rising edge or a falling edge of the input signal IN and transitions from a high level to a low level 1 cycle after the reference clock signal CK.

The reference clock initial count value holding circuit 24 holds the count value CT of the first high-level period of the edge detection signal ED as the count value CN1_1 during the measurement period T.

The reference clock update count value holding circuit 25 holds the count value CT of the high level period after the 2 nd time of the edge detection signal ED as the count value CN1_2 in the measurement period T. The count value CN1_2 is updated to the latest count value CT each time the edge detection signal ED goes high.

Therefore, the count value CN1_1 at the end of the measurement period T is set to n_E1Setting count value CN1_2 to n_E2When n is greater than n_E2And n_E1The difference (n) corresponds to the number of pulses n of the reference clock signal CK IN a period T' from the first rising edge or falling edge to the last rising edge or falling edge of the input signal IN IN the measurement period T_E. Therefore, in the above formula (3)) Substitution of n into_E＝n_E2-n_E1To obtain formula (6). The 2 nd frequency calculation circuit 50 may calculate the 2 nd frequency f by the equation (6)₂。

The count values CN1_1 and CN1_2 correspond to the count value CN1 in fig. 1. Further, if the count value CN1_1 is a fixed value, the reference clock first count value holding circuit 24 is not required. In this case, the count value CN1_2 corresponds to the count value CN1 of fig. 1.

Fig. 3 is a flowchart showing an example of the operation procedure of the frequency measuring device 1. As shown in fig. 3, first, the reference clock signal generation circuit 70 generates the reference clock signal CK (step S1).

Next, the measurement period setting circuit 10 sets the measurement period T and starts the measurement period T (step S2).

Next, the reference clock counting circuit 21 of the 1 st counter circuit 20 starts counting the number of pulses of the reference clock signal CK (step S3).

Next, the 2 nd counter circuit 30 starts counting the number of pulses of the input signal IN (step S4).

Next, the input signal edge detection circuit 23 of the 1 st counter circuit 20 stands by until a rising edge of the input signal IN is detected (step S5: no). Then, when the input signal edge detection circuit 23 detects a rising edge of the input signal IN (YES IN step S5), the reference clock initial count value holding circuit 24 of the 1 st counter circuit 20 holds the count value CT of the reference clock count circuit 21 as a count value CN1_1 (step S6).

Then, until the measurement period T is completed (NO IN step S9), the reference clock updated count value holding circuit 25 of the 1 st counter circuit 20 holds the count value CT of the reference clock counter circuit 21 as the count value CN1_2 each time the input signal edge detection circuit 23 detects the next rising edge of the input signal IN (YES IN step S7) (step S8).

Then, when the measurement period T is endedThereafter (step S9: YES), the count value CN2 of the 2 nd counter circuit 30 is set to n_INUsing the frequency f of the reference clock signal CK_RAnd measuring the number of pulses n of the reference clock signal CK in the period T_RThe 1 st frequency calculation circuit 40 calculates the 1 st frequency f by equation (2)₁(step S10).

Next, count value CN1_1 is set to n_E1The count value CN1_2 is set to n_E2The 2 nd frequency calculation circuit 50 calculates the 2 nd frequency f by equation (6)₂(step S11).

Next, the measurement error calculation circuit 80 calculates the measurement error Err by equation (4) (step S12).

Finally, when the measurement error Err is equal to or less than the threshold (step S13: YES), the frequency selection circuit 60 selects the 1 st frequency f₁When the measurement error Err is larger than the threshold value VTE (step S13: NO), the frequency selection circuit 60 selects the 2 nd frequency f as the frequency f of the input signal IN (step S14)₂As the frequency f of the input signal IN (step S15).

Fig. 4 is a timing chart showing an example of waveforms of various signals in the frequency measuring device 1.

In the example of fig. 4, first, at time T1, the measurement period signal TS changes from low level to high level, and the measurement period T starts. Then, in the measurement period T, the count value CT of the number of pulses of the reference clock signal CK is increased from 0 to 1 in sequence for each rising edge of the reference clock signal CK.

At time t2, the input signal IN transitions from a low level to a high level. IN synchronization with the rising edge of the input signal IN, the count value CN2 changes from 0 to 1. Further, the edge detection signal ED transitions from the low level to the high level in synchronization with the rising edge of the reference clock signal CK at time t 3.

At time t4, the edge detection signal ED is at a high level, and therefore, the count value CN1_1 is updated to the count value CT, i.e., 1, in synchronization with the rising edge of the reference clock signal CK.

At time t5, the input signal IN transitions from a low level to a high level. IN synchronization with the rising edge of the input signal IN, the count value CN2 changes from 1 to 2. Further, the edge detection signal ED transitions from the low level to the high level in synchronization with the rising edge of the reference clock signal CK at time t 6.

At time t7, the edge detection signal ED is at a high level, and therefore, the count value CN1_2 is updated to the count value CT, i.e., 5, in synchronization with the rising edge of the reference clock signal CK.

Thereafter, until time t8, as with time t5 to time t7, each time the input signal IN transitions from low level to high level, the count value CN2 is sequentially incremented by 1 IN synchronization with the rising edge of the input signal IN, and the count value CN1_2 is updated to the count value CT IN synchronization with the rising edge of the reference clock signal CK.

At time t8, the input signal IN transitions from a low level to a high level. IN synchronization with the rising edge of the input signal IN, the count value CN2 is counted from n_IN1 to n_IN. Further, the edge detection signal ED transitions from the low level to the high level in synchronization with the rising edge of the reference clock signal CK at time t 9.

At time t10, the edge detection signal ED is at a high level, and therefore, the count value CN1_2 is updated to the count value CT, that is, n in synchronization with the rising edge of the reference clock signal CK_R-3。

At time t11, the count value CT is n_RAccordingly, the measurement period signal TS changes from high level to low level, and the measurement period T ends. Count value CN2 n at time t11_INCorresponds to the number of pulses of the input signal IN the measurement period T. Further, n is a count value CN1_1, i.e., 1 at time t11_E1The count value CN1_2, i.e. n, at the time t11_R-3 is set to n_E2When n is greater than n_E2-n_E1The pulse number corresponds to the number of pulses of the reference clock signal CK in the period T' from the time T2 to the time T8.

At time t12, the 1 st frequency f is calculated by the above equation (2) in synchronization with the rising edge of the reference clock signal CK₁Calculating the 2 nd frequency f by said equation (6)₂The measurement error Err is calculated by the above equation (4). Then, the 1 st frequency f is selected based on the measurement error Err₁Or 2 nd frequency f₂As the frequency f of the input signal IN.

As described aboveAs described above, IN the frequency measuring device 1 of the present embodiment, the measurement period setting circuit 10 sets the measurement period T of the frequency f of the input signal IN based on the reference clock signal CK, and the 1 st counter circuit 20 sets the number of pulses n of the reference clock signal CK based on the period T' of the input signal IN the measurement period T_EThe 2 nd counter circuit 30 counts the number n of pulses of the input signal IN IN the measurement period T_INCounting is performed. The frequency of the reference clock signal CK is f_RThe number of pulses of the reference clock signal CK in the measurement period T is set to n_RThe 1 st frequency calculation circuit 40 calculates the 1 st frequency f by the above expression (2)₁The 2 nd frequency calculation circuit 50 calculates the 2 nd frequency f by the above equation (3)₂The frequency selection circuit 60 selects the 1 st frequency f₁Or 2 nd frequency f₂As the frequency f of the input signal IN.

That is, the frequency measuring device 1 of the present embodiment calculates the 1 st frequency f by the frequency measuring method₁Calculating the 2 nd frequency f by a periodic measurement method₂Selecting the 1 st frequency f₁Or 2 nd frequency f₂As a result, the frequency measurement range can be expanded. In addition, according to the frequency measuring device 1 of the present embodiment, the frequency at the 1 st frequency f by the frequency measuring method₁And the 2 nd frequency f based on the period measurement method₂Since the reference clock signal CK is used in common in the calculation of (2), a plurality of clock signals are not required, and cost reduction can be achieved.

IN the frequency measuring device 1 of the present embodiment, the measurement error calculating circuit 80 counts the number of pulses n of the input signal IN the measurement period T by the 2 nd counter circuit 30_INThe measurement error Err is calculated by the equation (4), and the frequency selection circuit 60 selects the 1 st frequency f based on the measurement error Err₁Or 2 nd frequency f₂As the frequency of the input signal IN. Specifically, if the absolute value of the measurement error Err is equal to or less than a predetermined threshold value VTE, the frequency selection circuit 60 selects the 1 st frequency f₁If the absolute value of the measurement error Err is larger than the threshold value VTE, the frequency selection circuit 60 selects the 2 nd frequency f₂. Thus, according to the present embodimentThe frequency measuring device 1 can select the 1 st frequency f by the frequency selection circuit 60 by setting the threshold VTE appropriately₁And 2 nd frequency f₂Of (3), since the measurement error is smaller, the frequency f of the input signal IN can be measured with high accuracy.

2. Micro-controller

Fig. 5 is a diagram showing the configuration of the microcontroller according to the present embodiment. As shown in fig. 5, the microcontroller 100 according to the present embodiment includes a reference clock signal generation circuit 110, a 1 st timer 120, a 2 nd timer 130, a memory 140, and a cpu (central Processing unit) 150. The 1 st timer 120, the 2 nd timer 130, the memory 140, and the CPU150 are connected to the bus 160. The microcontroller 100 may not have a part of these components, and may have other components.

The reference clock signal generation circuit 110, the 1 st timer 120, the 2 nd timer 130, the memory 140, and the CPU150 function as the frequency measurement device 1. That is, the microcontroller 100 includes the frequency measuring device 1.

The microcontroller 100 is connected to an oscillator 200 such as a quartz oscillator, and the reference clock signal generation circuit 110 oscillates the oscillator 200 to generate a reference clock signal CK having high frequency accuracy.

The 1 st timer 120 includes a comparison value register 121, a counter 122, a comparator 123, an output control unit 124, a capture register 125, and an edge detection unit 126.

The comparison value register 121 is set with a value for determining the measurement period T. For example, the number of pulses n of the reference clock signal CK in the measurement period T_RN is set in the comparison value register 121₁＝n_R-1。

After the measurement period T starts, the counter 122 is reset to 0, and counts the number of pulses of the reference clock signal CK.

The comparator 123 compares the count value CT1 of the counter 122 with the value of the comparison value register 121, and outputs a signal indicating whether or not both of them match.

The output control unit 124 generates a measurement period signal TS indicating the measurement period T, and outputs the signal to the outside of the microcontroller 100. The output control unit 124 changes the measurement period signal TS, which is output in synchronization with the reference clock signal CK, from a low level to a high level, starts the measurement period T, and when the output signal of the comparator 123 indicates that the count value CT1 matches the value of the comparison value register 121, changes the measurement period signal TS from a high level to a low level in synchronization with the reference clock signal CK, and ends the measurement period T.

The edge detector 126 samples an input signal IN input from the outside of the microcontroller 100 with the reference clock signal CK during the measurement period T, detects a rising edge or a falling edge of the input signal IN, and outputs an edge detection signal ED 1. IN this embodiment, the edge detection signal ED1 is a signal that transitions from low to high at the time of detection of a rising edge or a falling edge of the input signal IN and transitions from high to low after 1 cycle of the reference clock signal CK.

When the edge detection signal ED1 is at a high level, the capture register 125 acquires the count value CT1 at the rising edge of the reference clock signal CK and holds the count value CT1 as the capture value CP 1. The capture register 125 transmits the capture value CP1 acquired and held during the first high level period of the edge detection signal ED1 to the memory 140 via the bus 160 during the measurement period T, and stores the capture value CP in the memory 140 as the 1 st capture value 141 of the 1 st timer. In the measurement period T, the capture register 125 transfers the capture value CP1 acquired and held in the high level period of the edge detection signal ED1 from the 2 nd time onward to the memory 140 via the bus 160, and stores the capture value CP in the 1 st timer 2 nd capture value 142 in the memory 140. The 1 st timer 2 nd capture value 142 is updated to the latest capture value CP1 each time the edge detect signal ED1 goes high.

The 2 nd timer 130 has a counter 131, a capture register 132, and an edge detection section 133.

The counter 131 counts the number of pulses of the input signal IN the measurement period T.

The edge detector 133 samples the measurement period signal TS input from the outside of the microcontroller 100 by the input signal IN, detects a rising edge or a falling edge of the measurement period signal TS, and outputs an edge detection signal ED 2. IN the present embodiment, the edge detection signal ED2 is a signal that transitions from low to high at the detection time of the rising edge or the falling edge of the signal TS during the measurement period, and transitions from high to low after 1 cycle of the input signal IN.

When the edge detection signal ED2 is at a high level, the capture register 132 acquires the count value CT2 of the counter 131 at the rising edge of the input signal IN and holds the count value as the capture value CP 2. After the start of the measurement period T, the capture register 132 transmits the capture value CP2 acquired and held during the first high level period of the edge detection signal ED2 to the memory 140 via the bus 160, and stores the memory 140 as the 2 nd timer 1 st capture value 143. The capture register 132 also transmits the capture value CP2 acquired and held during the 2 nd high level of the edge detection signal ED2 to the memory 140 via the bus 160, and stores the capture value CP in the memory 140 as the 2 nd timer 2 nd capture value 144.

The CPU150 executes the frequency calculation program 145 stored IN the memory 140, and calculates the frequency f of the input signal IN by software processing. Specifically, first, after the measurement period T is completed, the CPU150 reads the 1 st timer 1 st capture value 141, the 1 st timer 2 nd capture value 142, the 2 nd timer 1 st capture value 143, and the 2 nd timer 2 nd capture value 144 from the memory 140 via the bus 160. Next, the 1 st capture value 141 is set to n for the 1 st timer_E1Setting the 1 st timer 2 nd capture value 142 to n_E2Setting the 1 st capture value 143 of the 2 nd timer to n_T1Setting the 2 nd timer capture value 144 to n_T2When n is greater than n, CPU150 sets to n_IN＝n_T2-n_T1Using the frequency f of the known reference clock signal CK_RAnd measuring the number of pulses n of the reference clock signal CK in the period T_RCalculating the 1 st frequency f by said formula (2)₁. Further, the CPU150 calculates the 2 nd frequency f by the above equation (6)₂. The CPU150 calculates the measurement error Err by the above equation (4). Then, the CPU150 selects the 1 st frequency f based on the measurement error Err₁Or 2 nd frequency f₂As the frequency f of the input signal IN. Specifically, if the absolute value of the measurement error Err is equal to or less than a predetermined threshold value VTE, the CPU150 selects the 1 st frequency f₁If the absolute value of the measurement error Err is larger than the threshold value VTE, the CPU150 selects the 2 nd frequency f₂。

The reference clock signal generation circuit 110 functions as the reference clock signal generation circuit 70 in fig. 1. The 1 st timer 120 and the memory 140 function as the measurement period setting circuit 10 and the 1 st counter circuit 20 in fig. 1. The 2 nd timer 130 and the memory 140 function as the 2 nd counter circuit 30 of fig. 1. That is, in the microcontroller 100, the reference clock signal generation circuit 70, the measurement period setting circuit 10, the 1 st counter circuit 20, and the 2 nd counter circuit 30 shown in fig. 1 are processed by hardware through logic circuits. However, at least a part of the processing of the measurement period setting circuit 10, the 1 st counter circuit 20, and the 2 nd counter circuit 30 may be performed by the CPU150 in a software manner.

The CPU150 and the memory 140 function as the 1 st frequency calculation circuit 40, the 2 nd frequency calculation circuit 50, the frequency selection circuit 60, and the measurement error calculation circuit 80 in fig. 1. That is, in the microcontroller 100, the processing of the 1 st frequency calculation circuit 40, the 2 nd frequency calculation circuit 50, the frequency selection circuit 60, and the measurement error calculation circuit 80 of fig. 1 is performed by the CPU150 in the form of software. This allows the microcontroller 100 to easily change the 1 st frequency f₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂The manner of selection of (a). However, at least a part of the processing of the 1 st frequency calculation circuit 40, the 2 nd frequency calculation circuit 50, the frequency selection circuit 60, and the measurement error calculation circuit 80 may be performed by a logic circuit in a hardware manner. Thus, the frequency measuring device 1 can perform the 1 st frequency f at high speed₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂At least a portion of the selection of (a).

Fig. 6 is a flowchart showing an example of the operation sequence of the microcontroller 100. As shown in fig. 6, first, the reference clock signal generation circuit 110 generates a reference clock signal CK (step S101).

Next, the output control unit 124 of the 1 st timer 120 raises the measurement period signal TS to start the measurement period T (step S102).

Next, the counter 122 of the 1 st timer 120 starts counting the number of pulses of the reference clock signal CK (step S103).

Next, the counter 131 of the 2 nd timer 130 starts counting the number of pulses of the input signal IN (step S104).

Next, the edge detector 133 of the 2 nd timer 130 detects a rising edge of the measurement period signal TS, and the capture register 132 acquires the count value CT2 of the counter 131 and stores the count value CT2 in the memory 140 as the 1 st capture value 143 of the 2 nd timer (step S105).

Then, the edge detector 126 of the 1 st timer 120 waits until the rising edge of the input signal IN is detected (step S106: NO). When the edge detector 126 detects a rising edge of the input signal IN (yes IN step S106), the capture register 125 of the 1 st timer 120 acquires the count value CT1 of the counter 122 and stores the 1 st capture value 141 IN the memory 140 (step S107).

Then, until the count value CT1 of the counter 122 of the 1 st timer 120 matches the value of the comparison value register 121 (no IN step S110), each time the edge detector 126 of the 1 st timer 120 detects the next rising edge of the input signal IN (yes IN step S108), the capture register 125 of the 1 st timer 120 acquires the count value CT1 of the counter 122 and stores the count value CT1 IN the memory 140 as the 1 st timer 2 nd capture value 142 (step S109).

Next, the output control unit 124 of the 1 st timer 120 lowers the measurement period signal TS to end the measurement period T (step S110).

Next, the edge detector 133 of the 2 nd timer 130 detects a falling edge of the measurement period signal TS, and the capture register 132 acquires the count value CT2 of the counter 131 and stores the count value CT2 in the memory 140 as the 2 nd timer 2 nd capture value 144 (step S111).

Next, the CPU150 calculates the 1 st frequency f₁2 nd frequency f₂And measuring the error Err (step S112). Specifically, the 2 nd timer 1 st capture value 143 is set to n_T1Setting timer 2, Capture value 144 to n_T2Is provided withIs n_IN＝n_T2-n_T1Using the frequency f of the reference clock signal CK_RAnd measuring the number of pulses n of the reference clock signal CK in the period T_RThe CPU150 calculates the 1 st frequency f by the above equation (2)₁. In addition, the 1 st timer 1 st capture value 141 is set to n_E1Setting the 1 st timer 2 nd capture value 142 to n_E2The CPU150 calculates the 2 nd frequency f by the above equation (6)₂. The CPU150 calculates the measurement error Err by the above equation (4).

Finally, when the measurement error Err is equal to or less than the threshold (step S114: YES), the CPU150 selects the 1 st frequency f₁When the measurement error Err is larger than the threshold value VTE (NO IN step S114) as the frequency f of the input signal IN (step S115), the CPU150 selects the 2 nd frequency f₂As the frequency f of the input signal IN (step S116).

Fig. 7 is a timing chart showing an example of waveforms of various signals in the microcontroller 100.

In the example of fig. 7, first, at time T1, the measurement period signal TS changes from low level to high level, and the measurement period T starts. After the count value CT1 of the pulse number of the reference clock signal CK is reset to 0, the count value CT1 is sequentially increased from 0 to 1 for each rising edge of the reference clock signal CK in the measurement period T.

At time t2, the input signal IN transitions from a low level to a high level. IN synchronization with the rising edge of the input signal IN, the count value CT2 changes from 0 to 1, and the edge detection signal ED2 transitions from low level to high level. Further, the edge detection signal ED1 transitions from the low level to the high level in synchronization with the rising edge of the reference clock signal CK at time t 3.

At time t4, the edge detection signal ED1 is at a high level, and therefore, the capture value CP1 is updated to the count value CT1, i.e., 1, in synchronization with the rising edge of the reference clock signal CK. The capture value CP1 is stored in memory 140 as timer 1 capture value 141.

At time t5, the input signal IN transitions from a low level to a high level. The edge detection signal ED2 is high, and therefore, the capture value CP2 is updated to the count value CT2, i.e., 1, IN synchronization with the rising edge of the input signal IN. The capture value CP2 is stored in memory 140 as timer 2, capture value 1 143. IN synchronization with the rising edge of the input signal IN, the count value CT2 changes from 1 to 2. Further, the edge detection signal ED1 transitions from the low level to the high level in synchronization with the rising edge of the reference clock signal CK at time t 6.

At time t7, the edge detection signal ED1 is at a high level, and therefore, the capture value CP1 is updated to the count value CT1, i.e., 4, in synchronization with the rising edge of the reference clock signal CK. The capture value CP1 is stored in memory 140 as timer 1, capture value 2 142.

Thereafter, until time t8, the count value CT2 is sequentially incremented by 1 IN synchronization with the rising edge of the input signal IN each time the input signal IN transitions from the low level to the high level, and the 1 st timer No. 2 capture value 142 is updated to the capture value CP1, that is, the count value CT1 IN synchronization with the rising edge of the reference clock signal CK, as IN the case of time t5 to time t 7.

At time t8, the input signal IN transitions from low level to high level, and the edge detection signal ED1 transitions from low level to high level IN synchronization with the rising edge of the reference clock signal CK at time t 9.

At time t10, the edge detection signal ED1 is at a high level, and therefore, the capture value CP1 is updated to the count value CT1, n, in synchronization with the rising edge of the reference clock signal CK₁-1. The capture value CP1 is stored in memory 140 as timer 1, capture value 2 142.

At time t11, the count value CT1 compares with the value n of the comparison value register 121₁Therefore, the measurement period signal TS changes from high level to low level, and the measurement period T ends.

At time t11, immediately after the signal TS changes from high level to low level during the measurement period, the input signal IN changes from low level to high level. IN synchronization with the rising edge of the input signal IN, the count value CT2 changes to n₂And, the edge detection signal ED2 transitions from low to high.

At time t12, the input signal IN transitions from a low level to a high level. The edge detect signal ED2 is highTherefore, IN synchronization with the rising edge of the input signal IN, the capture value CP2 is updated to the count value CT2, n₂. The capture value CP2 is stored in memory 140 as timer 2, capture value 1 143.

After time t12, the 1 st timer 1 st capture value 141 is set to n_E1Setting the 1 st timer 2 nd capture value 142 to n_E2When n is greater than n_E2-n_E1The pulse number corresponds to the number of pulses of the reference clock signal CK in the period T' from the time T2 to the time T8. In addition, the 1 st capture value 143 of the 2 nd timer is set to n_T1Setting the 2 nd timer capture value 144 to n_T2When n is greater than n_T2-n_T1Corresponds to the number of pulses of the input signal IN the measurement period T.

Then, the CPU150 calculates the 1 st frequency f using the equation (2)₁Calculating the 2 nd frequency f using said equation (6)₂The measurement error Err is calculated by the above equation (4). Then, the 1 st frequency f is selected based on the measurement error Err₁Or 2 nd frequency f₂As the frequency f of the input signal IN.

As described above, IN the microcontroller 100 according to the present embodiment, the 1 st timer 120 sets the measurement period T of the frequency f of the input signal IN based on the reference clock signal CK, and counts the number of pulses of the reference clock signal CK. The 1 st timer 120 sets a count value CT1 of the number of pulses of the reference clock signal CK at the detection time of the first rising edge or falling edge of the input signal IN the measurement period T to n_E1And stored in the memory 140. The 1 st timer 120 sets the count value CT1 at the detection time of the last rising edge or falling edge of the input signal IN the measurement period T to n_E2And stored in the memory 140. IN other words, the 1 st timer 120 sets a measurement period T of the frequency f of the input signal IN based on the reference clock signal CK, and counts the number of pulses n of the reference clock signal CK based on the period T' of the input signal IN the measurement period T_E＝n_E2-n_E1Counting is performed.

IN the microcontroller 100 according to the present embodiment, the 2 nd timer 130 counts the number of pulses of the input signal IN. In addition, the 2 nd timer 130N is a count value CT2 of the number of pulses of the input signal IN at the time of detecting the rising edge of the measurement period signal TS_T1And stored in the memory 140. The 2 nd timer 130 sets a count value CT2 at the detection time of the falling edge of the measurement period signal TS to n_T2And stored in the memory 140. IN other words, the 2 nd timer 130 counts the number of pulses n of the input signal IN IN the period T_IN＝n_T2-n_T1Counting is performed.

In the microcontroller 100 according to the present embodiment, the frequency of the reference clock signal CK is f_RThe number of pulses of the reference clock signal CK in the measurement period T is set to n_RThe CPU150 executes the frequency calculation program 145, thereby calculating the 1 st frequency f by the above equation (2)₁Calculating the 2 nd frequency f by said formula (3) or formula (6)₂Selecting the 1 st frequency f₁Or 2 nd frequency f₂As the frequency f of the input signal IN.

That is, the microcontroller 100 of the present embodiment calculates the 1 st frequency f by the frequency measurement method₁Calculating the 2 nd frequency f by a periodic measurement method₂Selecting the 1 st frequency f₁Or 2 nd frequency f₂As a result, the frequency measurement range can be expanded. Further, according to the microcontroller 100 of the present embodiment, the frequency measurement method is used at the 1 st frequency f₁And the 2 nd frequency f based on the period measurement method₂Since the reference clock signal CK is used in common in the calculation of (2), a plurality of clock signals are not required, and cost reduction can be achieved.

IN the microcontroller 100 according to the present embodiment, the CPU150 counts the number of pulses n of the input signal IN the measurement period T by the 2 nd timer 130_INThe measurement error Err is calculated by the formula (4), and the 1 st frequency f is selected based on the measurement error Err₁Or 2 nd frequency f₂As the frequency of the input signal IN. Specifically, if the absolute value of the measurement error Err is equal to or less than a predetermined threshold value VTE, the CPU150 selects the 1 st frequency f₁If the absolute value of the measurement error Err is larger than the threshold value VTE, the CPU150 selects the 2 nd frequency f₂. Thus, the micro-scale according to the present embodimentThe controller 100, by setting the threshold VTE appropriately, the CPU150 can select the 1 st frequency f₁And 2 nd frequency f₂Of (3), since the measurement error is smaller, the frequency f of the input signal IN can be measured with high accuracy.

Further, according to the microcontroller 100 of the present embodiment, the frequency measuring device 1 for measuring the frequency f of the input signal IN can be realized by the 1 st timer 120, the 2 nd timer 130, the memory 140, and the CPU150 having versatility. Furthermore, according to the microcontroller 100 of the present embodiment, the 1 st frequency f by the CPU150 can be easily changed by changing the frequency calculation program 145₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂The manner of selection of (a).

3. Electronic device

Fig. 8 is a functional block diagram showing a configuration example of the electronic apparatus of the present embodiment. Fig. 9 is a functional block diagram showing another configuration example of the electronic device of the present embodiment.

As shown in fig. 8 and 9, the electronic device 300 of the present embodiment includes a frequency measuring device 310 and a microcontroller 330. The electronic device 300 of the present embodiment may further include the vibrator 320, the operation unit 340, the communication unit 350, the display unit 360, and the sound output unit 370. The electronic device 300 according to the present embodiment may be configured such that a part of the components shown in fig. 8 or 9 is omitted or changed, or other components are added.

The frequency measurement device 310 and the microcontroller 330 perform various calculation processes and control processes in accordance with programs stored in a storage unit, not shown. Specifically, the frequency measurement device 310 and the microcontroller 330 perform various processes corresponding to operation signals from the operation unit 340, a process of controlling the communication unit 350 for data communication with other devices, a process of transmitting display signals for displaying various information on the display unit 360, a process of transmitting audio signals for outputting various sounds from the audio output unit 370, and the like.

IN particular, IN the present embodiment, the frequency measuring device 310 and the microcontroller 330 oscillate the external oscillator 320 to generate a reference clock signal, and measure the frequency of the input signal IN inputted from the outside based on the reference clock signal.

The operation unit 340 is an input device including operation keys, push-button switches, and the like, and outputs an operation signal corresponding to an operation performed by the user to the frequency measurement device 310 or the microcontroller 330.

The communication unit 350 performs various controls for establishing data communication between the frequency measurement device 310 or the microcontroller 330 and an external device.

The display unit 360 is a display device including an lcd (liquid Crystal display) and displays various information in accordance with an input display signal. The display unit 360 may be provided with a touch panel that functions as the operation unit 340.

The audio output unit 370 is constituted by a speaker or the like, and outputs audio based on an audio signal which is an output signal from the frequency measuring device 310 or the microcontroller 330.

For example, by applying the frequency measurement device 1 according to the above-described embodiment to the frequency measurement device 310 or applying the microcontroller 100 according to the above-described embodiment to the microcontroller 330, the electronic apparatus 300 having high frequency measurement accuracy can be realized.

As such an electronic device 300, various electronic devices are conceivable, and examples thereof include a digital multimeter, a vehicle speed sensor, and a tachometer.

Fig. 10 is a diagram showing an example of the configuration of a digital multimeter as an example of electronic device 300. As shown in fig. 10, digital multimeter 301 has vibrator 320, microcontroller 330, and display portion 360 shown in fig. 9.

The microcontroller 330 includes a reference clock signal generation circuit 331, a comparator 332, a measurement circuit 333, a cpu (central Processing unit)334, a memory 335, and an LCD drive circuit 336. The measurement circuit 333, the CPU334, and the memory 335 are connected to a bus 337.

The microcontroller 330 is connected to the oscillator 320 such as a quartz oscillator, and the reference clock signal generation circuit 331 oscillates the oscillator 320 to generate the reference clock signal CK with high frequency accuracy.

The comparator 332 compares an input signal IN such as a sine wave, a triangular wave, or a sawtooth wave with a reference voltage, and converts the input signal IN into a pulse-like input signal IN'.

The measurement circuit 333 counts the number of pulses of the reference clock signal CK IN the period T 'based on the input signal IN' among the measurement periods T set based on the reference clock signal CK, and transfers the count value to the memory 335 via the bus 337 for storage. The measurement circuit 333 counts the number of pulses of the input signal IN' during the measurement period T, and transmits the count value to the memory 335 via the bus 337 for storage.

The CPU334 reads various count values from the memory 335 via the bus 337, and calculates the 1 st frequency f obtained by the frequency measurement method using the above equation (2)₁. Further, the CPU334 calculates the 2 nd frequency f obtained by the period measurement method using the above equation (3) or (6)₂. The CPU334 calculates the measurement error Err using the above equation (4). Then, the CPU334 selects the 1 st frequency f according to the measurement error Err₁Or 2 nd frequency f₂The frequency f, which is the input signal IN, is transmitted to the LCD driver circuit 336 via the bus 337.

The reference clock signal generation circuit 331, the comparator 332, the measurement circuit 333, the CPU334, and the memory 335 function as the frequency measurement device 310 shown in fig. 8.

The LCD driving circuit 336 generates a display signal for driving the display unit 360, which is an LCD, and causing the display unit 360 to display information of the frequency f, based on the frequency f transmitted from the CPU334 via the bus 337.

The display unit 360 displays the frequency of the input signal IN measured by the frequency measuring device 310 based on the display signal output from the LCD drive circuit 336.

For example, by applying frequency measurement device 1 of the above-described embodiment to frequency measurement device 310, or by applying microcontroller 100 of the above-described embodiment to microcontroller 330, digital multimeter 301 having high frequency measurement accuracy can be realized.

The reference clock signal generation circuit 331, the CPU334, and the memory 335 correspond to the reference clock signal generation circuit 110, the CPU150, and the memory 140 of fig. 5, respectively. The measurement circuit 333 corresponds to the 1 st timer 120 and the 2 nd timer 130 in fig. 5.

The present invention is not limited to the embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, in the frequency measuring device 1 of the above embodiment, the reference clock signal generating circuit 70 oscillates the quartz resonator to generate the reference clock signal CK, and in the microcontroller 100 of the above embodiment, the reference clock signal generating circuit 110 oscillates the oscillator 200 such as the quartz resonator to generate the reference clock signal CK, but the reference clock signal generating circuits 70 and 110 may have other configurations. For example, the reference clock signal generation circuits 70 and 110 may be configured to generate the reference clock signal CK by oscillating a piezoelectric vibrator other than a quartz vibrator, a saw (surface Acoustic wave) resonator, a mems (micro Electro Mechanical systems) vibrator, or the like, or may be configured as a CR oscillation circuit.

In the frequency measurement device 1 or the microcontroller 100 according to the above-described embodiment, the reference clock signal CK is internally generated, but the reference clock signal CK may be input from the outside of the frequency measurement device 1 or the microcontroller 100.

In addition, in the frequency measuring device 1 or the microcontroller 100 of the above embodiment, the 1 st frequency f is also calculated₁And 2 nd frequency f₂However, in selecting the 1 st frequency f₁IN the case of the frequency f of the input signal IN, the 2 nd frequency f may not be calculated₂To calculate the 1 st frequency f₁At the selected 2 nd frequency f₂IN the case of the frequency f of the input signal IN, the 1 st frequency f may not be calculated₁And calculating the 2 nd frequency f₂。

The above embodiment and modification are examples, and are not limited thereto. For example, the embodiments and the modifications can be appropriately combined.

The present invention includes substantially the same structures as those described in the embodiments, for example, structures having the same functions, methods, and results, or structures having the same objects and effects. The present invention includes a structure obtained by substituting an extrinsic portion of the structure described in the embodiments. The present invention includes a structure that exhibits the same operational effects as the structures described in the embodiments or a structure that can achieve the same object. The present invention includes a structure obtained by adding a known technique to the structure described in the embodiment.

The following is derived from the above-described embodiment and the modifications.

One embodiment of a frequency measurement device measures a frequency of an input signal, the frequency measurement device including: the frequency measuring device measures the frequency of an input signal, and comprises: a measurement period setting circuit that sets a measurement period of the frequency of the input signal based on a reference clock signal; a 1 st counter circuit that counts the number of pulses of the reference clock signal in a period based on the input signal in the measurement period; a 2 nd counter circuit that counts the number of pulses of the input signal in the measurement period; a 1 st frequency calculation circuit for setting the frequency of the reference clock signal to f_RAnd the number of pulses of the reference clock signal in the measurement period is n_RThe count value of the 2 nd counter circuit is n_INThe count value of the 1 st counter circuit is n_EThe 1 st frequency calculation circuit passes through f₁＝f_R×n_IN/n_RCalculating the 1 st frequency f₁(ii) a 2 nd frequency calculation circuit which passes f₂＝f_R×n_IN/n_ECalculating the 2 nd frequency f₂(ii) a And a frequency selection circuit for selecting the 1 st frequency f₁Or the 2 nd frequency f₂As the frequency of the input signal.

In the frequency measuring device, the 1 st frequency calculating circuit calculates the 1 st frequency f by the frequency measuring method₁The frequency measurement method is to measure n of 1 cycle of the reference clock signal_RThe measurement period T of multiple length is n_R/f_RThe number of pulses n of the input signal in (1)_INThe frequency of the input signal is measured by counting. In addition, the 2 nd frequency calculation circuit calculates the 2 nd frequency f by a period measurement method₂The cycle measuring method is to perform n on the number of pulses of the input signal in the measuring period_INDuring the period of sub-countingNumber of pulses n of the reference clock signal_EThe time of 1 cycle of the input signal is measured by counting, and the frequency of the input signal is measured by taking the reciprocal thereof. Then, the frequency selection circuit selects the 1 st frequency f calculated by the frequency measurement method₁Or the 2 nd frequency f calculated by the periodic measurement method₂The frequency of the input signal can be set to a larger range. Further, according to the frequency measuring device, the frequency at the 1 st frequency f based on the frequency measuring method₁And the 2 nd frequency f based on the period measurement method₂Since the reference clock signal is used in common in the calculation of (2), a plurality of clock signals are not required, and cost reduction can be achieved.

One embodiment of the frequency measuring device may further include a measurement error calculation circuit that calculates a measurement error based on a count value of the 2 nd counter circuit, and the frequency selection circuit may select the 1 st frequency f based on the measurement error₁Or the 2 nd frequency f₂As the frequency of the input signal.

According to the frequency measuring device, the frequency selection circuit selects the 1 st frequency f according to the measurement error₁Or 2 nd frequency f₂Thus, the frequency of the input signal can be measured with high accuracy.

In one embodiment of the frequency measuring device, the measurement error may be ± 1/n_IN。

In one aspect of the frequency measurement device, the 1 st counter circuit may include a reference count value holding circuit that samples the input signal with the reference clock signal during the measurement period, detects a rising edge or a falling edge of the input signal, and holds the number of pulses of the reference clock signal from a start point of the measurement period to a detection point of the rising edge or the falling edge of the input signal.

One embodiment of the frequency measuring device may further include a reference clock signal generating circuit that generates the reference clock signal.

In one aspect of the frequency measuring device, the 1 st frequency calculating circuit, the 2 nd frequency calculating circuit, and the frequency selecting circuit are processed by software by a CPU.

According to the frequency measuring device, the 1 st frequency f can be easily changed₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂The manner of selection of (a).

In one aspect of the frequency measuring device, the 1 st frequency calculating circuit, the 2 nd frequency calculating circuit, and the frequency selecting circuit perform processing by a logic circuit.

According to the frequency measuring device, the 1 st frequency f can be performed at high speed₁Calculation of (2) frequency f₂And 1 st frequency f₁Or 2 nd frequency f₂Selection of (2).

One embodiment of the microcontroller includes one embodiment of the frequency measurement device.

One embodiment of the electronic device includes one embodiment of the frequency measurement device or one embodiment of the microcontroller.