阅读说明：本技术 包括延迟电路的高速触发器电路 (High speed flip-flop circuit including delay circuit ) 是由 姜秉坤 金昌泛 李达熙 金佑奎 于 2021-06-23 设计创作，主要内容包括：提供了触发器。该触发器包括主锁存器和从锁存器。主锁存器包括延迟电路,该延迟电路被配置为接收时钟信号并生成第一内部信号,并且被配置为通过基于第一内部信号锁存数据信号来生成内部输出信号。从锁存器被配置为通过锁存内部输出信号来生成最终信号。延迟电路还被配置为当时钟信号具有第一逻辑电平时,通过将时钟信号延迟延迟时间来生成第一内部信号,并且当时钟信号具有第二逻辑电平时,基于数据信号生成第一内部信号。(A trigger is provided. The flip-flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate a first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level, and generate the first internal signal based on the data signal when the clock signal has a second logic level.)

1. A flip-flop, comprising:

a master latch including a delay circuit configured to receive a clock signal and generate a first internal signal, and configured to generate an internal output signal by latching a data signal based on the first internal signal; and

a slave latch configured to generate a final signal by latching the internal output signal,

wherein the delay circuit is further configured to:

generating the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level, an

Generating the first internal signal based on the data signal when the clock signal has a second logic level.

2. The flip-flop of claim 1, wherein the slave latch comprises a logic circuit configured to:

generating a second internal signal based on the clock signal,

generating a second internal signal having the second logic level when the clock signal has the first logic level, an

When the clock signal has a second logic level, a second internal signal having the same logic level as the data signal is generated.

3. The flip-flop of claim 2, wherein the master latch is configured to:

generating an internal output signal having an inverted logic level of a logic level of the data signal in a period in which the clock signal has the first logic level and a period until a setup time elapses after the clock signal transitions to the second logic level, and

maintaining a logic level of the internal output signal at a logic level determined based on a logic level of a data signal received before the setup time elapses, during a period after the setup time elapses, and

wherein the setup time is less than the delay time.

4. The flip-flop of claim 3, wherein the slave latch is further configured to:

when the clock signal has the first logic level, maintaining the logic level of the final signal at the logic level of the final signal before the clock signal transitions to the first logic level, an

When the clock signal has the second logic level, a final signal having an inverted logic level of the internal output signal is output.

5. The flip-flop of claim 4, wherein the delay circuit comprises:

a first logic circuit configured to receive a scan input signal, a scan enable signal, and the clock signal; and

a second logic circuit configured to receive the internal output signal, the clock signal, and an output signal of the first logic circuit and output the first internal signal.

6. The flip-flop of claim 4, wherein the slave latch comprises a third logic circuit configured to receive the internal output signal and the clock signal and generate the second internal signal.

7. The flip-flop of claim 6, wherein the delay circuit comprises:

a fourth logic circuit configured to receive a scan input signal and a scan enable signal and enabled in response to the clock signal and the second internal signal; and

a fifth logic circuit configured to receive the clock signal, the second internal signal, and a signal of an internal node of the third logic circuit, and output the first internal signal.

8. The flip-flop of claim 7, wherein the third logic circuit comprises:

a first N-type transistor having a gate terminal receiving the clock signal, a drain terminal connected to a node generating the second internal signal, and a source terminal connected to the internal node; and

a second N-type transistor having a gate terminal receiving the internal output signal, a drain terminal connected to the internal node, and a source terminal connected to a ground node.

9. A flip-flop, comprising:

a first latch configured to receive a data signal and a clock signal and output an internal output signal; and

a second latch configured to output a final signal by latching the internal output signal in response to the clock signal,

wherein the first latch includes a delay circuit configured to generate a first internal signal, wherein a logic level of the first internal signal maintains a delay time after the clock signal transitions, and

wherein the first latch is further configured to generate the internal output signal by latching the data signal in response to the first internal signal.

10. The flip-flop of claim 9, wherein the delay circuit comprises a first logic circuit and a second logic circuit,

wherein the first logic circuit comprises: an AND gate configured to receive a scan enable signal and a scan input signal and output a first signal by performing an AND operation on the scan enable signal and the scan input signal; and a NOR gate configured to receive the first signal and the clock signal, and output a second signal by performing a NOR operation on the first signal and the clock signal, and

wherein the second logic circuit comprises: an AND gate configured to receive the internal output signal and the clock signal and output a third signal by performing an AND operation on the internal output signal and the clock signal; and a nor gate configured to receive the second signal and the third signal and output the first internal signal by performing a nor operation on the third signal and the second signal.

11. The flip-flop of claim 9, wherein the second latch comprises:

a third logic circuit configured to receive the internal output signal and the clock signal and output a second internal signal;

a fourth logic circuit configured to receive the inverted signal, the clock signal, and the second internal signal, and output an inverted final signal;

a first inverter configured to receive an inverted final signal and output the inverted signal by inverting the inverted final signal; and

a second inverter configured to receive the inverted final signal and output the final signal by inverting the inverted final signal.

12. The flip-flop of claim 11, wherein the first latch further comprises a fifth logic circuit configured to receive the second internal signal, the data signal, an inverted scan enable signal, and the first internal signal, and output an internal output signal.

13. The flip-flop of claim 11, wherein the third logic circuit comprises:

a sixth logic circuit comprising an AND gate configured to receive the clock signal and the internal output signal and output a fourth signal by performing an AND operation on the clock signal and the internal output signal; and

a seventh logic circuit including a NOR gate configured to receive a reset signal and the fourth signal and output the second internal signal by performing a NOR operation on the reset signal and the fourth signal.

14. The flip-flop of claim 9, wherein the second latch comprises an eighth logic circuit configured to receive the internal output signal and the clock signal and output a second internal signal.

15. The flip-flop of claim 14, wherein the eighth logic circuit comprises:

a ninth P-type transistor having a gate terminal receiving the internal output signal, a first terminal connected to a power supply node, and a second terminal connected to a fifth node;

a tenth P-type transistor having a gate terminal receiving the clock signal, a first terminal connected to the power supply node, and a second terminal connected to the fifth node;

an eighth N-type transistor having a gate terminal receiving the clock signal, a first terminal connected to the fifth node, and a second terminal connected to a sixth node; and

a ninth N-type transistor having a gate terminal receiving the internal output signal, a first terminal connected to the sixth node, and a second terminal connected to a ground node.

16. The flip-flop of claim 15, wherein the delay circuit comprises a circuit portion connected to the sixth node and configured to operate as an inverter, wherein the inverter receives the data signal as an input from the sixth node when the clock signal has a logic high level.

17. The flip-flop of claim 16, wherein the delay circuit further comprises a ninth logic circuit configured to receive a scan enable signal and a scan input signal, the ninth logic circuit being enabled in response to the clock signal and comprising an output connected to a seventh node, and

the circuit part includes:

an eleventh P-type transistor having a gate terminal receiving the second internal signal, a first terminal connected to the power supply node, and a second terminal connected to the seventh node;

a tenth N-type transistor having a gate terminal receiving the clock signal;

an eleventh N-type transistor having a gate terminal connected to the sixth node; and

a tenth logic circuit whose input terminal is connected to the seventh node and generates the first internal signal by inverting the signal of the seventh node,

wherein the tenth N-type transistor and the eleventh N-type transistor are connected in series to form a third series structure, a first end of the third series structure being connected to the ground node, and a second end of the third series structure being connected to the seventh node.

18. The flip-flop of claim 17, further comprising:

a twelfth P-type transistor having a gate terminal receiving the internal output signal, a first terminal connected to the power supply node, and a second terminal connected to the sixth node.

19. The flip-flop of claim 14, wherein the eighth logic circuit comprises:

a ninth P-type transistor having a gate terminal receiving the internal output signal, a first terminal connected to the eighth node, and a second terminal connected to the fifth node;

a tenth P-type transistor having a gate terminal receiving the clock signal, a first terminal connected to the eighth node, and a second terminal connected to the fifth node;

a thirteenth P-type transistor having a gate terminal receiving the reset signal, a first terminal connected to the power supply node, and a second terminal connected to the eighth node;

an eighth N-type transistor having a gate terminal receiving the clock signal, a first terminal connected to the fifth node, and a second terminal connected to a sixth node;

a ninth N-type transistor having a gate terminal receiving the internal output signal, a first terminal connected to the sixth node, and a second terminal connected to a ground node; and

a twelfth N-type transistor having a gate terminal receiving the reset signal, a first terminal connected to the ground node, and a second terminal connected to the fifth node.

20. A flip-flop, comprising:

a first or-and-inverter OAI21 logic circuit configured to receive a scan input signal, an inverted scan enable signal, and an inverted clock signal and output an intermediate signal;

a second OAI21 logic circuit configured to receive the internal output signal, the inverted clock signal, and the intermediate signal and output a first internal signal;

an OAI31 logic circuit configured to receive a second internal signal, a scan enable signal, a data signal, and the first internal signal and output the internal output signal;

a NOR2 logic circuit configured to receive the inverted clock signal and the internal output signal and output the second internal signal;

an and-or-inverter AOI21 logic circuit configured to receive the inverted signal, the inverted clock signal, and the second internal signal and output an inverted final signal;

a first inverter configured to output the inverted signal by inverting the inverted final signal; and

a second inverter configured to output a final signal by inverting the inverted final signal.

Technical Field

The present disclosure relates to flip-flop circuits, and more particularly, to high-speed flip-flop circuits including delay circuits.

Background

With high performance and high integration of semiconductor integrated circuits, the number of flip-flops included in the semiconductor integrated circuits is increasing. Flip-flops are used as data storage elements, and these data storage elements are used to store states. Flip-flops are electronic circuits that are capable of storing and holding one bit of information and are the basic elements of sequential logic circuits. The frequency of the clock signal used as a metric indicative of the performance of the semiconductor integrated circuit is important because flip-flops can transfer data in response to the active edges of the clock signal.

Disclosure of Invention

The present disclosure relates to a high-speed flip-flop circuit including a delay circuit, and provides a flip-flop circuit capable of increasing a frequency of a clock signal by latching a data signal in response to a first internal signal.

According to an aspect of the inventive concept, there is provided a flip-flop including: a master latch including a delay circuit configured to receive a clock signal and generate a first internal signal, and configured to generate an internal output signal by latching a data signal based on the first internal signal; and a slave latch configured to generate a final signal by latching the internal output signal, wherein the delay circuit is further configured to generate a first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level, and to generate the first internal signal based on the data signal when the clock signal has a second logic level.

According to another aspect of the inventive concept, there is provided a flip-flop including: a first latch configured to receive a data signal and a clock signal and output an internal output signal; and a second latch configured to output a final signal by latching the internal output signal in response to the clock signal, wherein the first latch includes a delay circuit configured to generate the first internal signal by delaying the internal output signal by a delay time. The first latch is further configured to generate an internal output signal by latching the data signal in response to the first internal signal.

According to another aspect of the inventive concept, there is provided a flip-flop including: a first OR-AND-inverter (OAI)21 logic circuit configured to receive a scan input signal, an inverted scan enable signal, AND an inverted clock signal AND output an intermediate signal; a second OAI21 logic circuit configured to receive the inverted internal output signal, the inverted clock signal, and the intermediate signal, and to output a first internal signal; an OAI31 logic circuit configured to receive the second internal signal, the scan enable signal, the data signal, and the first internal signal, and output an internal output signal; a NOR2 logic circuit configured to receive the inverted clock signal and the internal output signal and output a second internal signal; an AND-OR-inverter (AOI)21 logic circuit configured to receive the inverted signal, the inverted clock signal, AND the second internal signal, AND output an inverted final signal; a first inverter configured to output an inverted signal by inverting the inverted final signal; and a second inverter configured to generate a final signal by inverting the inverted final signal.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram of a flip-flop according to an example embodiment of the inventive concept;

FIG. 2 is a schematic diagram depicting an integrated circuit operating in a normal operating mode and a scan test mode;

fig. 3 is a block diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 4 is a circuit diagram of a delay circuit according to an example embodiment of the inventive concepts;

fig. 5 is a circuit diagram of an and-or-inverter (AOI31) logic circuit according to an example embodiment of the inventive concept;

fig. 6 is a circuit diagram of a second AOI21 logic circuit according to an example embodiment of the inventive concept;

FIG. 7A is a circuit diagram of an AOI31 logic circuit according to an example embodiment of the present inventive concept;

FIG. 7B is a circuit diagram of an AOI31 logic circuit according to an example embodiment of the present inventive concept;

fig. 8 is a circuit diagram of a slave latch according to an example embodiment of the inventive concept;

fig. 9A is a circuit diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 9B is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 9C is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 10A is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 10B is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 10C is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 10D is a circuit diagram of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 10E is a circuit diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 11 is a circuit diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 12A is a circuit diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 12B is a circuit diagram of a flip-flop according to an example embodiment of the inventive concept;

fig. 13A and 13B are circuit diagrams for describing a normal operation mode of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 14A and 14B are circuit diagrams for describing a normal operation mode of a flip-flop according to an exemplary embodiment of the inventive concept;

fig. 15 is a timing diagram of a flip-flop according to an exemplary embodiment of the inventive concept; and is

Fig. 16 is a timing diagram of a flip-flop according to an example embodiment.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram of a flip-flop (or flip-flop circuit) 10 according to an example embodiment of the inventive concepts. Referring to fig. 1, a flip-flop 10 according to an example embodiment of the inventive concept may be a scan flip-flop configured to receive a data signal D or a scan input signal SI and a scan enable signal SE and to output a final signal (or a final output signal) Q in response to a clock signal CK.

The scan enable signal SE may indicate the first operation mode or the second operation mode according to a logic level of the scan enable signal SE. For example, when the scan enable signal SE has a first logic level (e.g., a logic low level), the scan enable signal SE may indicate a first operation mode, and when the scan enable signal SE has a second logic level (e.g., a logic high level), the scan enable signal SE may indicate a second operation mode. Here, the logic level may represent a logic low level (e.g., '0') or a logic high level (e.g., '1'). Further, a logic level may mean a voltage level. For example, the first operation mode may be a normal operation mode in which data is transferred, and the second operation mode may be a scan test mode in which a test operation is performed. However, this is merely an embodiment of the inventive concept, and in some embodiments, the first operation mode may be a scan test mode and the second operation mode may be a normal operation mode.

When the scan enable signal SE indicates the normal operation mode, the flip-flop 10 may perform a normal operation of providing the final signal Q by latching the data signal D. When the scan enable signal SE indicates the scan test mode, the flip-flop 10 may perform a scan test operation of providing the final signal Q by latching the scan input signal SI.

The flip-flop 10 according to an example embodiment of the inventive concept may include a master latch 200 and a slave latch 300. The master latch 200 may receive the data signal D or the scan input signal SI in response to the scan enable signal SE and output an internal output signal Qm. The slave latch 300 may receive the internal output signal Qm and output a final signal Q.

The master latch 200 according to an example embodiment of the inventive concepts may include the delay circuit 100. As described below with reference to fig. 3, the delay circuit 100 may receive the clock signal CK and output the first internal signal DCK. By latching the data signal D based on the first internal signal DCK, the master latch 200 can ensure a reduction in setup time for latching the data signal D. The setup time may indicate a minimum time during which the value of the data signal D should be constantly maintained before the active edge of the clock signal CK in order to output the data signal D as the final signal Q.

The slave latch 300 may receive the clock signal CK and output a second internal signal CKb indicating an inverted value of the clock signal CK. For example, as described below with reference to fig. 14A, when the clock signal CK has a logic low level, the second internal signal CKb may have a logic high level. The second internal signal CKb may be a signal generated at an internal node of the slave latch 300. The flip-flop 10 according to an example embodiment of the inventive concept may secure the second internal signal CKb from the internal node of the slave latch 300 without including a separate clock inverter configured to invert the clock signal CK, thereby saving power consumed by the clock inverter.

Fig. 2 is a schematic diagram for describing the integrated circuit 100 operating in a normal operation mode and a scan test mode. Referring to fig. 2, an integrated circuit 100 may include a combinational logic circuit 1 and a plurality of scan flip-flops 10-1, 10-2, and 10-3. The combinational logic circuit 1 can output the same output data with respect to the same input data. The plurality of scan flip-flops 10-1, 10-2, and 10-3 may be sequential logic circuits. Sequential logic circuitry may include memory elements. Although the same input data is input, the sequential logic circuit may output different output data according to the memory state.

When the scan enable signal SE indicates the normal operation mode, data may be transmitted along the data path and the original functions of the integrated circuit 100 may be performed. When the scan enable signal SE indicates the scan test mode, data may be transmitted along the scan test path, thereby performing a scan test operation. In the scan test operation, an error occurring in the sequential logic circuit may be checked by comparing a scan test pattern (pattern) STP with the output pattern OP. The scan test pattern STP may be an input bitstream and the output pattern OP may be an output bitstream corresponding to the scan test pattern STP.

Fig. 3 is a block diagram of a flip-flop 10a according to an exemplary embodiment of the inventive concept. Fig. 4 is a circuit diagram of a delay circuit 100a according to an example embodiment of the inventive concepts. Fig. 5 is a circuit diagram of AOI31 logic circuit 220a according to an example embodiment of the inventive concept.

Referring to fig. 3, the flip-flop 10a may include a master latch 200a and a slave latch 300 a. Master latch 200a may include delay circuit 100 a. The delay circuit 100a may receive the scan input signal SI, the scan enable signal SE, the clock signal CK, and the internal output signal Qm, which is an output signal of the master latch 200a, and output a first internal signal DCK.

Delay circuit 100a may include two and-or-inverter (AOI)21 logic circuits, e.g., first AOI21 logic circuit 110 and second AOI21 logic circuit 120. The AOI21 logic circuit may include an AND (AND) gate configured to receive two signals as inputs, an OR (OR) gate configured to receive an output signal of the AND gate AND another signal as inputs, AND an inverter, connected in series.

For example, first AOI21 logic circuit 110 may receive as inputs a scan input signal SI, a scan enable signal SE, and a clock signal CK, and output an intermediate signal F. Referring to fig. 4, in an example embodiment, first AOI21 logic circuit 110 may include an and gate 111, and gate 111 configured to receive as inputs a scan input signal SI and a scan enable signal SE. First AOI21 logic circuit 110 may include a NOR (NOR) gate 112, the NOR gate 112 configured to receive as inputs the output signal of and gate 111 and clock signal CK, and output an intermediate signal F.

Referring to fig. 3, the second AOI21 logic circuit 120 may receive as inputs the internal output signal Qm, the clock signal CK and the intermediate signal F as output signals of the master latch 200a, and output a first internal signal DCK. Referring to fig. 4, second AOI21 logic circuit 120 may include and gate 121, and gate 121 configured to receive internal output signal Qm and clock signal CK as inputs. The second AOI21 logic circuit 120 may include a nor gate 122, the nor gate 122 being configured to receive as inputs the output signal of the and gate 121 and the intermediate signal F, and to output a first internal signal DCK.

Referring to fig. 3, the master latch 200a may include a first inverter 400. The first inverter 400 may receive the scan enable signal SE as an input and output an inverted scan enable signal nSE. However, the present embodiment is not limited thereto, and the first inverter 400 may be located outside the master latch 200 a.

Master latch 200a may include AOI31 logic 220 a. In an example embodiment, AOI31 logic may include an and gate configured to receive three signals as inputs, an or gate configured to receive an output signal of the and gate and another signal as inputs, and an inverter, connected in series.

The AOI31 logic circuit 220a may receive as inputs the second internal signal CKb, the data signal D, the inverted scan enable signal nSE, and the first internal signal DCK output from the latch 300a, and output an internal output signal Qm. Referring to fig. 5, in an example embodiment, the AOI31 logic circuit 220a may include an and gate 221, the and gate 221 configured to receive as inputs the second internal signal CKb, the data signal D, and the inverted scan enable signal nSE. The AOI31 logic circuit 220a may include a nor gate 222, the nor gate 222 configured to receive as inputs the output signal of the and gate 221 and the first internal signal DCK, and output an internal output signal Qm.

Referring to fig. 3, the slave latch 300a may include a two-input NAND (NAND) gate 310 a. The two-input nand gate 310a may receive the internal output signal Qm and the clock signal CK as inputs and output a second internal signal CKb. When the clock signal CK has the first logic level, the two-input nand gate 310a may invert the second internal signal CKb from the first logic level to the second logic level. For example, when the clock signal CK has a logic low level, the second internal signal CKb may have a logic high level through the two-input nand gate 310 a. The flip-flop 10a according to an exemplary embodiment of the inventive concept can provide the second internal signal CKb by inverting a specific logic level of the clock signal CK even if a clock inverter dedicated to inverting the clock signal CK is not included. Therefore, the power consumed by the clocked inverter can be saved.

Slave latch 300a may include or-and-inverter (OAI)21 logic 320. In an example embodiment, the OAI21 logic circuit may include an or gate configured to receive two signals as inputs, an and gate configured to receive an output signal of the or gate and another signal as inputs, and an inverter, connected in series. The OAI21 logic circuit 320 may receive an inverted signal Qi obtained by inverting the output signal QN of the OAI21 logic circuit 320, the clock signal CK, and the second internal signal CKb, and output the output signal QN.

The slave latch 300a may include a second inverter 330 and a third inverter 340. Second inverter 330 may receive output signal QN and provide inverted signal Qi to OAI21 logic circuit 320 by inverting output signal QN. The third inverter 340 may receive the output signal QN and output a final signal by inverting the output signal QN.

Fig. 6 is a circuit diagram of a second AOI21 logic circuit 120 according to an example embodiment of the inventive concept. Referring to fig. 6, the second AOI21 logic circuit 120 may include a pull-up circuit 123 and a pull-down circuit 124. The pull-up circuit 123 may generate the first internal signal DCK of a logic high level, and the pull-down circuit 124 may generate the first internal signal DCK of a logic low level.

In example embodiments, the transistor may include an active pattern (active pattern). The active pattern may have, for example, a fin (fin) shape, and a transistor formed by the active pattern and the gate electrode may be referred to as a fin field effect transistor (FinFET). However, the present embodiment is not limited thereto, and the active pattern may include a nanosheet (nanosheet). The transistor formed by the nanosheets and the gate electrode may be referred to as a multi-bridge channel field effect transistor (MBCFET). Further, a forklike field effect transistor (ForkFET) having a structure in which a nanosheet for a P-type transistor is separated from a nanosheet for an N-type transistor by a dielectric wall such that the N-type transistor and the P-type transistor are relatively close to each other may be included. In addition, the cell may include a Vertical Field Effect Transistor (VFET) having a structure in which source/drain regions are separated from each other by a channel region therebetween, and a gate electrode surrounds the channel region. Further, the transistor may be one of FETs such as a Complementary Field Effect Transistor (CFET), a Negative Capacitance Field Effect Transistor (NCFET), and a Carbon Nanotube (CNT) field effect transistor. In the specification, the transistor may be one of a bipolar junction transistor and other three-dimensional transistors. In the specification, a P-type transistor may denote a transistor formed in a P-type active region, and an N-type transistor may denote a transistor formed in an N-type active region.

The pull-up circuit 123 may include a plurality of P-type transistors, for example, a first P-type transistor P1 through a fourth P-type transistor P4. The intermediate signal F may be input to a gate terminal of the first P-type transistor P1, the clock signal CK may be input to a gate terminal of the second P-type transistor P2, the internal output signal Qm may be input to a gate terminal of the third P-type transistor P3, and the intermediate signal F may be input to a gate terminal of the fourth P-type transistor P4.

The first P-type transistor P1 and the second P-type transistor P2 may be connected in series to form a series structure. For example, as shown in fig. 6, the drain terminal of the first P-type transistor P1 may be connected to the source terminal of the second P-type transistor P2. However, the present embodiment is not limited thereto, and the source terminal of the first P-type transistor P1 may be connected to the drain terminal of the second P-type transistor P2. One end of the series structure may be connected to the power supply node VDD, and the other end of the series structure may be connected to the first node M1 outputting the first internal signal DCK.

The third P-type transistor P3 and the fourth P-type transistor P4 may be connected in series to form a series structure. For example, as shown in fig. 6, a drain terminal of the third P-type transistor P3 may be connected to a source terminal of the fourth P-type transistor P4. However, the present embodiment is not limited thereto, and a source terminal of the third P-type transistor P3 may be connected to a drain terminal of the fourth P-type transistor P4. One end of the series structure may be connected to the power supply node VDD, and the other end of the series structure may be connected to the first node M1.

The pull-down circuit 124 may include first to third N-type transistors N1 to N3. The intermediate signal F may be input to a gate terminal of the first N-type transistor N1, the clock signal CK may be input to a gate terminal of the second N-type transistor N2, and the internal output signal Qm may be input to a gate terminal of the third N-type transistor N3.

A source terminal of the first N-type transistor N1 may be connected to the ground node, and a drain terminal of the first N-type transistor N1 may be connected to the first node M1.

The second N-type transistor N2 and the third N-type transistor N3 may be connected in series to form a series structure. For example, as shown in fig. 6, the source terminal of the second N-type transistor N2 may be connected to the drain terminal of the third N-type transistor N3. However, the present embodiment is not limited thereto, and the drain terminal of the second N-type transistor N2 may be connected to the source terminal of the third N-type transistor N3. One end of the series structure may be connected to a ground node, and the other end of the series structure may be connected to the first node M1.

The second AOI21 logic circuit 120 according to an example embodiment of the inventive concept may include a pull-up circuit 123, the pull-up circuit 123 including a first P-type transistor P1 and a fourth P-type transistor P4 configured to receive the intermediate signal F, and thus, a series structure including the second P-type transistor P2 and a series structure including the third P-type transistor P3 may be connected to different power supply nodes, respectively. Therefore, the degree of freedom of wiring can be improved.

Fig. 7A is a circuit diagram of AOI31 logic 220a-1 according to an example embodiment of the inventive concept. Referring to FIG. 7A, AOI31 logic circuit 220a-1 may include a pull-up circuit 223-1 and a pull-down circuit 224-1. The pull-up circuit 223-1 may generate the internal output signal Qm of a logic high level, and the pull-down circuit 224-1 may generate the internal output signal Qm of a logic low level.

The pull-up circuit 223-1 may include fifth to eighth P-type transistors P5a to P8 a. The first internal signal DCK may be input to the gate terminal of the fifth P-type transistor P5a, the source terminal of the fifth P-type transistor P5a may be connected to the power supply node VDD, and the drain terminal of the fifth P-type transistor P5a may be connected to the second node M2. The inverted scan enable signal nSE may be input to a gate terminal of the sixth P-type transistor P6a, a source terminal of the sixth P-type transistor P6a may be connected to the second node M2, and a drain terminal of the sixth P-type transistor P6a may be connected to the third node M3. The data signal D may be input to a gate terminal of the seventh P-type transistor P7a, a source terminal of the seventh P-type transistor P7a may be connected to the second node M2, and a drain terminal of the seventh P-type transistor P7a may be connected to the third node M3. The second internal signal CKb may be input to a gate terminal of the eighth P-type transistor P8a, a source terminal of the eighth P-type transistor P8a may be connected to the power supply node VDD, and a drain terminal of the eighth P-type transistor P8a may be connected to the third node M3. The third node M3 may be a node that outputs the internal output signal Qm.

The pull-down circuit 224-1 may include fourth to seventh N-type transistors N4a to N7 a. The first internal signal DCK may be input to the gate terminal of the fourth N-type transistor N4 a. The data signal D may be input to the gate terminal of the fifth N-type transistor N5 a. The second internal signal CKb may be input to a gate terminal of the sixth N-type transistor N6 a. The inverted scan enable signal nSE may be input to the gate terminal of the seventh N-type transistor N7 a. The fifth N-type transistor N5a through the seventh N-type transistor N7a may be connected in series to form a series structure. For example, as shown in fig. 7A, a drain terminal of the fifth N-type transistor N5a may be connected to the third node M3, and a source terminal of the fifth N-type transistor N5a may be connected to a drain terminal of the sixth N-type transistor N6 a. A source terminal of the sixth N-type transistor N6a may be connected to a drain terminal of the seventh N-type transistor N7 a. The source terminal of the seventh N-type transistor N7a may be connected to the ground node. However, the present embodiment is not limited thereto, and there may be various orders in which the fifth N-type transistor N5a through the seventh N-type transistor N7a are connected in series.

As described below with reference to fig. 13B and 14B, in the flip-flop according to the example embodiment of the inventive concept, when the clock signal CK has a logic high level, the first and second internal signals DCK and CKb may have the same logic level as the data signal D. Otherwise, as described below with reference to fig. 13B and 14B, when the clock signal CK has a logic low level, the first internal signal DCK may have a logic low level, and the second internal signal CKb may have a logic high level. For example, in the AOI31 logic circuit 220a-1, there may be no case where the first internal signal DCK has a logic high level and the second internal signal CKb has a logic low level. Therefore, even when the source terminal of the eighth P-type transistor P8a is not connected to the second node M2, the AOI31 logic circuit 220a-1 may operate normally. Therefore, the source terminal of the eighth P-type transistor P8a may be connected to a separate power supply node, thereby increasing the overall wiring freedom of the flip-flop.

FIG. 7B is a circuit diagram of AOI31 logic 220a-2, according to an example embodiment of the present inventive concept. Referring to FIG. 7B, AOI31 logic circuit 220a-2 may include a pull-up circuit 223-2 and a pull-down circuit 224-2.

Unlike AOI31 logic circuit 220a-1 of FIG. 7A, the source terminals of the eighth P-type transistor P8b in AOI31 logic circuit 220a-2 may be commonly connected to the second node M2 to which the source terminals of the sixth P-type transistor P6b and the seventh P-type transistor P7b are connected.

In addition, a drain terminal of the sixth N-type transistor N6b in the AOI31 logic circuit 220a-2 may be connected to the third node M3 outputting the internal output signal Qm, and a source terminal of the sixth N-type transistor N6b may be connected to the fourth node M4. A drain terminal of the fourth N-type transistor N4b may be connected to the fourth node M4, and a source terminal of the fourth N-type transistor N4b may be connected to the ground node. The fifth N-type transistor N5b and the seventh N-type transistor N7b may be connected in series to form a series structure. One end of the series structure may be connected to the fourth node M4, and the other end of the series structure may be connected to a ground node.

As described below with reference to fig. 13B and 14B, in the flip-flop according to the example embodiment of the inventive concept, when the clock signal CK has a logic high level, the first and second internal signals DCK and CKb may have the same logic level as the data signal D. Otherwise, as described below with reference to fig. 13B and 14B, when the clock signal CK has a logic low level, the first internal signal DCK may have a logic low level, and the second internal signal CKb may have a logic high level. That is, in the AOI31 logic circuit 220a-2, when the first internal signal DCK has a logic high level, the second internal signal CKb may also have a logic high level.

Therefore, even when the drain terminal of the fourth N-type transistor N4b is not connected to the third node M3 but is connected to the fourth node M4, the AOI31 logic circuit 220a-2 may operate normally. Accordingly, the drain terminal of the fourth N-type transistor N4b may be selectively connected to the third node M3 or the fourth node M4, thereby increasing the degree of freedom in wiring of the flip-flop.

Fig. 8 is a circuit diagram of a slave latch 300a according to an example embodiment of the inventive concept. Referring to fig. 8, the slave latch 300a may receive the internal output signal Qm and the clock signal CK as inputs and output a final signal Q.

The slave latch 300a may include a two-input nand gate 310 a. The nand gate 310a may receive the internal output signal Qm and the clock signal CK as inputs and output a second internal signal CKb. When the clock signal CK has a specific logic level, the second internal signal CKb may have a logic level opposite to that of the clock signal CK. For example, when the clock signal CK has a logic low level, the second internal signal CKb may have a logic high level regardless of the internal output signal Qm. Accordingly, even in the case of not including the clock inverter, the flip-flop according to the example embodiment of the inventive concept may generate the second internal signal CKb by inverting the clock signal CK when the clock signal CK has a certain level.

Slave latch 300a may include OAI21 logic 320. OAI21 logic 320 may include an or gate 321 and a nand gate 322. Or gate 321 may receive as inputs clock signal CK and an inverted signal Qi obtained by inverting the output signal QN of OAI21 logic circuit 320. The nand gate 322 may receive the output signal of the or gate 321 and the second internal signal CKb as inputs, and output an output signal QN.

The slave latch 300a may include two inverters, for example, a second inverter 330 and a third inverter 340. Second inverter 330 may receive output signal QN and provide an inverted signal Qi, obtained by inverting output signal QN, to OAI21 logic circuit 320. The third inverter 340 may receive the output signal QN and output a final signal Q obtained by inverting the output signal QN.

Fig. 9A is a circuit diagram of the flip-flop 10a-2 according to an exemplary embodiment of the inventive concept. Referring to fig. 9A, the flip-flop 10a-2 may further include a clock buffer 500. The clock buffer 500 may include two inverters. Clock buffer 500 may receive clock signal CK and output buffered clock signal bCK. Unlike the flip-flop 10a shown in fig. 3, the flip-flop 10a-2 according to an exemplary embodiment of the inventive concept may receive the buffered clock signal bCK instead of the clock signal CK.

The buffered clock signal bCK may have a certain buffering delay time tb compared to the clock signal CK. As shown in fig. 2, a flip-flop that receives a relatively delayed data signal among the scan flip-flops 10-1, 10-2, and 10-3 included in the integrated circuit 100 may adjust data latch timing with other flip-flops by receiving a buffered clock signal bCK.

The slew rate (slew rate) of buffered clock signal bCK may be greater than the slew rate of clock signal CK. The greater the slew rate, the more the reliability of the flip-flop can be improved because the data signal is latched according to the active edge. According to example embodiments of the inventive concepts, a buffered clock signal bCK having a relatively high slew rate may be applied to the flip-flop instead of the clock signal CK, thereby increasing reliability of data latching.

Fig. 9B is a circuit diagram of the flip-flop 10a-3 according to an exemplary embodiment of the inventive concept. Referring to FIG. 9B, flip-flop 10a-3 may include slave latch 300 a-2. Unlike slave latch 300a of fig. 3, slave latch 300a-2 may include an and gate 350 and a nor gate 360. The and gate 350 may receive the internal output signal Qm and the clock signal CK, like the nand gate 310a of fig. 3. Nor gate 360 may receive the output signal of and gate 350 and reset signal RST.

When the reset signal RST has a logic high level, the output signal of the nor gate 360 may have a logic low level, and finally the signal Q may be reset to a logic low level.

When the reset signal RST has a logic low level, the nor gate 360 may operate as an inverter. Accordingly, the and gate 350 and the nor gate 360 may be connected in series to operate as the nand gate 310a of fig. 3.

Fig. 9C is a circuit diagram of the flip-flops 10a-4 according to an exemplary embodiment of the inventive concept. Referring to fig. 9C, the flip-flop 10a-4 may include a twelfth P-type transistor P12. Slave latch 300a-3 may include a glitch (glitch) protection circuit 370 and an inverter 380.

The internal output signal Qm may be input to a gate terminal of the twelfth P-type transistor P12, a source terminal of the twelfth P-type transistor P12 may be connected to the power supply node VDD, and a drain terminal of the twelfth P12 may be connected to the sixth node M6.

Referring to fig. 13B and 14B, when the clock signal CK has a logic high level, the internal output signal Qm may have a logic level inverted from the data signal D, and the second internal signal CKb may have the same logic level as the data signal D.

Referring to fig. 9C, when the clock signal CK has a logic high level, the eighth N-type transistor N8 may be turned on, and the second internal signal CKb of the fifth node M5 may be input to a source terminal of the second N-type transistor N2 through the sixth node M6. Since the second N-type transistor N2 may be turned on by the clock signal CK, the second internal signal CKb transmitted from the source terminal of the second N-type transistor N2 may be applied to the first node M1. When the clock signal CK has a logic high level, the second internal signal CKb may have the same logic level as the data signal D, and thus, the first internal signal DCK indicating the signal of the first node M1 may have the same logic level as the data signal D.

However, when the data signal D has a logic high level, the logic level of the sixth node M6 may be lower than the logic level of the data signal D by the threshold voltage of the eighth N-type transistor N8. When the logic level of the sixth node M6 is low, the logic level of the first internal signal DCK may also be low, and thus, an error may occur in the general operation of the flip-flops 10 a-4. That is, a low voltage may be applied to the AOI31 logic circuit 220a through the threshold voltage of the eighth N-type transistor N8, and thus, the flip-flops 10a-4 may perform a low voltage operation.

When the data signal D has a logic high level, the twelfth P-type transistor P12 may be turned on, thereby increasing the logic level of the sixth node M6. Accordingly, the logic level of the first internal signal DCK may also be maintained at a logic high level, and thus, the low voltage operation of the flip-flops 10a-4 may be standardized.

The glitch protection circuit 370 may include a fourteenth P-type transistor P14, a twelfth N-type transistor N12, and a thirteenth N-type transistor N13.

As described below with reference to fig. 13B and 14B, when the clock signal CK has a logic high level, the second internal signal CKb may have the same logic level as the data signal D. For example, when the clock signal CK has a logic high level, the data signal D may be input to the gate terminal of the fourteenth P-type transistor P14. In addition, when the clock signal CK has a logic high level, the eighth N-type transistor N8 is turned on, and thus, the data signal D may be input to the gate terminal of the twelfth N-type transistor N12. When the clock signal CK has a logic high level, the thirteenth N-type transistor N13 is turned on, and thus, the glitch protection circuit 370 may operate as an inverter in which the data signal D is input to the twelfth N-type transistor N12 and the fourteenth P-type transistor P14.

However, when the data signal D has a logic high level, the logic level of the sixth node M6 may be lower than the logic level of the data signal D by the threshold voltage of the eighth N-type transistor N8. When the logic level of the sixth node M6 is low, the twelfth N-type transistor N12 may not be turned on, and the glitch protection circuit 370 may not operate as an inverter. When the glitch protection circuit 370 does not operate as an inverter, the output signal QN may be different from the inverted value of the data signal D, and thus, a glitch may occur in the final signal Q.

As described above, since the twelfth P-type transistor P12 is turned on when the data signal D has a logic high level, the logic level of the sixth node M6 may increase. Accordingly, the twelfth N-type transistor N12 may be normally turned on, and the glitch protection circuit 370 may operate as an inverter. That is, the twelfth P-type transistor P12 may provide a stable logic high signal to the glitch protection circuit 370, thereby preventing the occurrence of a glitch in the final signal Q.

For example, when the clock signal CK has a logic low level, the second internal signal CKb has a logic high level, and thus, the thirteenth N-type transistor N13 and the fourteenth P-type transistor P14 may be turned off. Further, since the inverter 380 is enabled when the clock signal CK has a logic low level, the final signal Q may be maintained at a constant value when the clock signal CK has a logic low level.

Fig. 10A is a circuit diagram of a flip-flop 10b according to an exemplary embodiment of the inventive concept. Referring to fig. 10A, the flip-flop 10b may include a master latch 200b and a slave latch 300 b.

The slave latch 300b may include a nand gate 310 b. The nand gate 310b may include ninth and tenth P-type transistors P9 and P10 and eighth and ninth N-type transistors N8 and N9.

The internal output signal Qm may be input to a gate terminal of the ninth P-type transistor P9, a source terminal of the ninth P-type transistor P9 may be connected to the power supply node VDD, and a drain terminal of the ninth P-type transistor P9 may be connected to the fifth node M5. The clock signal CK may be input to a gate terminal of the tenth P-type transistor P10, a source terminal of the tenth P-type transistor P10 may be connected to the power supply node VDD, and a drain terminal of the tenth P-type transistor P10 may be connected to the fifth node M5.

The clock signal CK may be input to a gate terminal of the eighth N-type transistor N8, a source terminal of the eighth N-type transistor N8 may be connected to the sixth node M6, and a drain terminal of the eighth N-type transistor N8 may be connected to the fifth node M5. The internal output signal Qm may be input to a gate terminal of the ninth N-type transistor N9, a source terminal of the ninth N-type transistor N9 may be connected to the ground node, and a drain terminal of the ninth N-type transistor N9 may be connected to the sixth node M6.

Unlike the nand gate 310a of fig. 3, the logic level of the sixth node M6, which is an internal node of the nand gate 310b, may be fed back to the master latch 200 b.

Master latch 200b may include delay circuit 100 b. Unlike the delay circuit 100a of fig. 3, the delay circuit 100b may include a nand gate 130, a circuit part 140, and an inverter 150. The nand gate 130 may receive the scan enable signal SE and the scan input signal SI, and may be enabled in response to the clock signal CK. The output signal of the nand gate 130 may be output to the seventh node M7. The circuit part 140 may include a plurality of transistors, for example, an eleventh P-type transistor P11 and tenth and eleventh N-type transistors N10 and N11. The second internal signal CKb may be input to a gate terminal of the eleventh P-type transistor P11, a source terminal of the eleventh P-type transistor P11 may be connected to the power supply node VDD, and a drain terminal of the eleventh P-type transistor P11 may be connected to the seventh node M7. The clock signal CK may be input to a gate terminal of the tenth N-type transistor N10. A gate terminal of the eleventh N-type transistor N11 may be connected to the sixth node M6 that is an internal node of the slave latch 300 b. Referring to fig. 13B and 14B, when the clock signal CK has a logic high level, the sixth node M6 may have the same logic level as the data signal D. In addition, when the clock signal CK has a logic high level, the second internal signal CKb may also have the same logic level as the data signal D, and thus, the circuit portion 140 may operate as an inverter. Accordingly, the circuit part 140 may output an inverted value of the data signal D. As a result, the first internal signal DCK may have the same logic level as the data signal D passing through the inverter 150.

Fig. 10B is a circuit diagram of the flip-flop 10B-2 according to an exemplary embodiment of the inventive concept. Referring to fig. 10b, unlike the flip-flop 10b of fig. 10A, the flip-flop 10b-2 may further include a twelfth P-type transistor P12. The internal output signal Qm may be input to a gate terminal of the twelfth P-type transistor P12, a source terminal of the twelfth P-type transistor P12 may be connected to the power supply node VDD, and a drain terminal of the twelfth P12 may be connected to the sixth node M6.

Referring to fig. 13B and 14B, when the clock signal CK has a logic high level, the internal output signal Qm may have a logic level inverted from the data signal D, and the second internal signal CKb may have the same logic level as the data signal D.

Referring to fig. 10B, when the clock signal CK has a logic high level, the eighth N-type transistor N8 may be turned on, and the second internal signal CKb of the fifth node M5 may be input to the gate terminal of the eleventh N-type transistor N11 through the sixth node M6. However, when the data signal D has a logic high level, the logic level of the sixth node M6 may be lower than the logic level of the data signal D by the threshold voltage of the eighth N-type transistor N8. When the logic level of the sixth node M6 is low, the eleventh N-type transistor N11 may not be turned on, and the circuit part 140 may not operate as an inverter.

When the data signal D has a logic high level, the twelfth P-type transistor P12 may be turned on, thereby increasing the logic level of the sixth node M6. Accordingly, the eleventh N-type transistor N11 may be normally turned on, and the circuit part 140 may operate as an inverter. That is, the twelfth P-type transistor P12 may provide a stable logic high signal to the circuit portion 140, so that the circuit portion 140 operates as a normal inverter.

Fig. 10C is a circuit diagram of the flip-flop 10b-3 according to an exemplary embodiment of the inventive concept. Referring to fig. 10C, the flip-flop 10b-3 may include a slave latch 300b-2, and the slave latch 300b-2 may include a nand gate 310b-2 reset by a reset signal RST. The nand gate 310b-2 may further include reset transistors, for example, a thirteenth P-type transistor P13 and a twelfth N-type transistor N12.

The reset signal RST may be input to a gate terminal of the thirteenth P-type transistor P13, a source terminal of the thirteenth P-type transistor P13 may be connected to the power supply node VDD, and a drain terminal of the thirteenth P-type transistor P13 may be connected to the eighth node M8. A source terminal of the ninth P-type transistor P9 may be connected to the eighth node M8, and a drain terminal of the ninth P-type transistor P9 may be connected to the fifth node M5. A source terminal of the tenth P-type transistor P10 may be connected to the eighth node M8, and a drain terminal of the tenth P-type transistor P10 may be connected to the fifth node M5. When the reset signal RST has a logic high level, the thirteenth P-type transistor P13 is turned off, and thus, the fifth node M5 is not pulled up regardless of signals respectively applied to the gate terminals of the ninth P-type transistor P9 and the tenth P-type transistor P10. When the reset signal RST has a logic low level, the pull-up circuit of the nand gate 310B-2 may operate substantially the same as the pull-up circuit of the nand gate 310B of fig. 10A and 10B.

The reset signal RST may be input to the gate terminal of the twelfth N-type transistor N12. When the reset signal RST has a logic high level, the fifth node M5 is discharged by the turned-on twelfth N-type transistor N12, and thus, the second internal signal CKb may have a logic low level. When the second internal signal CKb has a logic low level, the final signal Q has a logic low level through the OAI21 logic circuit 320, and thus, the flip-flop 10b-3 can be reset. When the reset signal RST has a logic low level, the pull-down circuit of the nand gate 310B-2 may operate the same as the pull-down circuit of the nand gate 310B of fig. 10A and 10B.

Fig. 10D is a circuit diagram of the flip-flop 10b-4 according to an exemplary embodiment of the inventive concept. Referring to fig. 10D, the flip-flop 10b-4 may include a slave latch 300b-3, and the slave latch 300b-3 may include a glitch protection circuit 370 and an inverter 380.

The glitch protection circuit 370 may include a fourteenth P-type transistor P14, a twelfth N-type transistor N12, and a thirteenth N-type transistor N13.

As described below with reference to fig. 13B and 14B, when the clock signal CK has a logic high level, the second internal signal CKb may have the same logic level as the data signal D. For example, when the clock signal CK has a logic high level, the data signal D may be input to the gate terminal of the fourteenth P-type transistor P14. In addition, when the clock signal CK has a logic high level, the eighth N-type transistor N8 is turned on, and thus, the data signal D may be input to the gate terminal of the twelfth N-type transistor N12. When the clock signal CK has a logic high level, the thirteenth N-type transistor N13 is turned on, and thus, the glitch protection circuit 370 may operate as an inverter in which the data signal D is input to the twelfth N-type transistor N12 and the fourteenth P-type transistor P14.

However, when the data signal D has a logic high level, the logic level of the sixth node M6 may be lower than the logic level of the data signal D by the threshold voltage of the eighth N-type transistor N8. When the logic level of the sixth node M6 is low, the twelfth N-type transistor N12 may not be turned on, and the glitch protection circuit 370 may not operate as an inverter. When the glitch protection circuit 370 does not operate as an inverter, the output signal QN may be different from the inverted value of the data signal D, and thus, a glitch may occur in the final signal Q.

As described above with reference to fig. 10B, when the data signal D has a logic high level, the twelfth P-type transistor P12 may be turned on, thereby increasing the logic level of the sixth node M6. Accordingly, the twelfth N-type transistor N12 may be normally turned on, and the glitch protection circuit 370 may operate as an inverter. That is, the twelfth P-type transistor P12 may provide a stable logic high signal to the glitch protection circuit 370, thereby preventing the occurrence of a glitch in the final signal Q.

For example, when the clock signal CK has a logic low level, the second internal signal CKb has a logic high level, and thus, the thirteenth N-type transistor N13 and the fourteenth P-type transistor P14 may be turned off. Further, since the inverter 380 is enabled when the clock signal CK has a logic low level, the final signal Q may be maintained at a constant value when the clock signal CK has a logic low level.

Fig. 10E is a circuit diagram of the flip-flop 10b-5 according to an exemplary embodiment of the inventive concept. Referring to FIG. 10E, the flip-flop 10b-5 may include a slave latch 300b-4, and the slave latch 300b-4 may include a NAND gate 310b-2 that is reset by a reset signal RST, the NAND gate 310b-2 being described above with reference to FIG. 10C. The nand gate 310b-2 may further include reset transistors, for example, a thirteenth P-type transistor P13 and a fourteenth N-type transistor N14.

Fig. 10E includes the glitch protection circuit 370 and the twelfth P-type transistor P12 described above with reference to fig. 10D, and thus, a glitch in the final signal Q can be prevented. In addition, fig. 10E includes the nand gate 310b-2 described above with reference to fig. 10C, and thus, the final signal Q may be reset in response to the reset signal RST.

Fig. 11 is a circuit diagram of a flip-flop 10d according to an exemplary embodiment of the inventive concept. Referring to fig. 11, the flip-flop 10d may include a clocked inverter 600. The clock inverter 600 may receive the clock signal CK and output an inverted clock signal nCK. The flip-flop 10d may include a master latch 200d and a slave latch 300d, and the master latch 200d may include a delay circuit 100 d.

Unlike the delay circuit 100a of fig. 3, the delay circuit 100d may include a first OAI21 logic circuit 110d and a second OAI21 logic circuit 120 d. First OAI21 logic circuit 110d may include an OR gate 111d and a NAND gate 112 d. The or gate 111d may receive the scan input signal SI and the inverted scan enable signal nSE. The nand gate 112d may receive the output signal of the or gate 111d and the inverted clock signal nCK and output an intermediate signal F. The second OAI21 logic circuit 120d may include an or gate 121d and a nand gate 122 d. Or gate 121d may receive internal output signal Qm and inverted clock signal nCK. The nand gate 122 may receive the output signal of the or gate 121 and the intermediate signal and output a first internal signal DCK.

Unlike master latch 200a of FIG. 3, master latch 200d may include OAI31 logic 220 d. OAI31 logic circuit 220d may include an or gate 221d and a nand gate 222 d. The or gate 221D may receive the second internal signal CKb, the scan enable signal SE, and the data signal D. The nand gate 222 may receive the output signal of the or gate 221 and the first internal signal DCK and output an internal output signal Qm.

Unlike the slave latch 300a of fig. 3, the slave latch 300d may include a nor gate 310d, and the nor gate 310d outputs the second internal signal CKb. The nor gate 310d may receive the inverted clock signal nCK and the internal output signal Qm and output a second internal signal CKb. Unlike slave latch 300a of FIG. 3, slave latch 300d may include AOI21 logic 320 d. AOI21 logic 320d may include an AND gate 321d and an OR gate 322 d. And gate 321d may receive inverted clock signal nCK and inverted signal Qi. The nor gate 322d may receive the output signal of the and gate 321d and the second internal signal CKb and output an output signal QN. The third inverter 340 may receive the output signal QN and output the final signal Q by inverting the output signal QN.

Fig. 12A is a circuit diagram of the flip-flop 10d-2 according to an exemplary embodiment of the inventive concept. For example, FIG. 12A shows flip-flop 10d-2 using an inverted clock signal nCK. The description made above with reference to fig. 1 to 6, 7A, 7B, 8, 9A to 9C, 10A to 10E, and 11 may be omitted in the description to be made with reference to fig. 12A. Referring to FIG. 12A, flip-flop 10d-2 may include master latch 200d-2 and slave latch 300 d-2.

Master latch 200d-2 may include delay circuit 100 d-2. Unlike the delay circuit 100d of fig. 11, the delay circuit 100d-2 may include a nor gate 130d, a circuit portion 140d, and an inverter 150 d. The nor gate 130d may receive the inverted scan enable signal nSE and the scan input signal SI, and may be enabled in response to the inverted clock signal nCK and the second internal signal CKb. The output signal of the nor gate 130d may be output to the first node M1 d. The circuit portion 140d may include a plurality of transistors, for example, first and second P-type transistors P1d and P2d and a first N-type transistor N1 d. The second internal signal CKb may be input to the gate terminal of the first N-type transistor N1d, the source terminal of the first N-type transistor N1d may be connected to a ground node, and the drain terminal of the first N-type transistor N1d may be connected to the first node M1 d. The inverted clock signal nCK may be input to the gate terminal of the first P-type transistor P1 d. A gate terminal of the second P-type transistor P2d may be connected to the second node M2d, which is an internal node of the slave latch 300d-2, such that the glitch protection signal GP of the second node M2d is applied to the gate terminal of the second P-type transistor P2 d. When the inverted clock signal nCK has a logic high level, the third N-type transistor N3d may cause the second internal signal CKb to have a logic low level. In the normal operating mode, the inverted scan enable signal nSE has a logic high level and the scan input signal has a logic low level. Accordingly, the first node M1d has a logic low level, and the first internal signal DCK has a logic high level. The internal output signal Qm has the same logic level as the inverted data signal/D through the OAI31 logic circuit 220D. The glitch protection signal GP of the second node M2d has the same logic level as the inverted logic level of the internal output signal Qm. For example, the logic level of the glitch protection signal GP may be the same as that of the data signal D. In addition, when the inverted clock signal nCK has a logic low level, the second internal signal CKb may have the same logic level as the data signal D as the third P-type transistor P3D is turned on. Therefore, the circuit portion 140d can operate as an inverter. For example, the circuit part 140D may output an inverted value of the data signal D. As a result, the first internal signal DCK may have the same logic level as the data signal D through the delay circuit 100D-2.

Slave latch 300d-2 may include nor gate 310d, glitch protection circuit 350d, and fifth N-type transistor N5 d. The internal output signal Qm may be input to a gate terminal of the fifth N-type transistor N5d, a source terminal of the fifth N-type transistor N5d may be connected to the ground node, and a drain terminal of the fifth N-type transistor N5d may be connected to the second node M2 d.

When the inverted clock signal nCK has a logic high level, the second internal signal CKb may have a logic low level through the third N-type transistor N3 d. When the second internal signal CKb has a logic low level, the internal output signal Qm may have an inverted logic level of the data signal D through the OAI31 logic circuit 220D in a normal operation mode (e.g., SE ═ 0). For example, when the inverted clock signal nCK has a logic high level, the inverted logic level of the data signal D may be latched to the internal output signal Qm.

When inverted clock signal nCK transitions to a logic low level, NOR gate 310d may operate as an inverter receiving internal output signal Qm as an input. Accordingly, the second internal signal CKb may have the same logic level as the data signal D. For example, when the inverted clock signal nCK has a logic low level, the second node M2d may have the same logic level as the third node M3d through the third P-type transistor P3d being turned on. For example, when the inverted clock signal nCK has a logic low level, the second node M2D may have the same logic level as the data signal D.

When the data signal D has a logic low level, the logic level of the second node M2D may be greater than the logic level of the data signal D by the threshold voltage of the third P-type transistor P3D. When the logic level of the second node M2d is high, the second P-type transistor P2d may not be turned on, and the circuit part 140d may not operate as an inverter.

When the inverted clock signal nCK has a logic low level and the data signal D has a logic low level (e.g., the internal output signal Qm has a logic high level), the fifth N-type transistor N5D according to an exemplary embodiment of the inventive concept is turned on, and thus, the logic level of the second node M2D may be lowered. Accordingly, the second P-type transistor P2d may be normally turned on, and the circuit part 140d may operate as an inverter. For example, fifth N-type transistor N5d may provide a stable logic low signal to circuit portion 140d such that circuit portion 140d operates as a normal inverter.

The glitch protection circuit 350d may include a fourth N-type transistor N4d, a fifth P-type transistor P5d, and a sixth P-type transistor P6 d.

When the clock signal CK has a logic high level, the second internal signal CKb may have the same logic level as the data signal D, and thus, the glitch protection circuit 350D may operate as an inverter receiving the data signal D.

However, when the data signal D has a logic low level, the logic level of the second node M2D may be greater than the logic level of the data signal D by the threshold voltage of the third P-type transistor P3D. When the logic level of the second node M2d is high, the sixth P-type transistor P6d may not be turned on, and the glitch protection circuit 350d may not operate as an inverter. When the glitch protection circuit 350D does not operate as an inverter, the output signal QN may be different from the inverted value of the data signal D, and thus a glitch may occur in the final signal Q.

As described above, when the data signal D has a logic low level, the fifth N-type transistor N5D is turned on, and thus, the logic level of the second node M2D may be lowered. Accordingly, the sixth P-type transistor P6d may be normally turned on, and the glitch protection circuit 350d may operate as an inverter. For example, the fifth N-type transistor N5d may provide a stable logic low signal to the glitch protection circuit 350d so that the occurrence of glitches in the final signal Q is prevented.

Fig. 12B is a circuit diagram of the flip-flop 10d-3 according to an exemplary embodiment of the inventive concept. Referring to fig. 12B, the flip-flop 10d-3 may include a first nor gate 150d-2 and a second nor gate 330 d-2.

The first nor gate 150d-2 may receive the output signal of the circuit part 140d and the reset signal RST and output the first internal signal DCK. When the reset signal RST has a logic high level, the internal output signal Qm may be reset to a logic high level.

The second nor gate 330d-2 may receive the output signal QN and the reset signal RST and output an inverted output signal Qi. When the reset signal RST has a logic high level, the final signal Q may be reset to a logic low level.

Fig. 13A and 13B are circuit diagrams for describing a normal operation mode of the flip-flop 10a according to an exemplary embodiment of the inventive concept. For example, fig. 13A shows a normal operation mode of the flip-flop 10a when the clock signal CK has a logic low level. More specifically, fig. 13A shows a case where the first data signal D1 is applied to the and gate 221 within a predetermined setup time after the clock signal CK transitions to the logic high level. Fig. 13B shows a normal operation mode of the flip-flop 10a when the clock signal CK has a logic high level. More specifically, fig. 13B shows a case where the second data signal D2 is applied to the and gate 221 after the predetermined setup time. Therefore, the second data signal D2 may not be transmitted to the final signal.

Referring to fig. 13A and 13B, when the scan enable signal SE has a logic low level, the flip-flop 10a may operate in a normal operation mode. Assume that the clock signal CK transitions from a logic low level to a logic high level. For example, assume that in fig. 13A, the first data signal D1 is applied to the master latch 200a when the clock signal CK has a logic low level, and assume that in fig. 13B, the second data signal D2 is applied to the master latch 200a when the clock signal CK has a logic high level. For example, it is assumed that the second data signal D2 is applied to the master latch 200a after a setup time elapses from a point in time when the clock signal CK transitions to a logic high level. Here, the logic low level of the clock signal CK may be represented as 0, and the logic high level of the clock signal CK may be represented as 1.

Referring to fig. 13A, when the clock signal CK has a logic low level, the first internal signal DCK may have a logic low level through the delay circuit 100 a. The first internal signal DCK may be delayed by a delay time td from a time point when the clock signal CK transitions (e.g., from the first logic level to the second logic level).

Referring to fig. 13A, when the clock signal CK has a logic low level, the second internal signal CKb may have a logic high level through the nand gate 310 a.

Since the first internal signal DCK has a logic low level and the second internal signal CKb has a logic high level, the AOI31 logic circuit 220a may operate as an inverter (which receives the first data signal D1) and output the internal output signal Qm by inverting the first data signal D1. For example, when the first internal signal DCK maintains a logic low level, the master latch 200a may receive the first data signal D1 and output the inverted first data signal D1N as the internal output signal Qm.

Referring to fig. 13A, when the clock signal CK has a logic low level, the second internal signal CKb has a logic high level, and thus, the OAI21 logic circuit 320 may operate as an inverter receiving the inverted signal Qi. For example, when the clock signal CK has a logic low level, the slave latch 300a may hold the existing (or previous) final signal Q-.

In summary, when the clock signal CK has a logic low level, the master latch 200a may output the inverted first data signal D1N as the internal output signal Qm, and the slave latch 300a may hold the existing final signal Q-.

Referring to fig. 13B, when the clock signal CK has a logic high level, the second AOI21 logic circuit 120 may operate as an inverter (which receives the internal output signal Qm).

When the clock signal CK transitions to a logic high level, the internal output signal Qm is identical to the inverted first data signal D1N, and thus, the first internal signal DCK may be identical to the first data signal D1. According to example embodiments of the inventive concepts, a period in which the first internal signal DCK maintains a logic low level may be longer than a period in which the clock signal CK maintains a logic low level by a delay time. Accordingly, although the clock signal CK transitions to a logic high level, the first internal signal DCK may have a logic low level for a delay time.

Referring to fig. 13B, when the clock signal CK has a logic high level, the nand gate 310a may operate as an inverter. When the clock signal CK transitions to a logic high level, the internal output signal Qm is identical to the inverted first data signal D1N, and thus, the second internal signal CKb may be identical to the first data signal D1 through the nand gate 310 a. Although the clock signal CK transitions to a logic high level, the first internal signal DCK maintains a logic low level for a delay time, and thus, when the data signal applied to the and gate 221 is changed within a predetermined setup time, the internal output signal Qm may have the same value as the inverse value of the changed data signal.

The AOI31 logic circuit 220a may operate as a logic circuit including an and gate 221 and a nor gate 222, the and gate 221 receiving the first data signal D1 and the second data signal D2, the nor gate 222 receiving an output value of the and gate 221 and the first internal signal DCK. For example, the internal output signal Qm, which is an output value of the AOI31 logic circuit 220a, may be the inverted first data signal D1N represented by equation 1.

[ equation 1]

Qm＝/(D1D2+D1)＝D1N

For example, when the clock signal CK has a logic high level, the master latch 200a may hold the first data signal D1 as the internal output signal Qm.

Referring to fig. 13B, when the clock signal CK has a logic high level, the OAI21 logic circuit 320 may operate as an inverter (which receives the second internal signal CKb). Thus, the output signal QN may be the inverted first data signal D1N. The third inverter 340 receives the output signal QN and outputs an inverted value of the output signal QN as the final signal Q, and thus, the final signal Q may be the first data signal D1.

For example, when the clock signal CK has a logic high level, the slave latch 300a may output the first data signal D1 input to the master latch 200a when the clock signal CK has a logic low level as the final signal Q.

Fig. 14A and 14B are circuit diagrams for describing a normal operation mode of the flip-flop 10B according to an exemplary embodiment of the inventive concept. For example, fig. 14A shows a normal operation mode of the flip-flop 10b when the clock signal CK has a logic low level. Fig. 14B shows a normal operation mode of the flip-flop 10B when the clock signal CK has a logic high level. Although fig. 14A and 14B show the flip-flop 10B of fig. 10A, the description made with reference to fig. 14A and 14B can also be applied to the flip-flops 10B-2 to 10B-5 of fig. 10B to 10E.

Referring to fig. 14A and 14B, when the scan enable signal SE has a logic low level, the flip-flop 10B may operate in a normal operation mode. Assume that the clock signal CK transitions from a logic low level to a logic high level. It is assumed that the first data signal D1 is applied to the main latch 200B when the clock signal CK has a logic low level in fig. 14A, and that the second data signal D2 is applied to the main latch 200B when the clock signal CK has a logic high level in fig. 14B.

As with the flip-flop 10a of fig. 13A, when the clock signal CK has a logic low level, the first internal signal DCK may have a logic low level, the internal output signal Qm may have the same logic level as the inverted first data signal D1N, the second internal signal CKb may have a logic high level, and the final signal Q may maintain the previous final signal Q-.

As in the flip-flop 10a of fig. 13B, when the clock signal CK has a logic high level, the first internal signal DCK may have the same logic level as the first data signal D1, the internal output signal Qm may have the same logic level as the inverted first data signal D1N, the second internal signal CKb may have the same logic level as the first data signal D1, and the final signal Q may have the same logic level as the first data signal D1.

Fig. 15 is a timing diagram of a flip-flop according to an example embodiment of the inventive concept. The timing diagram of fig. 15 may be used to describe the operation of at least one of the flip-flops 10, 10-1, 10-2, 10-3, 10A-2, 10A-3, 10A-4, 10b-2, 10b-3, 10b-4, and 10b-5 described above with reference to fig. 1-3, 9A-9C, and 10A-10E, respectively. The clock signal CK may transition from a logic low level to a logic high level at a first time point t 1. The first internal signal DCK may maintain a logic low level until a third time point t3 delayed by a delay time td from the first time point t 1. For example, when the data signal D transitions from a logic low level to a logic high level at the second time point t2, the internal output signal Qm may change to a logic low level at the second time point t2, and finally the signal Q may change to a logic high level at the second time point t 2. For example, when the data signal D transitions from a logic high level to a logic low level at the fourth time point t4, the logic levels of the internal output signal Qm and the final signal Q may not change. The data signal D before the third time point t3 may be referred to as the first data signal D1 of fig. 13A and 13B, and the data signal D after the third time point t3 may be referred to as the second data signal D2 of fig. 13A and 13B. The delay time td may be, for example, a delay occurring when the internal output signal Qm passes through the delay circuit 100 of fig. 1 when the clock signal CK transitions to a logic high level. Although clock signal CK is described as an example, the timing diagram of fig. 15 may also be applied to buffered clock signal bCK of fig. 9A by modifying a portion of the timing diagram of fig. 15. Accordingly, the operation of at least one of the flip-flops 10a-2 shown in FIG. 9A may be described with reference to FIG. 15.

After the setup time ts has elapsed since the first time point t1, the data signal D may transition to a logic high level. According to example embodiments of the inventive concepts, the setup time ts may be less than the delay time td. When the first internal signal DCK maintains a logic low level, the data signal D may be reflected on the internal output signal Qm. Therefore, even after the clock signal CK transitions to a logic high level, when the data signal D changes within the setup time ts, the changed data signal D may be reflected on the final signal Q.

For example, referring to fig. 15, when the data signal D changes from a logic low level to a logic high level within a setup time ts from a first time point t1 at which the clock signal CK transitions to a logic high level, the changed data signal D (i.e., "1") may be reflected on the internal output signal Qm and the final signal Q.

Fig. 16 is a timing diagram of a flip-flop according to an example embodiment. The timing diagram of fig. 16 may be used to describe the operation of at least one of the flip-flops 10, 10-1, 10-2, 10-3, 10d-2, and 10d-3 described above with reference to fig. 1, 2, 11, 12A, and 12B, respectively. The clock signal CK may transition from a logic low level to a logic high level at a first time point t 1. The first internal signal DCK may maintain a logic high level until a third time point t3 delayed by a delay time td from the first time point t 1. For example, when the data signal D transitions from a logic high level to a logic low level at the second time point t2, the internal output signal Qm may change to a logic high level at the second time point t2, and finally the signal Q may change to a logic low level at the second time point t 2. For example, when the data signal D transitions from a logic low level to a logic high level at the fourth time point t4, the logic levels of the internal output signal Qm and the final signal Q may not change. The setup time ts may be less than the delay time td. When the first internal signal DCK maintains a logic high level, the data signal D may be reflected on the internal output signal Qm. Therefore, even after the clock signal CK transitions to a logic high level, when the data signal D changes within the setup time ts, the changed data signal D (i.e., "0") may be reflected on the final signal Q.

Although the clock signal CK is described as an example, the timing diagram of fig. 16 can also be applied to the inverted clock signal nCK of fig. 12A and 12B by modifying a portion of the timing diagram of fig. 16. Accordingly, the operation of at least one of the flip-flops 10d, 10d-2 and 10d-3 shown in fig. 12A and 12B may be described with reference to fig. 16.

In example embodiments, the flip-flop according to example embodiments of the inventive concept may include a delay circuit to perform a latch operation of the data signal D having a negative setup time. The shorter the setup time ts, the greater the maximum frequency of the clock signal CK, and thus, the flip-flop according to an exemplary embodiment of the inventive concept may provide an improved clock frequency.

While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.