Clock transmitting device and method, clock receiving device and method

文档序号：439450 发布日期：2021-12-24 浏览：37次中文

阅读说明：本技术 时钟发送装置及方法、时钟接收装置及方法 (Clock transmitting device and method, clock receiving device and method ) 是由续博雄关童童曾富前于 2020-06-24 设计创作，主要内容包括：本发明实施例提供了一种时钟发送装置及方法、时钟接收装置及方法,其中,时钟发送装置包括：输入单元,配置为输入第一输入时钟与第二输入时钟；采样单元,配置为获取第一采样时钟与第二采样时钟,并根据第一采样时钟与第二采样时钟确定第一频率控制字；其中,第一频率控制字用于指示第一采样时钟与第二采样时钟之间的关系,第一采样时钟由第一输入时钟按照预设规则确定,第二采样时钟由第二输入时钟按照预设规则确定；发送单元,配置为根据第一输入时钟生成时钟信号,并发送时钟信号至接收侧；其中,时钟信号中至少携带有第一频率控制字。通过本发明,可以解决相关技术中通信设备在时钟分发过程中时钟线路布设过于复杂且难以实现的问题。(The embodiment of the invention provides a clock sending device and a clock sending method, and a clock receiving device and a clock receiving method, wherein the clock sending device comprises: an input unit configured to input a first input clock and a second input clock; the sampling unit is configured to acquire a first sampling clock and a second sampling clock and determine a first frequency control word according to the first sampling clock and the second sampling clock; the first frequency control word is used for indicating the relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by a first input clock according to a preset rule, and the second sampling clock is determined by a second input clock according to the preset rule; a transmitting unit configured to generate a clock signal according to a first input clock and transmit the clock signal to a receiving side; the clock signal carries at least a first frequency control word. The invention can solve the problems that the clock circuit layout is too complicated and is difficult to realize in the clock distribution process of the communication equipment in the related technology.)

1. A clock transmission apparatus, characterized in that the apparatus comprises:

an input unit configured to input a first input clock and a second input clock;

the sampling unit is configured to acquire a first sampling clock and a second sampling clock and determine a first frequency control word according to the first sampling clock and the second sampling clock; the first frequency control word is used for indicating the relation between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule;

a transmitting unit configured to generate a clock signal according to the first input clock and transmit the clock signal to a receiving side; wherein the clock signal carries at least the first frequency control word.

2. The apparatus of claim 1, wherein the first frequency control word is used to indicate at least one of: a ratio of the clock frequencies of the first and second sampling clocks, a difference in the clock frequencies of the first and second sampling clocks.

3. The apparatus of claim 2, wherein the sampling unit is further configured to,

sampling a clock frequency of the first sampling clock and a clock frequency of the second sampling clock, respectively, to determine the first frequency control word.

4. The apparatus of claim 3, wherein the sampling unit comprises:

a transmit accumulation subunit configured to accumulate clock edges of the first sampling clock;

a transmission decision subunit configured to decide a clock edge of the second sampling clock;

and the counting subunit is configured to count the clock edge of the second sampling clock according to the decision result of the sending decision subunit, and determine the count value of the clock edge of the second sampling clock when the clock edge of the first sampling clock is accumulated to a preset value, so as to obtain the first frequency control word.

5. The apparatus of any one of claims 1 to 4, further comprising:

the frequency multiplication unit is configured to multiply the frequency of the first input clock according to a preset first multiple to obtain the first sampling clock; wherein a ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

6. The apparatus of claim 5, wherein the frequency doubling unit comprises:

the first frequency multiplication subunit is configured to multiply the frequency of the first input clock according to a preset second multiple to obtain a first sending clock; wherein the first transmit clock is used for the transmit unit to generate the clock signal according to the first transmit clock;

and the second frequency multiplication subunit is configured to multiply the frequency of the first sending clock according to a preset third multiple to obtain the first sampling clock.

7. The apparatus of claim 6, wherein the frequency doubling unit further comprises:

and the third frequency multiplication subunit is configured to multiply the frequency of the second input clock according to a preset fourth multiple to obtain the second sampling clock.

8. The apparatus of claim 7, wherein the first multiple, the second multiple, the third multiple, and the fourth multiple are further carried in the clock signal.

9. The apparatus of any one of claims 1 to 4, further comprising:

the filtering unit is configured to filter the first frequency control word according to a preset filtering manner, and send the filtered first frequency control word to the sending unit, so that the sending unit carries the filtered first frequency control word in the clock signal.

10. The apparatus of claim 9, wherein the sampling unit is further configured to,

repeatedly performing the following operations to obtain a plurality of the first frequency control words: determining the first frequency control word according to the first sampling clock and the second sampling clock;

the filtering unit is further configured to take an average of the plurality of first frequency control words as the filtered first frequency control word.

11. The apparatus of claim 1, wherein the sending unit further comprises:

a PWM coding subunit configured to code the first input clock to generate the clock signal and envelope the first frequency control word in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

12. The method of claim 1,

the input unit is further configured to input the first input clock, the second input clock, and a third input clock;

the sampling unit comprises a first sampling subunit and a second sampling subunit; wherein the content of the first and second substances,

the first sampling subunit is configured to determine the first frequency control word according to the first sampling clock and the second sampling clock;

the second sampling subunit is configured to determine a second frequency control word according to the first sampling clock and a third sampling clock; the second frequency control word is used for indicating the relation between the first sampling clock and the third sampling clock, and the third sampling clock is determined by the third input clock according to a preset rule;

the transmitting unit is further configured to generate the clock signal according to the first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least the first frequency control word and the second frequency control word.

13. The method of claim 1, wherein a frequency source of the first input clock is different from a frequency source of the second input clock.

14. A clock receiving apparatus, comprising:

a receiving unit configured to receive a clock signal transmitted by a transmitting side; the clock signal is generated according to a first input clock of the transmitting side, the clock signal at least carries a first frequency control word, the first frequency control word is used for indicating a relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock of the transmitting side according to the preset rule; the receiving unit is further configured to determine the first input clock and the first frequency control word according to the clock signal;

a recovery unit configured to determine the second input clock according to the first input clock and the first frequency control word.

15. The apparatus of claim 14, wherein the recovery unit is further configured to,

acquiring the first sampling clock according to the first input clock, and determining a plurality of first phase addresses according to the first sampling clock and the first frequency control word; wherein the first phase address is to indicate a phase of the second sampling clock;

determining the second sampling clock according to the plurality of first phase addresses, and determining the second input clock according to the second sampling clock.

16. The apparatus of claim 15, wherein the recovery unit comprises:

a receiving and accumulating subunit configured to accumulate the first frequency control word according to a clock edge of the first sampling clock, and obtain the plurality of first phase addresses according to each accumulation result of the first frequency control word;

the query subunit is configured to obtain a waveform of the second sampling clock according to the multiple first phase addresses and a preset mapping relation; the mapping relation is used for indicating the mapping relation between the first phase address and the waveform parameter preset by the second sampling clock; the query subunit is further configured to determine a clock frequency of the second sampling clock from a waveform of the second sampling clock.

17. The apparatus of claim 16, wherein the waveform parameter is configured to indicate a parameter of a periodic waveform, wherein the waveform parameter comprises at least one of: square wave output level value, sine wave output level value, triangular wave output level value, sawtooth wave output level value, and pulse output level value.

18. The apparatus of claim 17, wherein in the case that the waveform parameter is the square wave output level value, the query subunit is further configured to,

and judging the plurality of first phase addresses according to the mapping relation, and obtaining the waveform of the second sampling clock according to a judgment result.

19. The apparatus according to claim 17, wherein in the case that the waveform parameter is the sine wave output level value, the query subunit is further configured to obtain a plurality of sine wave output level values corresponding to the plurality of first phase addresses according to the mapping relationship and the plurality of first phase addresses;

the recovery unit further comprises a digital-to-analog converter (DAC) subunit configured to perform digital-to-analog conversion on the plurality of sine wave output level values to obtain a waveform of the second sampling clock.

20. The apparatus of claim 14, wherein the receiving unit further comprises:

a PWM decoding subunit configured to decode the clock signal to recover the first input clock and extract the first frequency control word carried in the clock signal.

21. A clock transmission system, comprising:

an input unit configured to input a first input clock and a second input clock;

a receiving unit configured to receive the clock signal and determine the first input clock and the first frequency control word according to the clock signal;

a recovery unit configured to determine the second input clock according to the first input clock and the first frequency control word.

22. The system of claim 21, further comprising:

a line unit disposed between the transmitting unit and the receiving unit, the line unit configured to transmit the clock signal to the receiving unit through the same line.

23. A clock transmission method applied to a transmission side, the method comprising:

inputting a first input clock and a second input clock;

acquiring a first sampling clock according to the first input clock, acquiring a second sampling clock according to the second input clock, and determining a first frequency control word according to the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate a relationship between the first sampling clock and the second sampling clock;

generating a clock signal according to the first input clock, and sending the clock signal to a receiving side; wherein the clock signal carries at least the first frequency control word.

24. The method of claim 23, wherein the first frequency control word is used to indicate at least one of: a ratio of the clock frequencies of the first and second sampling clocks, a difference in the clock frequencies of the first and second sampling clocks.

25. The method of claim 24, wherein determining a first frequency control word from the first sampling clock and the second sampling clock comprises:

sampling a clock frequency of the first sampling clock and a clock frequency of the second sampling clock, respectively, to determine the first frequency control word.

26. The method of claim 25, wherein the separately sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock to determine the first frequency control word comprises:

accumulating clock edges of the first sampling clock;

judging the clock edge of the second sampling clock, and counting the clock edge of the second sampling clock according to a judgment result;

and when the clock edge of the first sampling clock is accumulated to a preset value, determining the count value of the clock edge of the second sampling clock to obtain the first frequency control word.

27. The method of any of claims 23 to 26, wherein said deriving a first sampling clock from said first input clock comprises:

the first input clock is subjected to frequency multiplication according to a preset first multiple to obtain a first sampling clock; wherein a ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

28. The method of claim 27, wherein the multiplying the first input clock according to a preset first multiple to obtain the first sampling clock, further comprises:

the first input clock is subjected to frequency multiplication according to a preset second multiple to obtain a first sending clock; wherein the first transmit clock is used to generate the clock signal;

and carrying out frequency multiplication on the first sending clock according to a preset third multiple to obtain the first sampling clock.

29. The method of claim 28, wherein said deriving a second sampling clock from said second input clock comprises:

and multiplying the second input clock according to a preset fourth multiple to obtain the second sampling clock.

30. The method of claim 29, wherein the first multiple, the second multiple, the third multiple, and the fourth multiple are further carried in the clock signal.

31. The method of any one of claims 23 to 26, wherein generating a clock signal according to the first input clock and transmitting the clock signal to a receiving side, further comprises:

filtering the first frequency control word according to a preset filtering mode;

generating the clock signal according to the first input clock, and sending the clock signal to the receiving side; wherein the clock signal carries the filtered first frequency control word.

32. The method of claim 31, wherein determining a first frequency control word based on the first sampling clock and the second sampling clock further comprises:

the filtering the first frequency control word according to a preset filtering mode includes: taking an average of a plurality of the first frequency control words as the first frequency control word after filtering.

33. The method of claim 23, wherein generating a clock signal according to the first input clock comprises:

encoding the first input clock to generate the clock signal and enveloping the first frequency control word in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

34. The method of claim 23, further comprising:

inputting the first input clock, the second input clock and a third input clock;

determining the first frequency control word according to the first sampling clock and the second sampling clock;

acquiring a third sampling clock according to the third input clock, and determining a second frequency control word according to the first sampling clock and the third sampling clock; wherein the second frequency control word is used to indicate a relationship between the first sampling clock and the third sampling clock;

generating the clock signal according to the first input clock, and sending the clock signal to the receiving side; wherein the clock signal carries at least the first frequency control word and the second frequency control word.

35. The method of claim 23, wherein a frequency source of the first input clock is different from a frequency source of the second input clock.

36. A clock receiving method applied to a receiving side, the method comprising:

receiving a clock signal sent by a sending side; the clock signal is generated according to a first input clock of the transmitting side, the clock signal at least carries a first frequency control word, the first frequency control word is used for indicating a relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock of the transmitting side according to the preset rule;

determining the first input clock and the first frequency control word according to the clock signal;

and determining the second input clock according to the first input clock and the first frequency control word.

37. The method of claim 36, wherein determining the second input clock from the first input clock and the first frequency control word comprises:

determining the second sampling clock according to the plurality of first phase addresses, and determining the second input clock according to the second sampling clock.

38. The method of claim 37, wherein obtaining the first sampling clock from the first input clock and determining a plurality of first phase addresses from the first sampling clock and the first frequency control word comprises:

accumulating the first frequency control word according to a clock edge of the first sampling clock, and obtaining a plurality of first phase addresses according to each accumulation result of the first frequency control word;

the determining the second sampling clock according to the plurality of first phase addresses comprises:

obtaining the waveform of the second sampling clock according to the mapping relation between the plurality of first phase addresses and a preset value; the mapping relation is used for indicating the mapping relation between the first phase address and the waveform parameter preset by the second sampling clock;

and determining the clock frequency of the second sampling clock according to the waveform of the second sampling clock.

39. The method of claim 38, wherein the waveform parameter is used to indicate a parameter of a periodic waveform, wherein the waveform parameter comprises at least one of: square wave output level value, sine wave output level value, triangular wave output level value, sawtooth wave output level value, and pulse output level value.

40. The method as claimed in claim 39, wherein said obtaining the waveform of the second sampling clock according to the mapping relationship between the plurality of first phase addresses and the predetermined mapping relationship in case that the waveform parameter is the square wave output level value comprises:

and judging the plurality of first phase addresses according to the mapping relation, and obtaining the waveform of the second sampling clock according to a judgment result.

41. The method as claimed in claim 39, wherein said deriving the waveform of the second sampling clock according to the mapping relationship between the plurality of first phase addresses and the predetermined mapping relationship in case that the waveform parameter is the sine wave output level value comprises:

obtaining a plurality of sine wave output level values corresponding to the plurality of first phase addresses according to the mapping relation between the plurality of first phase addresses and the mapping relation;

performing digital-to-analog conversion on the plurality of sine wave output level values to obtain a waveform of the second sampling clock.

42. The method according to claim 39, wherein the clock signal further carries a second frequency control word, the second frequency control word is used to indicate a relationship between the first sampling clock and a third sampling clock, and the third sampling clock is determined by a third input clock of the transmitting side according to a preset rule;

the method further comprises the following steps:

determining the second frequency control word according to the clock signal;

determining the third input clock according to the first input clock and the second frequency control word.

43. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 23 to 36 when executed, or to perform the method of any of claims 36 to 42.

44. An electronic apparatus comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 23 to 36, or to perform the method of any of claims 36 to 42.

Technical Field

The embodiment of the invention relates to the field of communication, in particular to a clock sending device and method, a clock receiving device and method.

Background

With the continuous improvement of network throughput, the types of service cards and rack slots in communication equipment such as high-capacity switches and routers are more and more. Clock distribution corresponding to various services is an indispensable function in communication equipment, and generally speaking, the communication equipment needs to receive various frequency source clocks of external lines, and the number of the clocks is from 1 to infinity. For example, for a 20-slot system, 40 lines need to be arranged for the uplink and downlink clock lines; if the system has two clocks with different frequency sources for transmitting and returning, 80 lines are required to be arranged, if a differential wiring mode is further adopted, 160 lines are required to be arranged in total, and the number of the lines corresponding to the clocks is increased in a multiplied mode along with the increase of the number of the clocks with the different frequency sources in each slot position.

Furthermore, in the communication device, the lines are usually required to be continuously arranged for tens of centimeters, and in some large-scale communication devices, even more than one meter is required to be continuously arranged for completing the connection.

In view of the above problems in the related art that the clock line layout of the communication device is too complex and difficult to implement in the clock distribution process, no effective solution has been proposed in the related art.

Disclosure of Invention

The embodiment of the invention provides a clock sending device and method, a clock receiving device and method, and aims to at least solve the problems that in the related art, the layout of clock lines is too complex and difficult to realize in the clock distribution process of communication equipment.

According to an embodiment of the present invention, there is provided a clock transmission apparatus including:

an input unit configured to input a first input clock and a second input clock;

According to another embodiment of the present invention, there is also provided a clock receiving apparatus including:

a recovery unit configured to determine the second input clock according to the first input clock and the first frequency control word.

According to another embodiment of the present invention, there is also provided a clock transmission system including:

an input unit configured to input a first input clock and a second input clock;

a receiving unit configured to receive the clock signal and determine the first input clock and the first frequency control word according to the clock signal;

a recovery unit configured to determine the second input clock according to the first input clock and the first frequency control word.

According to another embodiment of the present invention, there is also provided a clock transmission method applied to a transmission side, including:

inputting a first input clock and a second input clock;

generating a clock signal according to the first input clock, and sending the clock signal to a receiving side; wherein the clock signal carries at least the first frequency control word.

According to another embodiment of the present invention, there is also provided a clock receiving method applied to a receiving side, the apparatus including:

determining the first input clock and the first frequency control word according to the clock signal;

and determining the second input clock according to the first input clock and the first frequency control word.

According to another embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to, when executed, perform the steps of any of the above method embodiments.

According to another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the embodiment of the invention, when the clock is sent at the sending end, for the first input clock and the second input clock to be sent which are input by the input unit, the first sampling clock determined by the first input clock according to the preset rule and the second sampling clock determined by the second input clock according to the preset rule are obtained through the sampling unit, and the first frequency control word for indicating the relationship between the first sampling clock and the second sampling clock is determined according to the first sampling clock and the second sampling clock; further, the sending unit generates a clock signal carrying a first frequency control word according to the first input clock and sends the clock signal to the receiving side; therefore, the clock sending device in the embodiment of the invention can send the first input clock and the second input clock simultaneously, and has no limitation on whether the first input clock and the second input clock are homologous. Therefore, the embodiment of the invention can solve the problems that the clock circuit layout is too complicated and difficult to realize in the clock distribution process of the communication equipment in the related art, so as to remarkably simplify the layout of the clock circuit in the clock distribution process, thereby reducing the cost in the manufacture of the backboard.

Drawings

FIG. 1 is a schematic diagram of a connection for clock distribution provided according to the related art;

FIG. 2 is a functional diagram of a clock transmitter according to an embodiment of the present invention;

fig. 3 is a functional diagram (two) of a clock transmission device according to an embodiment of the present invention;

fig. 4 is a functional diagram (three) of a clock transmission device provided according to an embodiment of the present invention;

fig. 5 is a functional diagram (four) of a clock transmission device provided according to an embodiment of the present invention;

fig. 6 is a functional diagram (five) of a clock transmission device according to an embodiment of the present invention;

fig. 7 is a functional diagram (six) of a clock transmission device according to an embodiment of the present invention;

FIG. 8 is a functional diagram of a clock receiving apparatus according to an embodiment of the present invention;

FIG. 9 is a functional diagram of a clock receiving apparatus according to an embodiment of the present invention (II);

fig. 10 is a functional diagram (three) of a clock receiving apparatus according to an embodiment of the present invention;

fig. 11 is a functional diagram (four) of a clock receiving apparatus according to an embodiment of the present invention;

FIG. 12 is a topology diagram of a clock networking provided in accordance with an exemplary embodiment of the present invention;

FIG. 13 is a topology diagram (one) of an internal implementation of clock networking provided in accordance with an embodiment of the present invention;

FIG. 14 is a schematic diagram of framing provided in accordance with an exemplary embodiment of the present invention;

FIG. 15 is a schematic diagram of PWM coding based on duty cycle modulation provided in accordance with an exemplary embodiment of the present invention;

FIG. 16 is a schematic diagram of a PWM encoding based on Manchester encoding according to an exemplary embodiment of the present invention;

FIG. 17 is a topology diagram (two) of an internal implementation of clock networking provided in accordance with an embodiment of the present invention;

FIG. 18 is a functional schematic diagram of a clock transmission system provided in accordance with an embodiment of the present invention;

fig. 19 is a flowchart of a clock transmission method provided according to an embodiment of the present invention;

fig. 20 is a flowchart of a clock transmission system provided according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

To further describe the clock transmitting apparatus and method, the clock receiving apparatus and method in the embodiments of the present invention, the following describes application scenarios of the clock transmitting apparatus and method, and the clock receiving apparatus in the embodiments of the present invention:

fig. 1 is a schematic diagram of clock distribution connection provided according to the related art, and as shown in fig. 1, in the related art, for clock lines corresponding to non-homologous clocks, connection transmission needs to be performed in a point-to-point manner, that is, the non-homologous clocks respectively and fixedly occupy one clock line, and a sending module transfers the clocks to a clock board or a receiving module of a service board in an uplink or downlink manner, so that the receiving module can respectively lock and recover the corresponding non-homologous clocks.

In the process of laying the lines, the clock signals of each different frequency source need to fixedly occupy a point-to-point physical transmission medium, and the clock signals of the different frequency sources are transmitted by using a physical link, that is, when two or more clock lines are combined, the receiving module cannot lock all the frequency sources, so that the transmission of non-homologous clocks on the same line cannot be realized in the related art. Therefore, in the related art, the non-homologous clock needs to additionally occupy a Printed Circuit Board (PCB) routing space, a connector pin distribution space, and the like in the backplane of the communication device, so that in the process of laying the clock lines of more than two frequency sources, routing, PCB layering, and connector increasing numbers must be performed, and further, the space of the current miniaturized backplane is difficult to implement the laying of the clock lines.

In view of the above, embodiments of the present invention provide a clock transmitting apparatus and method, and a clock receiving apparatus and method, so as to implement transmission of clocks of different frequency sources through the same clock line between a transmitting side and a receiving side; the clock transmitting device and the clock receiving device in the embodiment of the invention are respectively used for a transmitting side and a receiving side in the clock distribution process in the communication equipment. The clock transmitting device and method, and the clock receiving device and method in the embodiments of the present invention are described below:

an embodiment of the present invention provides a clock sending apparatus, and fig. 2 is a functional schematic diagram (i) of the clock sending apparatus provided in the embodiment of the present invention, as shown in fig. 2, the apparatus in the embodiment of the present invention includes:

an input unit 102 configured to input a first input clock and a second input clock;

the sampling unit 104 is configured to obtain a first sampling clock and a second sampling clock, and determine a first frequency control word according to the first sampling clock and the second sampling clock; the first frequency control word is used for indicating the relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by a first input clock according to a preset rule, and the second sampling clock is determined by a second input clock according to the preset rule;

a transmitting unit 106 configured to generate a clock signal according to a first input clock and transmit the clock signal to a receiving side; the clock signal carries at least a first frequency control word.

In the embodiment of the present invention, the input unit may be implemented by an input port, and the first input clock and the second input clock input by the input unit may be homologous or non-homologous.

After the first input clock and the second input clock are simultaneously input to the input unit of the clock sending unit, the first sampling clock and the second sampling clock can be determined by the first input clock and the second input clock according to a preset rule. It should be noted that the preset rule for the first input clock may be the same as or different from the preset rule for the second input clock, and in an example, the first input clock may be subjected to frequency multiplication processing to obtain a first sampling clock, and the first sampling clock is transmitted to the sampling unit, and the second input clock may be directly transmitted to the sampling unit as the second sampling clock without being processed; or, the first input clock and the second input clock are respectively multiplied by different multiples to obtain the first sampling clock and the second sampling clock. Fig. 3 is a functional schematic diagram (ii) of a clock transmission apparatus according to an embodiment of the present invention, and as shown in fig. 3, the clock transmission apparatus according to the embodiment of the present invention may further include:

a frequency doubling unit 108 configured to frequency-double the first input clock according to a preset first multiple to obtain a first sampling clock; and the ratio of the clock frequency of the first sampling clock to the clock frequency of the second sampling clock is within a preset range.

It should be noted that, the frequency doubling unit frequency-doubles the first input clock, so that the ratio of the clock frequency between the frequency doubled first input clock, that is, the first sampling clock and the second sampling clock, is within a preset range, so that in the confirmation process of the first frequency control word, the time for sampling or confirmation by the sampling unit can be controlled, and further, the processing efficiency of the clock transmission device in the embodiment of the present invention is improved. Those skilled in the art can select the multiple times of the frequency doubling unit according to the actual clock frequencies of the first input clock and the second input clock, such as the first multiple mentioned above, which is not limited by the present invention.

Optionally, the frequency doubling unit 108 may further include:

a first frequency multiplication subunit 1082, configured to multiply the first input clock by a preset second multiple to obtain a first transmit clock; the first sending clock is used for the sending unit to generate a clock signal according to the first sending clock;

the second frequency multiplication sub-unit 1084 is configured to multiply the first transmit clock by a preset third multiple to obtain the first sampling clock.

Through the first frequency multiplication subunit and the second frequency multiplication subunit, the first input clock is subjected to first-stage frequency multiplication through the first frequency multiplication subunit to obtain a first sending clock, the first sending clock is sent to the sending unit to generate a clock signal, and meanwhile, the first sending clock is subjected to second-stage frequency multiplication through the second frequency multiplication subunit to obtain a first sampling clock.

On the other hand, for the second input clock, in the case that the second input clock is a low frequency clock, such as: 1001hz, 4002hz, 8003hz, etc., if the low-frequency second input clock is directly used as the second sampling clock, the low-frequency clock cannot be effectively determined or counted during sampling or confirmation by the sampling unit, which results in a certain error. Therefore, the frequency doubling unit in the embodiment of the present invention may further include a third frequency doubling unit 1086 configured to double the frequency of the second input clock according to a preset fourth multiple, so as to obtain the second sampling clock.

It should be noted that, the frequency doubling unit in the embodiment of the present invention, or the first frequency doubling subunit, the second frequency doubling subunit, and the third frequency doubling subunit included in the frequency doubling unit may be implemented by a frequency doubling device or a frequency doubling manner, such as a pulse erasing gate, a phase-locked loop, a Voltage Controlled Oscillator (VCO), a locked frequency division, and the like, which is not limited in this respect; the way of multiplying a fixed-frequency clock is known to those skilled in the art, and the embodiments of the present invention are not described herein again.

In the embodiment of the present invention, the first frequency control word may indicate the relationship between the first sampling clock and the second sampling clock in various ways, and in an example, the first frequency control word may indicate a ratio of clock frequencies of the first sampling clock and the second sampling clock, or a difference value of the clock frequencies of the first sampling clock and the second sampling clock; it should be noted that the above ratio or difference is only used to more clearly describe the relationship between the first sampling clock and the second sampling clock indicated by the first frequency control word, and any parameter or mathematical relationship that can indicate the relationship between the first sampling clock and the second sampling clock can be used as the first frequency control word in the embodiment of the present invention.

In the process of determining the first frequency control word, the sampling unit in the embodiment of the present invention may determine the first frequency control word by sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock, respectively.

It should be noted that, in an example, the sampling unit in the embodiment of the present invention may be implemented by a counter, that is, sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock by counting clock edges through the counter; in another example, the sampling unit in the embodiment of the present invention may also be implemented by a frequency meter, that is, the sampling frequencies of the first sampling clock and the second clock are directly measured by the frequency meter, so as to implement sampling of the clock frequency of the first sampling clock and the clock frequency of the second sampling clock. The following description is made in a manner of implementing sampling of the clock frequency of the first sampling clock and the clock frequency of the second sampling clock by counting clock edges by a counter in the above example:

fig. 4 is a functional schematic diagram (three) of the clock transmission apparatus provided in the embodiment of the present invention, and as shown in fig. 4, the sampling unit 104 optionally includes:

a transmit accumulation subunit 1042 configured to accumulate clock edges of the first sampling clock;

a transmission decision subunit 1044 configured to decide a clock edge of the second sampling clock;

the counting subunit 1046 is configured to count the clock edge of the second sampling clock according to the decision result of the sending decision subunit, and determine a count value of the clock edge of the second sampling clock when the clock edge of the first sampling clock is accumulated to a preset value, so as to obtain the first frequency control word.

In the sampling unit shown in fig. 4, the first sampling clock is sent to the sending and accumulating subunit to accumulate the clock edge, usually the upper edge, of the first sampling clock, and meanwhile, the second sampling clock is sent to the sending and deciding subunit to decide the clock edge, usually the upper edge, of the second sampling clock, and the counting subunit can count the clock edge of the second sampling clock according to the decision result. When the result of the sending and accumulating subunit accumulating the clock edges of the first sampling clock reaches the preset threshold, the counting subunit may be enabled to perform latching and clearing, the current count value of the clock edge of the second sampling clock in the latched state may constitute the first frequency control word in the embodiment of the present invention, and the cleared counter may count the clock edge of the second sampling clock again.

In the above sampling unit, the transmission accumulation subunit may be formed by an accumulator, for example, 2^NAn accumulator; the transmission decision subunit may be constituted by a decider and the counting subunit may be constituted by a counter. In one example, the transmit accumulation subunit is taken as 2^NThe accumulator is illustrated as an example: the first sampling clock is set to 1000000080hz, and the second sampling clock is set to 10000004hz, 2^NIf N in the accumulator is 32, the sampling unit works as follows:

2^Nthe accumulator accumulates the number of rising edges of 1000000080hz clocks corresponding to the first sampling clock, meanwhile, the decision device decides 10000004hz clock rising edges corresponding to the second sampling clock, and the counter counts the rising edges of the second sampling clock according to the decision result; when 2 is in^NAnd after the accumulator accumulates the number of rising edges of the power of 2^32, the counter latches the number of rising edges of the current second sampling clock. For example, 2^NThe accumulator accumulates the first sampling clock to 4294967296(2^32) rising edges, and the number of rising edges of the second sampling clock latched by the counter is 42949687, and the 42949687 is the first frequency control word for the second sampling clock.

It should be noted that, since the counter can only record an integer, the obtained first frequency control word is an integer, and therefore, there is a certain error. Fig. 5 is a functional schematic diagram (four) of a clock transmission apparatus provided in an embodiment of the present invention, and as shown in fig. 5, for a possible error of the first frequency control word, the clock transmission unit in an embodiment of the present invention may further include:

the filtering unit 110 is configured to filter the first frequency control word according to a preset filtering manner, and send the filtered first frequency control word to the sending unit, so that the sending unit carries the filtered first frequency control word in the clock signal.

It should be noted that, there may be multiple filtering manners preset in the filtering unit, in one example, the filtering unit may use average filtering as the filtering manner, and in another example, the filtering unit may also use sliding average filtering as the filtering manner. For any filtering method, the sampling unit is required to provide multiple sets of data, i.e. multiple first frequency control words, and the filtering process of the first frequency control words is described as follows by means of mean filtering:

causing the sampling unit to repeatedly perform the following operations to obtain a plurality of first frequency control words: and determining a first frequency control word according to the first sampling clock and the second sampling clock. Specifically, based on 2 in the above example^NAn example of a sample unit of an accumulator and counter is illustrated, the counter being at 2^NThe accumulator accumulates the rising edge number of the first sampling clock to reach 2^NAt one time, the counter latches and clears, and outputs a first frequency control word (denoted as K)₁) (ii) a After the counter is cleared, 2^NThe accumulator continues to accumulate the number of rising edges of the first sampling clock and the counter resumes counting the rising edges of the second sampling circuit, at 2^NThe accumulator accumulates the rising edge number of the first sampling clock to reach 2 again^NAt one time, the counter latches and clears, and outputs a first frequency control word (denoted as K)₂) (ii) a Reciprocating in this way, i.e. the counter is at 2^NThe accumulator accumulates the rising edge number of the first sampling clock to reach 2^NAll can output a frequency control word (marked as K)₁、K₂……K_MAnd M is a positive integer greater than 1).

The counter outputs the above K₁、K₂……K_MThen, the filter unit can be based on K₁、K₂……K_MIs taken as the first frequency control word after filtering (denoted as K), then K should satisfy (K)₁、K₂……K_M)/M。

On one hand, the filtered first frequency control word output by the filtering unit can be a non-integer, and on the other hand, convergence stabilization can be performed on a jitter phenomenon possibly existing in the first frequency control word output by a certain sampling unit, so that the error can be effectively reduced by the filtered first frequency control word.

After the output of the first frequency control word is completed, the sending unit in the embodiment of the present invention may carry the first frequency control word in a clock signal generated based on the first input clock, so as to send the first frequency control word to the receiving side through a clock line. The sending unit may include a sending port for connecting a clock line, fig. 6 is a functional schematic diagram (five) of the clock sending apparatus provided in the embodiment of the present invention, and as shown in fig. 6, the sending unit 106 in the embodiment of the present invention may further include:

a Pulse Width Modulation (PWM) encoding subunit 1062 configured to encode the first input clock to generate a clock signal, and envelope a first frequency control word in the clock signal; the clock frequency of the clock signal is the clock frequency of the first input clock.

The PWM encoding unit in the embodiment of the present invention may modulate the first frequency control word into a PWM wave-based clock signal based on the first input clock to transmit to the receiving side. The modulation process of the PWM wave may be a duty cycle modulation method, a manchester encoding method, an 8B/10B encoding method, a 64B/66B encoding method, and the like, which is not limited in the present invention.

The PWM coding subunit may employ a Direct Digital Synthesis (DDS) signal generator with coding capability, a Digital Controlled Oscillator (DCO), a Digital Phase Locked Loop (DPLL), a single Chip, a field programmable gate array processor, or an application specific Integrated Circuit (IC), a System-on-a-Chip (SOC). The PWM coding subunit is formed by one or more of the above devices, that is, any device capable of coding and synthesizing the first input clock into the PWM wave carrying the first frequency control word may form the PWM coding subunit in the embodiment of the present invention.

It should be noted that, in the above example, when the clock sending apparatus in the embodiment of the present invention includes a frequency doubling unit and a filtering unit, the clock signal also needs to carry frequency doubling multiples of the frequency doubling unit, for example, a first multiple, a second multiple, a third multiple, a fourth multiple, and the like, and the first frequency control word carried in the clock signal is a filtered frequency control word.

With the clock transmission apparatus in the embodiment of the present invention, when the clock is transmitted at the transmitting end, for a first input clock and a second input clock to be transmitted, which are input by the input unit, a first sampling clock determined by the first input clock according to a preset rule and a second sampling clock determined by the second input clock according to the preset rule are obtained by the sampling unit, and a first frequency control word indicating a relationship between the first sampling clock and the second sampling clock is determined according to the first sampling clock and the second sampling clock; further, the sending unit generates a clock signal carrying a first frequency control word according to the first input clock and sends the clock signal to the receiving side; therefore, the clock sending device in the embodiment of the invention can send the first input clock and the second input clock simultaneously, and has no limitation on whether the first input clock and the second input clock are homologous. Therefore, the embodiment of the invention can solve the problems that the clock circuit layout is too complicated and difficult to realize in the clock distribution process of the communication equipment in the related art, so as to remarkably simplify the layout of the clock circuit in the clock distribution process, thereby reducing the cost in the manufacture of the backboard.

It should be noted that, by using the clock sending apparatus in the embodiment of the present invention, it is possible to implement transmission of non-homogeneous clocks in the same clock line, so that, when a communication device relates to a plurality of to-be-transmitted non-homogeneous clocks in a clock distribution process, clock transmission can be implemented only by using one clock line, and it is not necessary to separately arrange clock lines for each non-homogeneous clock, so that the number of clock lines in the clock distribution process is significantly reduced, and the utilization of the routing space of the backplane is significantly improved. Meanwhile, by the clock sending device in the embodiment of the invention, the back plate does not need to expand the routing, the PCB layer or the connector and the like aiming at excessive lines in the manufacturing process, so that the manufacturing cost of the back plate can be obviously improved.

It should be noted that, in the embodiment of the present invention, there may be a plurality of second input clocks, that is, the clock sending apparatus in the embodiment of the present invention may implement simultaneous sending of any number of non-homologous clocks, fig. 7 is a functional schematic diagram (six) of the clock sending apparatus provided according to the embodiment of the present invention, as shown in an example shown in fig. 7, the clock sending apparatus in the embodiment of the present invention may send three non-homologous clocks to a receiving side at the same time, and the following describes the example:

optionally, the clock sending apparatus in the embodiment of the present invention further includes:

an input unit 102 configured to input a first input clock, a second input clock, and a third input clock;

a sampling unit 104 including a first sampling sub-unit 1104 and a second sampling sub-unit 2104; wherein the content of the first and second substances,

the first sampling subunit 1104 is configured to determine a first frequency control word according to the first sampling clock and the second sampling clock;

the second sampling subunit 2014 is configured to determine a second frequency control word according to the first sampling clock and the third sampling clock; the second frequency control word is used for indicating the relation between the first sampling clock and a third sampling clock, and the third sampling clock is determined by a third input clock according to a preset rule;

a transmitting unit 106 configured to generate a clock signal according to a first input clock and transmit the clock signal to a receiving side; the clock signal at least carries a first frequency control word and a second frequency control word.

It should be noted that, the working processes of the first sampling subunit and the second sampling subunit refer to the description of the working process of the sampling unit, and therefore, the description thereof is omitted here.

Therefore, in the process of sending a plurality of non-homologous clocks, the clock sending device in the embodiment of the invention can set a corresponding adoption module for any one non-homologous clock, and further determine the frequency control word corresponding to the non-homologous clock by taking the first input clock as a comparison.

It should be noted that the first input clock in the embodiment of the present invention may be any one of a plurality of non-homogeneous clocks that the transmitting side needs to transmit to the receiving side, or may be a reference clock of the transmitting side.

Fig. 8 is a functional schematic diagram (one) of the clock receiving apparatus according to the embodiment of the present invention, and as shown in fig. 8, the apparatus in the embodiment of the present invention includes:

a receiving unit 202 configured to receive a clock signal transmitted by a transmitting side; the clock signal is generated according to a first input clock of a sending side, the clock signal at least carries a first frequency control word, the first frequency control word is used for indicating the relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock of the sending side according to the preset rule; the receiving unit 202 is further configured to determine a first input clock and a first frequency control word according to the clock signal;

the recovery unit 204 is configured to determine the second input clock according to the first input clock and the first frequency control word.

It should be noted that, a clock signal received by the clock receiving apparatus in the embodiment of the present invention is a clock signal transmitted by the clock transmitting apparatus in the embodiment of the present invention, and therefore, for a generation process or a preamble processing process of the clock signal by the clock transmitting apparatus, a description in the clock transmitting apparatus is corresponding, and is not repeated herein.

The receiving unit in this embodiment of the present invention is configured to receive a clock signal sent by a sending side through a clock line, the receiving unit may include a receiving port for connecting the clock line, fig. 9 is a functional schematic diagram (ii) of the receiving unit provided in this embodiment of the present invention, and as shown in fig. 9, the receiving unit may further include a PWM decoding subunit 2022 configured to decode the clock signal to recover a first input clock and extract a first frequency control word carried in the clock signal.

It should be noted that, in the embodiment of the present invention, when the clock signal is a PWM wave encoded and synthesized by the PWM encoding subunit at the transmitting side, the receiving unit may decode and recover the received PWM wave by the PWM decoding unit, so as to obtain the corresponding first input clock and the first frequency control word in the PWM wave.

Similar to the PWM encoding unit, the PWM decoding subunit may adopt a DDS signal generator with decoding capability, a DCO, a DPLL, a single chip, a field programmable gate array processor, or the like, or may adopt a dedicated IC, an SOC, or the like. The PWM decoding subunit is formed by one or more of the above devices, that is, any device capable of decoding the clock signal to obtain the first input clock and the first frequency control word may form the PWM decoding subunit in the embodiment of the present invention.

In an embodiment of the present invention, the first input signal and the first frequency control word obtained by the receiving unit can be sent to the recovering unit to recover the second input signal, and the recovering unit 204 can be further configured to,

acquiring a first sampling clock according to a first input clock, and determining a plurality of first phase addresses according to the first sampling clock and a first frequency control word; wherein the first phase address is used to indicate a phase of a second sampling clock;

a second sampling clock is determined from the plurality of first phase addresses and the second input clock is determined from the second sampling clock.

It should be noted that, if the clock sending device for sending the clock signal includes the aforementioned frequency doubling unit, that is, the first sampling clock or the second sampling clock is obtained by frequency doubling the first input clock or the second input clock according to a preset frequency doubling multiple, the receiving unit may further obtain the carried frequency doubling multiple from the clock signal on the premise of obtaining the first input clock and the first frequency control word, for example, the first multiple, the second multiple, the third multiple, the fourth multiple, and the like in the aforementioned frequency doubling unit. In the clock receiving device in the embodiment of the present invention, after the receiving unit obtains the first input clock, the same frequency multiplication factor as that in the clock sending device is also adopted to perform frequency multiplication on the first input clock, and then the recovery unit further performs recovery on the second input clock. In an example, in the clock sending apparatus, a first sampling clock is obtained by performing frequency multiplication on a first input clock by a frequency multiplication unit by 40 times, and a second input clock is directly used as a second sampling clock without being processed, under the above situation, after the receiving unit obtains the first input clock, the first frequency control word, and the frequency multiplication factor, the clock receiving apparatus in the embodiment of the present invention needs to perform frequency multiplication processing on the first input clock by 40 times, and send the frequency-multiplied first input clock to a recovery unit for recovery. In another example, in the clock sending apparatus, a first frequency multiplication subunit in the frequency multiplication unit performs a first-stage frequency multiplication on a first input clock according to 40 times to obtain a first sending clock, a second frequency multiplication subunit performs a second-stage frequency multiplication on the first sending clock according to 20 times to obtain a first sampling clock, and a third frequency multiplication subunit performs a frequency multiplication on a second input clock according to 20 times to obtain a second sampling clock; meanwhile, for the first transmission clock, frequency division processing is required to be performed according to 1/40 times to recover the first input clock, and for the clock directly output by the recovery unit, frequency division processing is required to be performed according to 1/20 times to recover the second input clock. The process of performing frequency multiplication processing on the first input clock according to the processing mode of the clock sending device is a process of acquiring the first sampling clock according to the first input clock in the recovery unit.

It should be noted that the first phase address is used to indicate that the second sampling clock adopts a phase address of a corresponding waveform, and in an example, the second sampling clock is a square wave, or a sine wave.

It should be noted that, after the second sampling clock is determined, the second input clock can be recovered by the second sampling clock according to the rule for determining the second sampling clock according to the second input clock.

In the following, the determination process of the first phase address is described by an alternative example, fig. 10 is a functional schematic diagram (three) of the clock receiving apparatus according to the embodiment of the present invention, and as shown in fig. 10, the recovery unit 204 includes:

a receiving and accumulating subunit 2042, configured to accumulate the first frequency control word according to a clock edge of the first sampling clock, and obtain a plurality of first phase addresses according to each accumulation result of the first frequency control word;

the query subunit 2044 is configured to obtain a waveform of the second sampling clock according to the multiple first phase addresses and a preset mapping relationship; the mapping relation is used for indicating the mapping relation between the first phase address and the waveform parameter preset by the second sampling clock; the query subunit is further configured to determine a clock frequency of the second sampling clock from a waveform of the second sampling clock.

As shown in fig. 10, after the first sampling clock is sent to the receiving and accumulating subunit, the receiving and accumulating subunit may accumulate the first frequency control word according to the clock edge of the first sampling clock, so as to obtain the first phase address. In the accumulation process, when the first sampling clock reaches the clock frequency once, the receiving and accumulating subunit can accumulate the first frequency control word once according to the clock edge from the first sampling clock under the condition, and the accumulation result of each time is the first phase address, so that the receiving and accumulating subunit can obtain a plurality of first phase addresses.

In the above recovery unit, the receiving accumulation subunit may be formed by an accumulator, for example, 2^NAnd an accumulator. In one example, the receive accumulation subunit is 2^NThe accumulator is illustrated as an example: setting the first sampling clock to be 1Ghz and the first frequency control word to be 42949672, the operation of the recovery unit is as follows:

2^Nthe accumulator accumulates the upper edge of the first sampling clock according to the clock frequency of the first sampling clock, i.e. each time a rising edge of 1Ghz is reached, 2^NThe accumulator accumulates the automatic first frequency control word once, and each time the accumulation is completed, a first phase address can be obtained, and the first phase address is the accumulation result of the current time. When the accumulated result is larger than the preset threshold value, such as 2^32, then 2^NThe accumulator clears the accumulation result and starts accumulation again; the above accumulation process is as follows:

the first time to reach 1Ghz, 2^NThe accumulation result of the accumulator is 42949672 × 1 ═ 42949672, and the corresponding first phase address is 42949672;

second reaching 1Ghz, 2^NThe accumulation result of the accumulator is 42949672 × 2 ═ 85899344, and the corresponding first phase address is 85899344;

the third time reaches 1Ghz, 2^NThe accumulation result of the accumulator is 42949672 × 3 ═ 128849016, and the corresponding first phase address is 128849016;

……

the first hundred times of the reaction reach 1Ghz, 2^NThe accumulation result of the accumulator is 42949672 × 100 ═ 4294967200, and the corresponding first phase address is 4294967200;

the first hundred times reaches 1Ghz, 2 since 42949672 x 101 is 4337916872, which is greater than 2 x 32 to the power^NClearing the accumulator and restarting accumulation, 2^NThe accumulation result of the accumulator is 42949672 × 1 ═ 42949672, and the corresponding first phase address is 42949672;

the first hundred and zero times reach 1Ghz, 2^NThe accumulator accumulates 42949672 × 2 — 85899344, and the corresponding first phase address is 85899344.

For the first phase address obtained by each accumulation, the query subunit may query the waveform parameter of the second sampling clock corresponding to the current first phase address. The waveform parameter is used to indicate a parameter of the periodic waveform, wherein the waveform parameter includes at least one of: a square wave output level value, a sine wave output level value, a triangular wave output level value, a sawtooth wave output level value, a pulse output level value (i.e., an output level value corresponding to a waveform having a duty ratio other than 50%). In an example, the waveform parameter of the second sampling clock may be a sine wave output level value; in another example, the waveform parameter of the second sampling clock may be a square wave output level value. The following description is made in conjunction with the waveform parameters of the second sampling clock.

As described in the above example in which the waveform parameter is a square wave output level value, the querying subunit 2044 is further configured to determine the multiple first phase addresses according to the mapping relationship, and obtain the waveform of the second sampling clock according to the determination result.

In the above example, since the waveform parameter is a square wave output level value, the querying subunit may be directly constituted by a decision device, that is, a decision is made on the first phase address corresponding to the accumulation result of the receiving accumulation subunit according to a preset rule to determine to output a high level/a low level. The mapping relationship may be predetermined, for example, to output a low level when the first phase address is less than or equal to power 2^31, and to output a high level when the first phase address is greater than power 2^31, which is power 2^ 32. Therefore, the square wave output level values corresponding to the plurality of first phase addresses can be output through the judgment of the inquiry subunit, and the waveform of the second sampling clock is further obtained. Based on the square waveform of the second sampling clock, the clock frequency of the second sampling clock can be determined.

To illustrate the situation that the waveform parameter is a sine wave output level value in the above example, fig. 11 is a functional schematic diagram (four) of the clock receiving apparatus according to the embodiment of the present invention, as shown in fig. 11, the querying subunit 2044 is further configured to obtain a plurality of sine wave output level values corresponding to a plurality of first phase addresses according to a mapping relationship between the plurality of first phase addresses and a preset value;

the recovery unit 204 further includes a Digital-to-Analog Converter (DAC) sub-unit 2046, and the DAC sub-unit 2046 is configured to perform Digital-to-Analog conversion on the plurality of sine wave output level values to obtain a waveform of the second sampling clock.

In the above example, since the waveform parameter is a sine wave output level value, the query subunit needs to include a preset local Read-Only Memory (ROM) table, in which the mapping relationship between the first phase address and the corresponding sine wave output level value is described. Taking first phase addresses 0, 1, 2, and 3 as an example, the local ROM table stores a mapping relationship between the first phase addresses 0, 1, 2, and 3 and a sine wave output level value, where the mapping relationship may be:

0～0V；

1～1.65V；

2～3.3V；

3～1.65V；

therefore, when the first phase address corresponding to the accumulation result of the receiving accumulation subunit is 0, the query subunit may determine, through the mapping relationship described in the local ROM table, that the sine wave output level value corresponding to the first phase address is 0V, and further, the DAC subunit may output a level of 0V through digital-to-analog conversion. Therefore, the sine wave output level values corresponding to the plurality of first phase addresses can be continuously output through the inquiry subunit and the DAC subunit, and the waveform of the second sampling clock is further obtained. Based on the sine wave of the second sampling clock, the clock frequency of the second sampling clock can be determined.

It should be noted that, when the number of input clocks in the clock transmission device is more than two, correspondingly, the clock reception device in the embodiment of the present invention can also recover one of the input clocks. In an optional embodiment, the clock signal further carries a second frequency control word, where the second frequency control word is used to indicate a relationship between the first sampling clock and a third sampling clock, and the third sampling clock is determined by a third input clock of the transmitting side according to a preset rule. In the clock receiving apparatus in the embodiment of the present invention, the receiving unit may determine the second frequency control word according to the clock signal while determining the first input clock and the first frequency control word; and determining a third input clock according to the first input clock and the second frequency control word by referring to the second input clock recovery mode.

To further illustrate the clock transmitting apparatus, the clock receiving apparatus, and the clock transmission system in the embodiments of the present invention, the following description is made with reference to a plurality of exemplary embodiments. It should be noted that, in the following exemplary embodiments, the sending module is used to indicate a clock sending apparatus in the embodiment of the present invention, the receiving module is used to indicate a clock receiving module in the embodiment of the present invention, and the sending module and the receiving module together form a clock transmission system in the embodiment of the present invention.

Exemplary embodiment 1

Fig. 12 is a topological diagram of clock networking provided according to an exemplary embodiment of the present invention, and a networking structure adopted in a clock distribution process in the present exemplary embodiment is shown in fig. 12. Fig. 13 is a topology diagram (a) of an internal implementation of a clock networking according to an embodiment of the present invention, and in this exemplary embodiment, the internal implementation of a sending module and a receiving module in a clock distribution process is as shown in fig. 13. As shown in fig. 13, in the present exemplary embodiment, the clocks to be transmitted input by the transmitting module include four non-homologous clocks with different frequencies, where the four non-homologous clocks are sequentially: fundamental frequency clock F_clk25000002hz, 33000018hz, 10000004hz and 19440009hz respectively.

Fundamental frequency clock F_clkAfter 25000002hz enters the sending module, one path enters the frequency doubling unit for frequency doubling. The frequency multiplication unit in the exemplary embodiment adopts frequency multiplication of 40 times, so that the basic frequency clock becomes 40 × F_clk1000000080hz, the multiplied basic frequency clock is provided to the sampling unit A, the sampling unit B and the sampling unit C, and the edge decision and 2 are given^NThe accumulator provides a base clock. Another path F of the basic frequency clock_clk25000002hz is sent to the PWM coding unit without frequency multiplication and is provided to the PWM coding unitA base clock.

And the non-homologous clock A is 33000018hz and enters a sampling unit A, the non-homologous clock A is subjected to edge sampling judgment by a 40-frequency-multiplied basic frequency clock provided by a frequency multiplier, and the result is sent to a counter for self-addition. 40 multiplied fundamental frequency clock 40 x F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating in a single accumulation mode when the accumulation number is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock a at the present moment_AThe calculation formula is as follows:

in the above formula, C_freqAFor indicating the clock frequency, C, of a non-homologous clock A_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

For example, when N is 32, the accumulator accumulates to 4294967296 clocks with 40 times the base frequency, and the counter latches the frequency control word | K_AAnd | ≈ 141733987, which is passed to the calculation filtering unit.

Similarly, the non-homologous clock B is 10000004hz and enters the sampling unit B, the edge sampling decision is performed on the non-homologous clock B by the 40-frequency-multiplied basic frequency clock provided by the frequency multiplier, and the result is sent to the counter for self-addition. 40 multiplied fundamental frequency clock 40 x F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating in a single accumulation mode when the accumulation number is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock B at the current moment_BThe calculation formula is as follows:

in the above formula, C_freqBFor indicating the clock frequency, C, of a non-homologous clock, B_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

For example, when N is 32, the accumulator accumulates to 4294967296 clocks with 40 times the base frequency, and the counter latches the frequency control word | K_BAnd | ≈ 42949687, which is passed to the calculation filtering unit.

Similarly, the non-homologous clock C enters the sampling unit C at 19440009hz, and the edge sampling decision is performed on the non-homologous clock C by the 40-frequency-multiplied basic frequency clock provided by the frequency multiplier, and the result is sent to the counter for self-addition. 40 multiplied fundamental frequency clock 40 x F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating in a single accumulation mode when the accumulation number is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock C at the current moment_CThe calculation formula is

In the above formula, C_freqCFor indicating the clock frequency of a non-homologous clock C, C_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

For example, when N is 32, the accumulator accumulates to 4294967296 clocks with 40 times the base frequency, and the counter latches the frequency control word | K_CAnd | ≈ 83494196, which is passed to the calculation filtering unit.

It should be noted that this exemplary embodiment exemplifies 2^NN in the accumulator is 32, which is a method for better explaining frequency synthesis, N may be any number such as 8, 16, 32, 48, 64, etc., and N is a certain threshold valueThe larger the value range is, the longer the time for determining the frequency control word is, and the more accurate the precision is, and a person skilled in the art can adjust the N value according to the error precision of the system, and the embodiment of the present invention is not limited to the N value.

Due to the above K_A、K_B、K_CThe real-time frequency control words obtained for the sampling unit A, the sampling unit B and the sampling unit C are integer frequency control words with decimal parts removed, if the real-time frequency control words are directly transmitted to the recovery unit A, the recovery unit B and the recovery unit C of the receiving module, the recovered clocks are 33000018.0608hz, 10000004.0689hz and 19440008.9512hz respectively, and the frequency errors with the original non-homologous clock A, the original non-homologous clock B and the original non-homologous clock C are +1.8ppb, +6.9ppb and-2.5 ppb.

In order to further reduce errors and jitter, a real-time frequency control word K obtained by a sampling unit A, a sampling unit B and a sampling unit C is used_A、K_B、K_CAnd sending the data to a calculation filtering unit. Calculating filter unit to real-time frequency control word K_A、K_B、K_CAnd (6) filtering.

The exemplary embodiment adopts the mean filtering as a filtering mode, and the algorithm is as follows:

the algorithm indicates that the frequency control words in the sampling unit are accumulated and counted for M times, and filtering processing is realized through the average value of the M frequency control words. The accuracy of the filtering depends on the value of M.

Through the calculation of the mean value algorithm, three non-homologous frequency control words with one decimal number after filtering are obtained, wherein the three non-homologous frequency control words are sequentially as follows: k_A’＝141733986.7、K_B’＝42949686.7、K_C’＝83494196.2。

It should be noted that the filtering performed by the mean filtering algorithm in the exemplary embodiment is only an example, and a person skilled in the art may sample other filtering manners to perform filtering, which is not limited in the embodiment of the present invention.

Filtered post-frequency control word K_A’、K_B’、K_C' feeding into a PWM coding unit based on a fundamental frequency clock F_clkThree frequency control words K are framed_A’、K_B’、K_C' are separately enveloped into coded composite PWM carriers. Fig. 14 is a schematic diagram of framing provided according to an exemplary embodiment of the present invention, and as shown in fig. 14, the framing method is as follows, where 0001 denotes a frame header of a frequency control word a, and the frame header is followed by the frequency control word a; 0010 represents the frame header of the frequency control word B, followed by the frequency control word B; 0011 represents the frame header of the frequency control word C, followed by the frequency control word C; 1111 represents a frame header D of configuration information, which is followed by basic information of an accompanying frame, such as multiple information of a frequency doubling unit, sampling frequency information of a sampling unit, and the like, and finally followed by a CRC check frame.

It should be noted that the frame header may be placed in front of the frequency control word or behind the frequency control word; similarly, the frame headers 0001-1111 are exemplified in the present exemplary embodiment to better explain the framing manner, and do not refer to specific content, nor refer to the frame header capacity and whether to encrypt, and a person skilled in the art may modify and encrypt the frame headers according to the implementation manner of the service requirement.

The encoding and combining manner of the PWM encoding unit may be duty cycle modulation, and fig. 15 is a schematic diagram of PWM encoding based on duty cycle modulation according to an exemplary embodiment of the present invention, as shown in fig. 15, 0 is represented by 80% duty cycle, and 1 is represented by 20% duty cycle, or 0 is represented by 30% duty cycle, and 1 is represented by 70% duty cycle, which is not limited in this embodiment of the present invention.

It should be noted that the duty cycle modulation is used in the present exemplary embodiment to better illustrate the frequency synthesis method, and those skilled in the art may use other encoding forms, and fig. 16 is a schematic diagram of PWM encoding based on manchester encoding according to the exemplary embodiment of the present invention, that is, the present exemplary embodiment may use manchester encoding as shown in fig. 16 to perform PWM encoding, and may also use 8B/10B encoding or the like to encode PWM waves, which is not limited by the present invention.

After the PWM coding unit completes coding synthesis, the frequency control word A, the frequency control word B and the frequency control word C are all coded into the PWM carrier wave finally. The synthesized PWM carrier wave transmits the signal to a receiving module through a single transmission link. It should be noted that. The single transmission link may be a PCB trace, a connector, an optical fiber, a differential line, a link using a mixture of multiple physical media, and the like, which is not limited in the present invention.

The receiving module receives the PWM carrier transmitted by the single transmission link, then sends the PWM carrier to the PWM decoding unit for decoding, and respectively decodes the frequency control word K by identifying the frame header_A’、K_B’、K_CAnd multiple of frequency multiplying unit, multiplying K_A’、K_B’、K_C' distributing and feeding the mixture into a recovery unit A, a recovery unit B and a recovery unit C; the frequency multiplication factor is sent to a frequency multiplication unit of the receiving module; PWM decoding unit physically recovers PWM carrier basic frequency clock F_clk25000002hz, outputting a receiving module as a first path of receiving clock output; in addition, inside the receiving module, a frequency multiplication unit is introduced to the base frequency clock.

After the frequency multiplication unit of the receiving module is set to be the same as that of the frequency multiplication unit of the sending module, the input basic frequency clock F is used_clkMultiplying by 40 times to obtain 40 × F_clk1000000080 hz. The basic clock frequency of 40 times is sent to a recovery unit A, a recovery unit B and a recovery unit C to be used as a reference clock of each recovery unit.

Filtered non-homologous clock frequency control word K_A' into recovery unit A, the 40 multiplied fundamental frequency clock provided by the multiplier provides the reference clock, in K_A' accumulate as an accumulated number with an accumulator maximum of 2^NAccording to the following algorithm:

with N-32 calculation in the present exemplary embodiment, the local ROM table address is obtained by continuous accumulation. The local ROM table stores square waves with addresses corresponding to 1 and 0, and when the duty ratio of the required output clock is 50%, the data corresponding to the first half address in the ROM is '1', and the data corresponding to the second half address is '0'.

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqA33000017.990991225466132164001465hz, the difference between 33000018hz and the original non-homologous clock a is 0.272 ppb.

Likewise, the filtered non-homologous clock frequency control word K_B' into recovery unit B, the 40 multiplied fundamental frequency clock provided by the multiplier provides the reference clock, in K_B' accumulate as an accumulated number with an accumulator maximum of 2^NAccording to the following algorithm:

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqB10000003.999093299731612205505371hz, which differs from the 10000004hz corresponding to the original non-homologous clock B by 0.09 ppb.

Likewise, the filtered non-homologous clock frequency control word K_C' into recovery unit B, the 40 multiplied fundamental frequency clock provided by the multiplier provides the reference clock, in K_C' accumulate as an accumulated number with an accumulator maximum of 2^NAccording to the following algorithm:

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqC19440008.99780907109379768371582hz, which differs by 0.11ppb from the 19440009hz corresponding to the original non-homologous clock C.

It should be noted that the above-mentioned 50% duty ratio is used to better describe the determination process of the local ROM table address, and those skilled in the art may adjust the ratio and the sequence relationship of '1' and '0' corresponding to the address according to the actual duty ratio requirement, which is not limited in the present invention. Similarly, the error is only the error between the recovered non-homologous clock and the original non-homologous clock of the transmitting module in the exemplary embodiment, and in practical implementation, the error depends on the size of the N value in the accumulator, the filtering capability of the calculation filter, the depth of the local ROM table, and other factors, for example, the error may decrease with the increase of the N value or with the improvement of the filtering capability of the calculation filter, and a person skilled in the art may control or adjust the error according to actual needs.

Exemplary embodiment 2

Fig. 17 is a topology diagram (two) of an internal implementation of a clock networking according to an embodiment of the present invention, and as shown in fig. 17, in this exemplary embodiment, a clock to be transmitted input by a transmission module includes four non-homologous clocks with different frequencies, where the four non-homologous clocks are sequentially: fundamental frequency clock F_clk10000.0008hz, 8001hz, 10000004hz and 6480003 hz.

Fundamental frequency clock F_clkAfter 10000.0008hz enters the transmitting module, the frequency is multiplied by the first-stage frequency multiplying unit D. After 2500 times of frequency multiplication, d x F is obtained_clk25000002 hz. AOne path of d x F after stage frequency multiplication_clkAnd transmitting the frequency signals to a second-stage frequency multiplication unit for frequency multiplication. The present exemplary embodiment uses a frequency multiplication of 40 times to change the base frequency clock to 40 d F_clk1000000080hz, and is provided to sample unit A, sample unit B, and sample unit C, and is provided with edge decision sum 2^NThe accumulator provides a base clock. Another path d x F of primary frequency-doubled basic frequency clock_clk25000002hz is sent to the PWM coding unit without frequency multiplication, and a basic clock is provided for the PWM coding unit.

After entering the sending module, the non-homologous clock a 8001hz enters the frequency doubling unit a, performs frequency doubling by 2000 times, increases the clock frequency to 16002000hz, and then sends the clock frequency to the sampling unit a. In the sampling unit A, edge sampling judgment is carried out by a 40-frequency-multiplication basic frequency clock provided by a frequency multiplier, and the result is sent to a counter for self-addition. 40 multiplied fundamental frequency clock 40 d F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating in a single accumulation mode when the accumulation number is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock a at the present moment_AThe calculation formula is as follows:

in the above formula, C_freqAFor indicating the clock frequency, C, of a non-homologous clock A_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

For example, when N is 32, the accumulator accumulates to 4294967296 clocks with 40 times the base frequency, and the counter latches the frequency control word | K_AAnd | ≈ 68728061, which is passed to the calculation filtering unit.

Similarly, the non-homologous clock B enters the frequency doubling unit B at 10000004hz, performs single frequency doubling, i.e. keeping the clock frequency at 10000004hz, and then sends the clock frequency to the sampling unit B.In the sampling unit B, edge sampling judgment is carried out by a 40-frequency-multiplication basic frequency clock provided by a frequency multiplier, and the result is sent to a counter for self-addition. 40 multiplied fundamental frequency clock 40 d F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating in a single accumulation mode when the accumulation number is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock B at the current moment_BThe calculation formula is as follows:

in the above formula, C_freqBFor indicating the clock frequency, C, of a non-homologous clock, B_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

Similarly, the non-homologous clock C is 6480003hz, multiplied by 3 times, i.e. the clock frequency C is 19440009hz, and then sent to the sampling unit C. In the sampling unit C, edge sampling judgment is carried out by a 40-frequency-multiplication basic frequency clock provided by a frequency multiplier, and the result is sent to a counter for self-addition. 40 multiplied fundamental frequency clock 40 d F provided by frequency multiplier_clk1000000080hz feed-in 2^NAn accumulator for accumulating when the number of accumulations is equal to 2^NThen, latching and resetting the rear-stage counter; accordingly, 2^NThe accumulator is also cleared and re-accumulated. 2^NThe accumulator accumulates to 2 each time^NThe value latched by the counter, i.e. the frequency control word K of the non-homologous clock C at the current moment_CThe calculation formula is

In the above formula, C_freqCFor indicating the clock frequency of a non-homologous clock C, C_x*fclkFor indicating the clock frequency of the multiplied base frequency clock.

It should be noted that this exemplary embodiment exemplifies 2^NN in the accumulator is 32, which is a method for better explaining frequency synthesis, N may be any number such as 8, 16, 32, 48, 64, etc., and the larger the N value is within a certain threshold range, the longer the time for determining the frequency control word is, and the more accurate the accuracy is, and those skilled in the art can adjust the N value according to the error accuracy of the system, and the embodiment of the present invention is not limited to the N value.

Due to the above K_A、K_B、K_CThe real-time frequency control words respectively obtained by the sampling unit A, the sampling unit B and the sampling unit C are integer frequency control words with decimal parts removed, and in order to further reduce errors and jitter, the real-time frequency control words obtained by the sampling unit A, the sampling unit B and the sampling unit C are subjected to frequency control words K_A、K_B、K_CAnd sending the data to a calculation filtering unit. Calculating filter unit to real-time frequency control word K_A、K_B、K_CAnd (6) filtering.

The exemplary embodiment adopts the mean filtering as a filtering mode, and the algorithm is as follows:

Calculating by the mean algorithm to obtain the filtered wavelet bandThree non-homologous frequency control words of one decimal are: k_A’＝68728061.2、K_B’＝42949686.7、K_C’＝83494196.2。

Filtered post-frequency control word K_A’、K_B’、K_C' feeding into a PWM coding unit based on a fundamental frequency clock F_clkThree frequency control words K are framed_A’、K_B’、K_C' are separately enveloped into coded composite PWM carriers. The framing method can be seen in fig. 14, and the framing method is represented by using 0001 as a frame header of the frequency control word a, followed by the frequency control word a; 0010 represents the frame header of the frequency control word B, followed by the frequency control word B; 0011 represents the frame header of the frequency control word C, followed by the frequency control word C; 1111 represents a frame header D of configuration information, which is followed by basic information of an accompanying frame, such as multiple information of a frequency doubling unit, sampling frequency information of a sampling unit, and the like, and finally followed by a CRC check frame.

The encoding and synthesizing manner of the PWM encoding unit may be, as shown in fig. 5, duty ratio modulation, where 80% duty ratio represents 0 and 20% duty ratio represents 1, or 30% duty ratio represents 0 and 70% duty ratio represents 1, which is not limited in this embodiment of the present invention.

It should be noted that the present exemplary embodiment uses duty cycle modulation to better illustrate the frequency synthesis method, and those skilled in the art may encode the PWM wave by other encoding forms, such as manchester encoding, 8B/10B encoding, and the like, which is not limited by the present invention.

The receiving module receives the PWM carrier transmitted by the single transmission link, then sends the PWM carrier to the PWM decoding unit for decoding, and respectively decodes the frequency control word K by identifying the frame header_A’、K_B’、K_CAnd multiple of each frequency multiplying element, K_A’、K_B’、K_CThe frequency multiplication factor is distributed and sent into a recovery unit A, a recovery unit B and a recovery unit C, and each transmitted frequency multiplication factor is written into a frequency division unit at the rear stage of the recovery unit; d x F_clkThe frequency multiplication factor is sent to a frequency multiplication unit of the receiving module; PWM decoding unit physically recovers PWM carrier basic frequency clock d x F_clk25000002hz, and F is obtained after division by 2500 times through a division D unit_clk10000.0008hz, outputting a receiving module as a first path of receiving clock output; in addition, d x F is arranged in the receiving module_clkA frequency multiplying unit to which the base frequency clock is directed.

The frequency multiplier of the receiving module is set to have the same multiple as that of the frequency multiplier of the transmitting module, and then the input basic frequency clock d F_clkMultiplying by 40 times to obtain 40 × d × F_clk1000000080 hz. The basic clock frequency of 40 times is sent to a recovery unit A, a recovery unit B and a recovery unit C to be used as a reference clock of each recovery unit.

the local ROM table address is obtained by performing calculation with N being 32 in this embodiment. The local ROM table stores square waves with addresses corresponding to 1 and 0, and when the duty ratio of the required output clock is 50%, the data corresponding to the first half address in the ROM is '1', and the data corresponding to the second half address is '0'.

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqA16002000.006438441574573516845703hz, then the frequency is divided by 2000 times by a frequency divider which is matched with the frequency multiplication coefficient 2000 of the original sending module, and the frequency is 8001.0000032192207872867584228515hz, which is 0.402ppb different from 8001hz corresponding to the original non-homologous clock A.

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqB10000003.999093299731612205505371hz, because the frequency multiplication coefficient in the original sending module is single frequency, the latter-level frequency divider does not adjust, and the obtained non-homologous frequency has a difference of 0.09ppb from 10000004hz corresponding to the original non-homologous clock B.

The actual non-homologous clock frequency obtained by looking up the table of the addresses output by the accumulator is F_reqC19440008.99780907109379768371582hz, then the frequency is divided by 3 times by a frequency divider which matches the frequency multiplication coefficient 3 of the original sending module, the frequency is 6480002.9992696903645992279052734hz, and the difference between the frequency and 6480003hz corresponding to the original non-homologous clock C is 0.11 ppb.

An embodiment of the present invention further provides a clock transmission system, fig. 18 is a functional schematic diagram of the clock transmission system provided in the embodiment of the present invention, and as shown in fig. 18, the clock transmission system in the embodiment of the present invention includes:

an input unit 302 configured to input a first input clock and a second input clock;

a sampling unit 304 configured to obtain a first sampling clock and a second sampling clock, and determine a first frequency control word according to the first sampling clock and the second sampling clock; the first frequency control word is used for indicating the relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by a first input clock according to a preset rule, and the second sampling clock is determined by a second input clock according to the preset rule;

a transmitting unit 306 configured to generate a clock signal according to a first input clock and transmit the clock signal to a receiving side; the clock signal at least carries a first frequency control word;

a receiving unit 308 configured to receive a clock signal and determine a first input clock and a first frequency control word according to the clock signal;

the recovery unit 310 is configured to determine a second input clock according to the first input clock and the first frequency control word.

It should be noted that the input unit, the sampling unit, and the sending unit in the clock transmission system according to the embodiment of the present invention constitute corresponding units in the clock sending apparatus according to the embodiment of the present invention, correspondingly, the receiving unit and the recovery unit in the clock transmission system of the embodiment of the present invention are corresponding units in the clock receiving apparatus of the embodiment of the present invention, therefore, the clock transmission system in the embodiment of the present invention may be composed of the clock sending device and the clock receiving device in the embodiment of the present invention, the remaining optional embodiments and technical implementations of the sending side of the clock transmission system in the embodiment of the present invention correspond to the clock sending device in the embodiment of the present invention, and the remaining optional embodiments and technical implementations of the receiving side of the clock transmission system in the embodiment of the present invention correspond to the clock receiving device in the embodiment of the present invention, which is not described herein again.

In an optional embodiment, the clock transmission system in the embodiment of the present invention further includes:

a line unit 312 disposed between the transmitting unit and the receiving unit, the line unit configured to transmit the clock signal to the receiving unit through the same line.

It should be noted that the line unit in the embodiment of the present invention forms a physical link between the transmitting unit and the receiving unit in the clock transmission system, and the physical link indicated by the line unit is one, so that a plurality of input clocks on the transmitting side can be transmitted to the receiving side through the same line.

An embodiment of the present invention further provides a clock sending method applied to a sending side, fig. 19 is a flowchart of the clock sending method provided in the embodiment of the present invention, and as shown in fig. 19, the clock sending method in the embodiment of the present invention includes:

s102, inputting a first input clock and a second input clock;

s104, acquiring a first sampling clock according to the first input clock, acquiring a second sampling clock according to the second input clock, and determining a first frequency control word according to the first sampling clock and the second sampling clock; the first frequency control word is used for indicating the relation between the first sampling clock and the second sampling clock;

s106, generating a clock signal according to the first input clock, and sending the clock signal to a receiving side; the clock signal carries at least a first frequency control word.

It should be noted that other optional embodiments and technical implementations of the clock sending method in the embodiment of the present invention correspond to the clock sending apparatus in the embodiment of the present invention, and are not described herein again.

In an alternative embodiment, the first frequency control word is used to indicate at least one of the following objects: a ratio of the clock frequencies of the first and second sampling clocks, a difference in the clock frequencies of the first and second sampling clocks.

In an optional embodiment, the determining the first frequency control word according to the first sampling clock and the second sampling clock in step S104 includes:

the clock frequency of the first sampling clock and the clock frequency of the second sampling clock are sampled, respectively, to determine a first frequency control word.

In an optional embodiment, the sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock respectively to determine the first frequency control word includes:

accumulating clock edges of the first sampling clock;

judging the clock edge of the second sampling clock, and counting the clock edge of the second sampling clock according to the judgment result;

and when the clock edge of the first sampling clock is accumulated to a preset value, determining the count value of the clock edge of the second sampling clock to obtain a first frequency control word.

In an optional embodiment, in the step S104, acquiring the first sampling clock according to the first input clock includes:

the method comprises the steps that frequency multiplication is carried out on a first input clock according to a preset first multiple to obtain a first sampling clock; and the ratio of the clock frequency of the first sampling clock to the clock frequency of the second sampling clock is within a preset range.

In an optional embodiment, the frequency doubling the first input clock according to a preset first multiple to obtain the first sampling clock further includes:

frequency multiplication is carried out on the first input clock according to a preset second multiple to obtain a first sending clock; wherein the first transmit clock is used to generate a clock signal;

and carrying out frequency multiplication on the first sending clock according to a preset third multiple to obtain a first sampling clock.

In an optional embodiment, in the step S104, obtaining the second sampling clock according to the second input clock includes:

and multiplying the second input clock according to a preset fourth multiple to obtain a second sampling clock.

In an optional embodiment, the clock signal further carries a first multiple, a second multiple, a third multiple, and a fourth multiple.

In an optional embodiment, in the step S106, generating a clock signal according to the first input clock, and sending the clock signal to the receiving side, further includes:

filtering the first frequency control word according to a preset filtering mode;

generating a clock signal according to a first input clock, and transmitting the clock signal to a receiving side; the clock signal carries the filtered first frequency control word.

In an optional embodiment, in step S104, determining the first frequency control word according to the first sampling clock and the second sampling clock further includes:

repeatedly performing the following operations to obtain a plurality of first frequency control words: determining a first frequency control word according to the first sampling clock and the second sampling clock;

filtering the first frequency control word according to a preset filtering mode, comprising: and taking the average value of the plurality of first frequency control words as the filtered first frequency control word.

In an alternative embodiment, the step S106 of generating a clock signal according to the first input clock includes:

encoding a first input clock to generate a clock signal, and enveloping a first frequency control word in the clock signal; the clock frequency of the clock signal is the clock frequency of the first input clock.

In an optional embodiment, the clock sending method in the embodiment of the present invention further includes:

inputting a first input clock, a second input clock and a third input clock;

determining a first frequency control word according to the first sampling clock and the second sampling clock;

acquiring a third sampling clock according to a third input clock, and determining a second frequency control word according to the first sampling clock and the third sampling clock; the second frequency control word is used for indicating the relation between the first sampling clock and the third sampling clock;

generating a clock signal according to a first input clock, and transmitting the clock signal to a receiving side; the clock signal at least carries a first frequency control word and a second frequency control word.

In an alternative embodiment, the frequency source of the first input clock is different from the frequency source of the second input clock.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

An embodiment of the present invention further provides a clock receiving method applied to a receiving side, where fig. 20 is a flowchart of the clock receiving method provided in the embodiment of the present invention, and as shown in fig. 20, the clock receiving method in the embodiment of the present invention includes:

s202, receiving a clock signal sent by a sending side; the clock signal is generated according to a first input clock of a sending side, the clock signal at least carries a first frequency control word, the first frequency control word is used for indicating the relation between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock of the sending side according to the preset rule;

s204, determining a first input clock and a first frequency control word according to the clock signal;

s206, determining a second input clock according to the first input clock and the first frequency control word.

It should be noted that other optional embodiments and technical implementations of the clock receiving method in the embodiment of the present invention correspond to the clock receiving apparatus in the embodiment of the present invention, and are not described herein again.

In an alternative embodiment, the step S206 of determining the second input clock according to the first input clock and the first frequency control word includes:

a second sampling clock is determined based on the plurality of first phase addresses, and a second input clock is determined based on the second sampling clock.

In an optional embodiment, the obtaining the first sampling clock according to the first input clock and determining the plurality of first phase addresses according to the first sampling clock and the first frequency control word includes:

accumulating the first frequency control word according to the clock edge of the first sampling clock, and obtaining a plurality of first phase addresses according to each accumulation result of the first frequency control word;

determining a second sampling clock based on the plurality of first phase addresses, comprising:

obtaining a waveform of a second sampling clock according to the mapping relation between the plurality of first phase addresses and a preset value; the mapping relation is used for indicating the mapping relation between the first phase address and the waveform parameter preset by the second sampling clock;

and determining the clock frequency of the second sampling clock according to the waveform of the second sampling clock.

In an optional embodiment, the waveform parameter is used to indicate a parameter of a periodic waveform, wherein the waveform parameter includes at least one of: square wave output level value, sine wave output level value, triangular wave output level value, sawtooth wave output level value, and pulse output level value.

In an optional embodiment, in a case that the waveform parameter is a square wave output level value, obtaining a waveform of the second sampling clock according to a mapping relationship between a plurality of first phase addresses and a preset, includes:

and judging the plurality of first phase addresses according to the mapping relation, and obtaining the waveform of the second sampling clock according to the judgment result.

In an optional embodiment, when the waveform parameter is a sine wave output level value, obtaining a waveform of the second sampling clock according to a mapping relationship between a plurality of first phase addresses and a preset, includes:

obtaining a plurality of sine wave output level values corresponding to the first phase addresses respectively according to the first phase addresses and the mapping relation;

the plurality of sine wave output level values are subjected to digital-to-analog conversion to obtain a waveform of the second sampling clock.

In an optional embodiment, the clock signal further carries a second frequency control word, where the second frequency control word is used to indicate a relationship between the first sampling clock and a third sampling clock, and the third sampling clock is determined by a third input clock at a transmitting side according to a preset rule;

in the foregoing situation, the clock receiving method in the embodiment of the present invention further includes:

determining a second frequency control word according to the clock signal;

and determining a third input clock according to the first input clock and the second frequency control word.

Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.

In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.

It will be apparent to those skilled in the art that the various modules or steps of the invention described above may be implemented using a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and they may be implemented using program code executable by the computing devices, such that they may be stored in a memory device and executed by the computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into various integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

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