阅读说明：本技术 一种低功耗宽电压范围振荡器 (Low-power-consumption wide-voltage-range oscillator ) 是由 王梓淇 雷晓 黄少卿 肖培磊 王映杰 于 2021-09-30 设计创作，主要内容包括：本发明公开一种低功耗宽电压范围振荡器,属于模拟电路领域,包括积分电路、缓冲电路和锁存电路。所述积分电路对电流进行积分,使内部的电容进行充放电,产生交替上升或下降的斜坡电压；所述缓冲电路对积分电路产生的斜坡电压进行整形；所述锁存电路将状态锁存,输出时钟频率CLK和CLKN,所述锁存电路将时钟频率CLKN输入至所述积分电路,并重置所述积分电路中的积分电容。本发明的低功耗宽电压范围振荡器结构极简,所占芯片面积小,静态电流低以实现低功耗,当本结构的偏置稳定工作后,即产生时钟频率,工作电压范围广。(The invention discloses a low-power consumption wide-voltage-range oscillator, which belongs to the field of analog circuits and comprises an integrating circuit, a buffer circuit and a latch circuit. The integrating circuit integrates the current to charge and discharge an internal capacitor to generate alternately rising or falling ramp voltage; the buffer circuit shapes the ramp voltage generated by the integrating circuit; the latch circuit latches the state, outputs clock frequencies CLK and CLKN, inputs the clock frequency CLKN to the integration circuit, and resets an integration capacitor in the integration circuit. The oscillator with low power consumption and wide voltage range has the advantages of simple structure, small occupied chip area and low quiescent current to realize low power consumption, and when the bias of the oscillator works stably, the clock frequency is generated, and the working voltage range is wide.)

1. A low power wide voltage range oscillator, comprising:

an integration circuit for integrating the current to charge and discharge the internal capacitor and generate a ramp voltage which alternately rises and falls;

a buffer circuit for shaping the ramp voltage generated by the integrating circuit;

and the latch circuit latches the state and outputs clock frequencies CLK and CLKN, and the latch circuit inputs the clock frequency CLKN to the integrating circuit and resets an integrating capacitor in the integrating circuit.

2. The low-power consumption wide voltage range oscillator of claim 1, wherein the integration circuit comprises PMOS transistors PM 11-PM 14, NMOS transistors NM 11-NM 13, integration capacitors C11, C12, and a bias current source IREF;

the PMOS tube PM11, the PMOS tube PM12 and the PMOS tube PM14 are current mirror tubes, and the PMOS tube PM13 and the NMOS tube NM13 are switching tubes; the sources of the PMOS tubes PM11, PM12, PM13 and PM14 are all connected with a power voltage VCC, the sources of the NMOS tubes NM11, NM12 and NM13 are all connected with a ground potential GND, the upper plate of the integrating capacitor C11 is connected with the power voltage VCC, and the lower plate of the integrating capacitor C12 is connected with the ground potential GND;

the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM11, and the gate electrode and the drain electrode of the PMOS tube PM11 are both connected with the gate electrode of the PMOS tube PM12 and the gate electrode of the PM 14; the drain of the PM12 is connected with the drain and the gate of the NM11, the gate of the NMOS tube NM11 is connected with the gate of the NM12, the drain of the NMOS tube NM12 is connected with the drain of the switch tube PM13 and the upper plate of the integrating capacitor C12, the gate of the PM13 is connected with the gate of the switch tube NM13, and the drain of the NM13 is connected with the drain of the PM14 and the lower plate of the integrating capacitor C11; the gates of the switching transistor PM13 and the switching transistor NM13 are connected to the clock frequency CLKN at the same time.

3. The low-power consumption wide voltage range oscillator of claim 2, wherein the buffer circuit comprises a first buffer logic and a second buffer logic, wherein the input end of the first buffer logic is connected with the drain electrode of the PMOS transistor PM14 and the lower plate of the integrating capacitor C11; the input end of the second buffer logic is connected with the drain of the NMOS tube NM12 and the upper plate of the integrating capacitor C12.

4. The low-power-consumption wide-voltage-range oscillator of claim 1, wherein the integration circuit comprises PMOS transistors PM 21-PM 24, NMOS transistors NM 21-NM 23, and an integration capacitor C_PM、C_NMAnd a bias current source IREF;

the PMOS tube PM21, the PMOS tube PM22 and the PMOS tube PM24 are current mirror tubes, and the PMOS tube PM23 and the NMOS tube NM23 are switching tubes; the sources of the PMOS tubes PM21, PM22, PM23 and PM24 are all connected with a power voltage VCC, the sources of the NMOS tubes NM21, NM22 and NM23 are all grounded at the ground potential GND, and the integrating capacitor C_PMIs connected with a power supply voltage VCC and an integrating capacitor C_NMThe source and drain ground potential GND;

the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM21, and the gate electrode and the drain electrode of the PMOS tube PM21 are both connected with the gate electrode of the PMOS tube PM22 and the gate electrode of the PM 24; the drain of the PM22 is connected with the drain and the gate of the NM21, the gate of the NMOS transistor NM21 is connected with the gate of the NM22, and the drain of the NMOS transistor NM22 is connected with the drain of the switching transistor PM23 and the integrating capacitor C_NMThe gate of the PM23 is connected with the gate of the switching tube NM23, the drain of the NM23 is connected with the drain of the PM24 and the integrating capacitor C_PMA gate electrode of (1); the gates of the switching transistor PM23 and the switching transistor NM23 are connected to the clock frequency CLKN at the same time.

5. The low-power-consumption wide-voltage-range oscillator according to claim 4, wherein the buffer circuit comprises a first buffer logic and a second buffer logic, wherein an input end of the first buffer logic is connected with a drain electrode of the PMOS transistor PM24 and the integrating capacitor C_PMA gate electrode of (1); the input end of the second buffer logic is connected with the drain electrode of the NMOS tube NM22 and the integrating capacitor C_NMA gate electrode of (1).

6. The low power consumption wide voltage range oscillator of claim 3 or 5, wherein the first buffer logic and the second buffer logic are two identical buffer elements, and are any one of an inverter, a buffer, a Schmitt trigger, or a comparator.

7. The low power wide voltage range oscillator of claim 6, wherein said latch circuit comprises a latch having a first input coupled to an output of said first buffer logic and a second input coupled to an output of said second buffer logic; a first output terminal of the latch outputs the clock frequency CLK and a second output terminal outputs the clock frequency CLKN.

8. The low power wide voltage range oscillator of claim 1, further comprising a bias circuit for generating a zero temperature drift bias current;

the bias circuit comprises resistors R31 and R32, PMOS tubes PM31 and PM32, and NMOS tubes NM31 and NM 32; a first end of the resistor R31 is connected with a power supply voltage VCC, a second end of the resistor R32 is connected with a first end of the resistor R32, and a second end of the resistor R32 is connected with a source electrode of the PMOS transistor PM 31; the gate of the PMOS transistor PM31 is connected with the gate and the drain of the PM32, the source of the PM32 is connected with a power supply voltage VCC, the drain of the PM32 is connected with the drain of the NM32, the source of the NM32 is connected with the ground potential GND, the gate of the NM32 is connected with the gate and the drain of the NM31, the source of the NM31 is connected with the ground potential GND, and the drain of the NM31 is connected with the drain of the PM 31.

9. The low-power-consumption wide-voltage-range oscillator of claim 8, wherein the integration circuit comprises PMOS transistors MP 3-MP 6, NMOS transistors MN 3-MN 6, an integration capacitor C31 and a integration capacitor C32; the sources of the PMOS tubes PM 33-PM 36 are connected with a power supply voltage VCC, the sources of the NMOS tubes NM 33-NM 36 are connected with a ground potential GND, the upper plate of the integrating capacitor C31 is connected with the power supply voltage VCC, and the lower plate of the integrating capacitor C32 is connected with the ground potential GND; the gate of the NMOS transistor NM33 is connected with the gate of NM31, the drain of NM33 is connected with the drain of PM33, the gate and the drain of PM33 are connected with the gate of PM34 and the gate of PM35, the drain of PM34 is connected with the drain and the gate of NM34, the gate of NM34 is connected with the gate of NM35, the drain of NM35 is connected with the drain of PM36 and the upper plate of the integrating capacitor C32, the gate of PM36 is connected with the gate of NM36, and the drain of NM36 is connected with the drain of PM35 and the lower plate of the integrating capacitor C31.

10. The low power wide voltage range oscillator of claim 9, wherein the buffer circuit comprises buffers B1, B2, the latch circuit comprises inverters I1, I2, I3, a three-input nand gate N1, N2; the input end of the buffer B1 is connected with the lower plate of the integrating capacitor C31, and the output end of the buffer B1 is connected with the input end of the inverter I1; the input end of the buffer B2 is connected with the upper plate of the integrating capacitor C32, and the output end is connected with the third input end of the three-input NAND gate N1;

the output end of the inverter I1 is connected with the first input end of the three-input NAND gate N1, and an enable signalThe output end of the inverter I2 is connected with the second input end of the three-input NAND gate N1 and the second input end of the N2, the output end of the three-input NAND gate N1 is connected with the first input end of the three-input NAND gate N2, the output end of the three-input NAND gate N2 is connected with the third input end of the three-input NAND gate N1 and the input end of the inverter I3, the output end of the inverter I3 is connected with the gates of the PM36 and the NM36 in the integrating circuit, and the output end of the three-input NAND gate N2 outputs the clock frequency CLK.

Technical Field

The invention relates to the technical field of analog circuits, in particular to a low-power-consumption wide-voltage-range oscillator.

Background

In general, a relaxation oscillator generates the clock frequency CLK by current charging and discharging integration of a circuit. The current delay monitoring circuit, the timing circuit and the conversion circuit all need an oscillator integrated inside a chip for generating a clock frequency CLK for timing. For a circuit with low area, low power consumption and low cost, if a complex oscillator is added, the power consumption is greatly increased; if a high-precision oscillator with trimming logic is added, the area cost cannot be controlled.

Disclosure of Invention

The present invention is directed to a low power consumption oscillator with a wide voltage range to solve the problems of the related art.

To solve the above technical problem, the present invention provides a low power consumption wide voltage range oscillator, comprising:

an integration circuit for integrating the current to charge and discharge the internal capacitor and generate a ramp voltage which alternately rises and falls;

a buffer circuit for shaping the ramp voltage generated by the integrating circuit;

and the latch circuit latches the state and outputs clock frequencies CLK and CLKN, and the latch circuit inputs the clock frequency CLKN to the integrating circuit and resets an integrating capacitor in the integrating circuit.

Optionally, the integration circuit includes PMOS transistors PM11 to PM14, NMOS transistors NM11 to NM13, integration capacitors C11, C12, and a bias current source IREF;

the PMOS tube PM11, the PMOS tube PM12 and the PMOS tube PM14 are current mirror tubes, and the PMOS tube PM13 and the NMOS tube NM13 are switching tubes; the sources of the PMOS tubes PM11, PM12, PM13 and PM14 are all connected with a power voltage VCC, the sources of the NMOS tubes NM11, NM12 and NM13 are all connected with a ground potential GND, the upper plate of the integrating capacitor C11 is connected with the power voltage VCC, and the lower plate of the integrating capacitor C12 is connected with the ground potential GND;

the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM11, and the gate electrode and the drain electrode of the PMOS tube PM11 are both connected with the gate electrode of the PMOS tube PM12 and the gate electrode of the PM 14; the drain of the PM12 is connected with the drain and the gate of the NM11, the gate of the NMOS tube NM11 is connected with the gate of the NM12, the drain of the NMOS tube NM12 is connected with the drain of the switch tube PM13 and the upper plate of the integrating capacitor C12, the gate of the PM13 is connected with the gate of the switch tube NM13, and the drain of the NM13 is connected with the drain of the PM14 and the lower plate of the integrating capacitor C11; the gates of the switching transistor PM13 and the switching transistor NM13 are connected to the clock frequency CLKN at the same time.

Optionally, the buffer circuit includes a first buffer logic and a second buffer logic, and an input end of the first buffer logic is connected to the drain of the PMOS transistor PM14 and the lower plate of the integrating capacitor C11; the input end of the second buffer logic is connected with the drain of the NMOS tube NM12 and the upper plate of the integrating capacitor C12.

Optionally, the integration circuit includes PMOS transistors PM21 to PM24, NMOS transistors NM21 to NM23, and an integration capacitor C_PM、C_NMAnd a bias current source IREF;

the PMOS tube PM21, the PMOS tube PM22 and the PMOS tube PM24 are current mirror tubes, and the PMOS tube PM23 and the NMOS tube NM23 are switching tubes; the sources of the PMOS tubes PM21, PM22, PM23 and PM24 are all connected with a power voltage VCC, the sources of the NMOS tubes NM21, NM22 and NM23 are all grounded at the ground potential GND, and the integrating capacitor C_PMIs connected with a power supply voltage VCC and an integrating capacitor C_NMThe source and drain ground potential GND;

the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM21, and the gate electrode and the drain electrode of the PMOS tube PM21 are both connected with the gate electrode of the PMOS tube PM22 and the gate electrode of the PM 24; the drain of the PM22 is connected with the drain and the gate of the NM21, the gate of the NMOS transistor NM21 is connected with the gate of the NM22, and the drain of the NMOS transistor NM22 is connected with the drain of the switching transistor PM23 and the integrating capacitor C_NMThe gate of the PM23 is connected with the gate of the switching tube NM23, the drain of the NM23 is connected with the drain of the PM24 and the integrating capacitor C_PMA gate electrode of (1); the gates of the switching transistor PM23 and the switching transistor NM23 are connected to the clock frequency CLKN at the same time.

Optionally, the buffer circuit includes a first buffer logic and a second buffer logic, and an input end of the first buffer logic is connected to the drain of the PMOS transistor PM24 and the integrating capacitor C_PMA gate electrode of (1); the input end of the second buffer logic is connected with the drain electrode of the NMOS tube NM22 and the integrating capacitor C_NMA gate electrode of (1).

Optionally, the first buffer logic and the second buffer logic are two identical buffer elements, and are any one of an inverter, a buffer, a schmitt trigger, or a comparator.

Optionally, the latch circuit includes a latch, a first input terminal of the latch is connected to the output terminal of the first buffer logic, and a second input terminal of the latch is connected to the output terminal of the second buffer logic; a first output terminal of the latch outputs the clock frequency CLK and a second output terminal outputs the clock frequency CLKN.

Optionally, the low-power-consumption wide-voltage-range oscillator further includes a bias circuit for generating a zero-temperature-drift bias current;

the bias circuit comprises resistors R31 and R32, PMOS tubes PM31 and PM32, and NMOS tubes NM31 and NM 32; a first end of the resistor R31 is connected with a power supply voltage VCC, a second end of the resistor R32 is connected with a first end of the resistor R32, and a second end of the resistor R32 is connected with a source electrode of the PMOS transistor PM 31; the gate of the PMOS transistor PM31 is connected with the gate and the drain of the PM32, the source of the PM32 is connected with a power supply voltage VCC, the drain of the PM32 is connected with the drain of the NM32, the source of the NM32 is connected with the ground potential GND, the gate of the NM32 is connected with the gate and the drain of the NM31, the source of the NM31 is connected with the ground potential GND, and the drain of the NM31 is connected with the drain of the PM 31.

Optionally, the integration circuit includes PMOS transistors MP 3-MP 6, NMOS transistors MN 3-MN 6, and integrating capacitors C31 and C32; the sources of the PMOS tubes PM 33-PM 36 are connected with a power supply voltage VCC, the sources of the NMOS tubes NM 33-NM 36 are connected with a ground potential GND, the upper plate of the integrating capacitor C31 is connected with the power supply voltage VCC, and the lower plate of the integrating capacitor C32 is connected with the ground potential GND; the gate of the NMOS transistor NM33 is connected with the gate of NM31, the drain of NM33 is connected with the drain of PM33, the gate and the drain of PM33 are connected with the gate of PM34 and the gate of PM35, the drain of PM34 is connected with the drain and the gate of NM34, the gate of NM34 is connected with the gate of NM35, the drain of NM35 is connected with the drain of PM36 and the upper plate of the integrating capacitor C32, the gate of PM36 is connected with the gate of NM36, and the drain of NM36 is connected with the drain of PM35 and the lower plate of the integrating capacitor C31.

Optionally, the buffer circuit includes buffers B1, B2, and the latch circuit includes inverters I1, I2, I3, and three-input nand gates N1, N2; the input end of the buffer B1 is connected with the lower plate of the integrating capacitor C31, and the output end of the buffer B1 is connected with the input end of the inverter I1; the input end of the buffer B2 is connected with the upper plate of the integrating capacitor C32, and the output end is connected with the third input end of the three-input NAND gate N1;

the output end of the inverter I1 is connected with the first input end of the three-input NAND gate N1, and an enable signalThe output end of the inverter I2 is connected with the second input end of the three-input NAND gate N1 and the second input end of the N2, the output end of the three-input NAND gate N1 is connected with the first input end of the three-input NAND gate N2, the output end of the three-input NAND gate N2 is connected with the third input end of the three-input NAND gate N1 and the input end of the inverter I3, the output end of the inverter I3 is connected with the gates of the PM36 and the NM36 in the integrating circuit, and the output end of the three-input NAND gate N2 outputs the clock frequency CLK.

The oscillator with low power consumption and wide voltage range provided by the invention has the following advantages:

(1) the circuit structure is extremely simple, MOS tubes and capacitors are less in use and easy to match, the area of a chip is reduced, and the types of the capacitors, the buffer structure and the latch are various and selectable so as to realize special functions such as enabling, clearing and the like;

(2) the circuit can work when having very small current, and can effectively reduce static power consumption;

(3) the range of working voltage is wide, and the integrated circuit is only influenced by the integrated circuit, and the two PMOS and NMOS which are longitudinally connected in the integrated circuit are saturated, so that the integrated circuit can normally work.

Drawings

FIG. 1 is a schematic diagram of a low power consumption wide voltage range oscillator according to the present invention;

FIG. 2 is a schematic diagram of a low power consumption wide voltage range oscillator circuit according to the present invention;

FIG. 3 is a schematic diagram of a low power consumption wide voltage range oscillator voltage waveform provided by the present invention;

FIG. 4 is a schematic circuit diagram of a second embodiment of a low power consumption wide voltage range oscillator according to the present invention;

fig. 5 is a schematic diagram of a three-circuit structure of an embodiment of the low-power wide-voltage-range oscillator provided by the present invention.

Detailed Description

The invention provides a low power consumption wide voltage range oscillator, which is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a low-power consumption wide-voltage range oscillator, the structure of which is shown in fig. 1, comprising an integrating circuit 110, a buffer circuit 120 and a latch circuit 130; the integrating circuit 110 proportionally mirrors the bias current, and charges and discharges the integrating capacitor by controlling the on-off of the light tube in the integrating circuit to generate the ramp voltage V which alternately rises or falls_C1And V_C2(ii) a The buffer circuit 120 shapes the ramp voltage signal generated by the integrating circuit 110, and the shaped ramp voltage signal is transmitted to the post-stage latch circuit 130, wherein the buffer circuit 120 can specifically suppress the leakage of the switch of the logic gate during the middle rail voltage, so that the buffer circuit 120 has high selectivity, and comprises logics such as an inverter, a buffer, a schmitt trigger and a comparator; after the state of the input signal of the latch circuit 130 is inverted, the latch circuit starts to work, latches the state and outputs clock frequency CLK and CLKN, the clock frequency CLKN is fed back to the integration circuit 110 to control the grid voltage of the light-emitting tube therein, and the integration capacitor is charged and discharged to generate ramp voltage, so that a complete loop is formed; the voltage shaping and output waveforms are shown in fig. 2.

As shown in fig. 3, the integration circuit includes PMOS transistors PM11 to PM14, NMOS transistors NM11 to NM13, integration capacitors C11, C12, and a bias current source IREF; the PMOS tube PM11, the PMOS tube PM12 and the PMOS tube PM14 are current mirror tubes, and the PMOS tube PM13 and the NMOS tube NM13 are switching tubes; the sources of the PMOS tubes PM11, PM12, PM13 and PM14 are all connected with a power voltage VCC, the sources of the NMOS tubes NM11, NM12 and NM13 are all connected with a ground potential GND, the upper plate of the integrating capacitor C11 is connected with the power voltage VCC, and the lower plate of the integrating capacitor C12 is connected with the ground potential GND; the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM11, and the gate electrode and the drain electrode of the PMOS tube PM11 are both connected with the gate electrode of the PMOS tube PM12 and the gate electrode of the PM 14; the drain of the PM12 is connected with the drain and the gate of the NM11, the gate of the NMOS tube NM11 is connected with the gate of the NM12, the drain of the NMOS tube NM12 is connected with the drain of the switch tube PM13 and the upper plate of the integrating capacitor C12, the gate of the PM13 is connected with the gate of the switch tube NM13, and the drain of the NM13 is connected with the drain of the PM14 and the lower plate of the integrating capacitor C11; the gates of the switching tube PM13 and the switching tube NM13 are simultaneously connected with a clock frequency CLKN, and the clock frequency CLKN alternately switches the MOS tubes PM13 and NM13 to realize charging and discharging of the integrating capacitor.

The buffer circuit comprises a first buffer logic and a second buffer logic, wherein the input end of the first buffer logic is connected with the drain electrode of the PMOS pipe PM14 and the lower plate of the integrating capacitor C11; the input end of the second buffer logic is connected with the drain of the NMOS tube NM12 and the upper plate of the integrating capacitor C12. The first buffer logic and the second buffer logic are two identical buffer elements, and are any one of an inverter, a buffer, a Schmitt trigger or a comparator.

The latch circuit comprises a latch, wherein a first input end of the latch is connected with an output end of the first buffer logic, and a second input end of the latch is connected with an output end of the second buffer logic; a first output terminal of the latch outputs the clock frequency CLK and a second output terminal outputs the clock frequency CLKN.

The bias current IREF is subjected to n-time equal proportion adjustment, the integral capacitor is charged and discharged after the mirror image, and the generated clock frequency

Of the above formula, clock frequency f_CLKReceiving power supply voltage VCC, bias current IREF and circuit delay time T_delayOptional zero temperature drift bias current IREF reduces temperature effects. Delay time T_delayThe influence of temperature is large, but in the circuit with medium and low precision requirement, the influence of the temperature on the clock frequency is acceptable.

Example two

The second embodiment of the invention also provides another low-power consumptionThe wide voltage range oscillator, as shown in FIG. 4, is different from the first embodiment in that the integrating circuit includes PMOS transistors PM 21-PM 24, NMOS transistors NM 21-NM 23, and an integrating capacitor C_PM、C_NMAnd a bias current source IREF; the PMOS tube PM21, the PMOS tube PM22 and the PMOS tube PM24 are current mirror tubes, and the PMOS tube PM23 and the NMOS tube NM23 are switching tubes; the sources of the PMOS tubes PM21, PM22, PM23 and PM24 are all connected with a power voltage VCC, the sources of the NMOS tubes NM21, NM22 and NM23 are all grounded at the ground potential GND, and the integrating capacitor C_PMIs connected with a power supply voltage VCC and an integrating capacitor C_NMThe source and drain ground potential GND; the input end of the bias current source IREF is connected with the drain electrode of the PMOS tube PM21, and the gate electrode and the drain electrode of the PMOS tube PM21 are both connected with the gate electrode of the PMOS tube PM22 and the gate electrode of the PM 24; the drain of the PM22 is connected with the drain and the gate of the NM21, the gate of the NMOS transistor NM21 is connected with the gate of the NM22, and the drain of the NMOS transistor NM22 is connected with the drain of the switching transistor PM23 and the integrating capacitor C_NMThe gate of the PM23 is connected with the gate of the switching tube NM23, the drain of the NM23 is connected with the drain of the PM24 and the integrating capacitor C_PMA gate electrode of (1); the gates of the switching transistor PM23 and the switching transistor NM23 are connected to the clock frequency CLKN at the same time. The integration circuit 210 couples the integration capacitors C respectively composed of PMOS and NMOS according to the proportional mirror bias current IREF_PMAnd C_NMCharging and discharging to generate a ramp voltage V_C1And V_C2The ramp voltage is shaped by the buffer circuit 220 to drive the latch 230 to generate the clock frequencies CLK and CLKN. The clock frequency CLKN is fed back to the integration circuit 210 to control the gate voltages of the switching transistors PM3, NM3 to the capacitor C_PMAnd C_NMCharging and discharging are carried out to generate a slope voltage, and a complete loop is formed.

The buffer circuit comprises a first buffer logic and a second buffer logic, wherein the input end of the first buffer logic is connected with the drain electrode of the PMOS pipe PM24 and the integrating capacitor C_PMA gate electrode of (1); the input end of the second buffer logic is connected with the drain electrode of the NMOS tube NM22 and the integrating capacitor C_NMA gate electrode of (1). The first buffer logic and the second buffer logic are two identical buffer elements, and are any one of an inverter, a buffer, a Schmitt trigger or a comparator.

EXAMPLE III

The present invention further provides a third low-power consumption wide voltage range oscillator, which has a structure as shown in fig. 5, and includes a bias circuit 310, an integrating circuit 320, a buffer circuit 330, and a latch circuit 340. The bias circuit 310 adopts a positive temperature drift resistor and a negative temperature drift resistor which are superposed to form a zero temperature drift resistor, generates a zero temperature drift bias current, and improves the clock frequency precision, and comprises resistors R31 and R32, PMOS tubes PM31 and PM32, and NMOS tubes NM31 and NM 32; a first end of the resistor R31 is connected with a power supply voltage VCC, a second end of the resistor R32 is connected with a first end of the resistor R32, and a second end of the resistor R32 is connected with a source electrode of the PMOS transistor PM 31; the gate of the PMOS transistor PM31 is connected with the gate and the drain of the PM32, the source of the PM32 is connected with a power supply voltage VCC, the drain of the PM32 is connected with the drain of the NM32, the source of the NM32 is connected with the ground potential GND, the gate of the NM32 is connected with the gate and the drain of the NM31, the source of the NM31 is connected with the ground potential GND, and the drain of the NM31 is connected with the drain of the PM 31. The bias current is represented as:

wherein, K is a PMOS pipe PM 31: multiples of PM 32;is the width-to-length ratio of the PMOS transistors PM31 and PM 32.

The integrating circuit 320 proportionally mirrors bias current to generate a ramp voltage to drive the buffer circuit 330 to finish output shaping, and the integrating circuit 320 comprises PMOS tubes MP 3-MP 6, NMOS tubes MN 3-MN 6, an integrating capacitor C31 and an integrating capacitor C32; the sources of the PMOS tubes PM 33-PM 36 are connected with a power supply voltage VCC, the sources of the NMOS tubes NM 33-NM 36 are connected with a ground potential GND, the upper plate of the integrating capacitor C31 is connected with the power supply voltage VCC, and the lower plate of the integrating capacitor C32 is connected with the ground potential GND; the gate of the NMOS transistor NM33 is connected with the gate of NM31, the drain of NM33 is connected with the drain of PM33, the gate and the drain of PM33 are connected with the gate of PM34 and the gate of PM35, the drain of PM34 is connected with the drain and the gate of NM34, the gate of NM34 is connected with the gate of NM35, the drain of NM35 is connected with the drain of PM36 and the upper plate of the integrating capacitor C32, the gate of PM36 is connected with the gate of NM36, and the drain of NM36 is connected with the drain of PM35 and the lower plate of the integrating capacitor C31.

The buffer circuit 330 comprises buffers B1 and B2, wherein the buffers B1 and B2 adopt large-size and inverse ratio structures to shape a ramp voltage and inhibit the switching leakage current of a device; the latch circuit 340 comprises inverters I1, I2, I3, a three-input NAND gate N1, N2; the input end of the buffer B1 is connected with the lower plate of the integrating capacitor C31, and the output end of the buffer B1 is connected with the input end of the inverter I1; the input end of the buffer B2 is connected with the upper plate of the integrating capacitor C32, and the output end is connected with the third input end of the three-input NAND gate N1; the output end of the inverter I1 is connected with the first input end of the three-input NAND gate N1, and an enable signalThe output end of the inverter I2 is connected with the second input end of the three-input NAND gate N1 and the second input end of the N2, the output end of the three-input NAND gate N1 is connected with the first input end of the three-input NAND gate N2, the output end of the three-input NAND gate N2 is connected with the third input end of the three-input NAND gate N1 and the input end of the inverter I3, the output end of the inverter I3 is connected with the gates of the PM36 and the NM36 in the integrating circuit, and the output end of the three-input NAND gate N2 outputs the clock frequency CLK.

The bias circuit generates a zero-temperature drift bias current and provides a high-precision charging current, the current is used for integrating the capacitance time tau, and the clock frequency CLK is expressed as:

wherein the time constant τ is expressed as:

wherein n is the current mirror multiple, and the charging current is nI_REF。

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.