阅读说明：本技术 基于双栅的具有p型沟道特性的新型半导体器件 (Novel semiconductor device with P-type channel characteristic based on double gates ) 是由 李琦 王磊 陈永和 姜焱彬 黄晓咪 杨保争 曾鹏 何智超 张锋 于 2021-09-02 设计创作，主要内容包括：本发明公开一种基于双栅的具有P型沟道特性的新型半导体器件,在传统AlGaN/GaN HEMT器件中引入底部栅极,通过背栅与顶栅控制沟道,实现具有P沟道特性的HEMT器件。一方面,通过顶部栅极偏置电压,使得器件处于关断状态。降低底部栅极偏置电压,削弱顶部栅所产生的电场,使得沟道二维电子气重新产生,实现P型沟道器件特性。另一方面,在开态下,进一步减小底部栅极偏置电压,异质结界面三角形势阱的深度增加,从而增大器件的开态电流。本发明实现的是一种基于双栅的具有P型沟道特性的新型半导体器件,避免了传统HEMT器件的无法实现二维空穴气,P型沟道的HEMT器件难以制造的难题,为实现具有P型沟道特性的HEMT器件提供新的思路。(The invention discloses a novel semiconductor device with a P-type channel characteristic based on a double gate. In one aspect, the device is placed in an off state by a top gate bias voltage. The bias voltage of the bottom grid electrode is reduced, the electric field generated by the top grid electrode is weakened, the two-dimensional electron gas of the channel is regenerated, and the characteristic of the P-type channel device is realized. On the other hand, in the on state, the bottom gate bias voltage is further reduced, and the depth of the heterojunction interface triangular potential well is increased, so that the on-state current of the device is increased. The invention realizes a novel semiconductor device with a P-type channel characteristic based on a double gate, avoids the difficult problems that the traditional HEMT device cannot realize two-dimensional hole gas and the HEMT device with the P-type channel is difficult to manufacture, and provides a new idea for realizing the HEMT device with the P-type channel characteristic.)

1. The novel semiconductor device with the P-type channel characteristic based on the double gates comprises a substrate layer (1), a buffer layer (2), a channel layer (5), a barrier layer (6), a passivation layer (7), a source electrode (8), a drain electrode (9) and a top grid electrode (10); the substrate layer (1), the buffer layer (2), the channel layer (5), the barrier layer (6) and the passivation layer (7) are sequentially superposed from bottom to top; the source electrode (8) and the drain electrode (9) are positioned at two ends above the buffer layer (2) or the channel layer (5), and the source electrode (8) and the drain electrode (9) are in ohmic contact; the top grid (10) is positioned on the passivation layer (7) and is positioned between the source electrode (8) and the drain electrode (9); the novel semiconductor device is characterized by further comprising a bottom grid (3) and a P-type doped region (4); the bottom grid (3) extends from the bottom of the substrate layer (1) to the middle lower part of the buffer layer (2); the P-type doped region (4) is positioned on the buffer layer (2) and wraps the outer side of the bottom grid (3); the bottom grid (3) and the P-type doped region (4) are simultaneously positioned right below the top grid (10).

2. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 1, characterized by the fact that the bottom gate (3) and the P-doped region (4) are schottky contacts.

3. New semiconductor device with P-type channel characteristics based on dual gate as claimed in claim 1, characterized by the fact that the top gate (10) and the bottom gate (3) control the same channel.

4. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 1, characterized by the fact that the symmetry centerlines of the top gate (10) and the bottom gate (3) coincide.

5. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 1, characterized by the fact that the top gate (10) and the bottom gate (3) have the same width.

6. The novel semiconductor device with the P-type channel characteristic based on the double gates comprises a substrate layer (1), a buffer layer (2), a channel layer (5), a barrier layer (6), a passivation layer (7), a source electrode (8), a drain electrode (9) and a top grid electrode (10); the substrate layer (1), the buffer layer (2), the channel layer (5), the barrier layer (6) and the passivation layer (7) are sequentially superposed from bottom to top; the source electrode (8) and the drain electrode (9) are positioned at two ends above the buffer layer (2) or the channel layer (5), and the source electrode (8) and the drain electrode (9) are in ohmic contact; the top grid (10) is positioned on the passivation layer (7) and is positioned between the source electrode (8) and the drain electrode (9); the novel semiconductor device is characterized by further comprising a bottom grid (3) and a P-type doped region (4); the bottom grid (3) is positioned on the substrate layer (1), the P-type doped region (4) is positioned at the middle lower part of the buffer layer (2), and the top of the bottom grid (3) is attached to the bottom of the P-type doped region (4); the bottom grid (3) and the P-type doped region (4) are simultaneously positioned right below the top grid (10).

7. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 6, characterized by the fact that the bottom gate (3) and the P-doped region (4) are schottky contacts.

8. Novel semiconductor device with P-type channel characteristics based on dual gate as claimed in claim 6, characterized by the fact that the top gate (10) and the bottom gate (3) control the same channel.

9. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 6, characterized by the fact that the symmetry centerlines of the top gate (10) and the bottom gate (3) coincide.

10. Novel semiconductor device with P-channel characteristics based on dual gate as claimed in claim 6, characterized by the fact that the top gate (10) and the bottom gate (3) have the same width.

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a novel semiconductor device with a P-type channel characteristic based on a double gate.

Background

The power semiconductor device has extremely wide application in the fields of power electronics, microwave communication and the like, and in recent decades, the silicon-based device is always a hot spot of application and research as a mainstream power semiconductor device, and has also obtained very rapid development and important achievement. However, with the rapid development of human society and scientific technology, the existing silicon-based power semiconductor devices have difficulty meeting the performance requirements of some specific fields on the devices.

Under the condition that a silicon-based device gradually approaches the theoretical limit, the GaN material with the advantages of wide forbidden band, high breakdown electric field, high temperature resistance, radiation resistance and the like has great potential market value. The P-channel GaN material structure is the basis of a GaN-based digital circuit, and for example, common P-channel metal-oxide-semiconductor (MOS) transistors and N-channel MOS transistors form a CMOS circuit. At present, with the progress of Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) technology in gallium nitride material application and the breakthrough of key thin film growth technology, various GaN heterostructures are successfully grown. For example, AlGaN/GaN heterojunction, can realize HEMT devices with very excellent performance due to the presence of a high density, high mobility two-dimensional electron gas. However, in the prior art, it is difficult to epitaxially grow a GaN-based heterogeneous material of a P-type channel, and a series of problems that the hole mobility of the conventional P-type device is low, the lattice damage is easily caused by acceptor impurity injection, the activation is difficult, and the like are not well solved yet, so that the development of a digital integrated circuit is seriously hindered, and the development of a GaN digital control device in the aspects of radio frequency and power integrated circuits is restricted.

Disclosure of Invention

The invention aims to solve the problems of high process difficulty, low hole mobility and difficult activation of acceptor impurities caused by difficult growth of GaN-based heterogeneous materials of the traditional P-channel device, provides a novel semiconductor device with P-type channel characteristics based on a double gate, and aims to realize the characteristics of the P-channel device without changing the excellent characteristics of a GaN HEMT device.

In order to solve the problems, the invention is realized by the following technical scheme:

a novel semiconductor device with P-type channel characteristics based on a double-gate comprises a substrate layer, a buffer layer, a channel layer, a barrier layer, a passivation layer, a source electrode, a drain electrode and a top grid electrode; the substrate layer, the buffer layer, the channel layer, the barrier layer and the passivation layer are sequentially superposed from bottom to top; the source electrode and the drain electrode are positioned at two ends above the buffer layer or the channel layer and are in ohmic contact; the top grid electrode is positioned on the passivation layer and is positioned between the source electrode and the drain electrode; the novel semiconductor device is characterized by further comprising a bottom grid and a P-type doped region; the bottom grid extends from the bottom of the substrate layer to the middle lower part of the buffer layer; the P-type doped region is positioned on the buffer layer and wraps the outer side of the bottom grid; the bottom gate and the P-type doped region are simultaneously located right below the top gate.

In the above scheme, the bottom gate and the P-type doped region are schottky contacts.

In the above scheme, the top gate and the bottom gate control the same channel.

In the above scheme, the symmetrical centerlines of the top gate and the bottom gate coincide.

In the above scheme, the widths of the top gate and the bottom gate are the same.

The novel semiconductor device comprises a substrate layer, a buffer layer, a channel layer, a barrier layer, a passivation layer, a source electrode, a drain electrode and a top grid electrode; the substrate layer, the buffer layer, the channel layer, the barrier layer and the passivation layer are sequentially superposed from bottom to top; the source electrode and the drain electrode are positioned at two ends above the buffer layer or the channel layer and are in ohmic contact; the top grid electrode is positioned on the passivation layer and is positioned between the source electrode and the drain electrode; the novel semiconductor device is characterized by further comprising a bottom grid and a P-type doped region; the bottom grid is positioned on the substrate layer, the P-type doped region is positioned at the middle lower part of the buffer layer, and the top of the bottom grid is attached to the bottom of the P-type doped region; the bottom gate and the P-type doped region are simultaneously located right below the top gate.

In the above scheme, the bottom gate and the P-type doped region are schottky contacts.

In the above scheme, the top gate and the bottom gate control the same channel.

In the above scheme, the symmetrical centerlines of the top gate and the bottom gate coincide.

In the above scheme, the widths of the top gate and the bottom gate are the same.

Compared with the prior art, the method avoids the problems of low hole mobility, difficult activation of acceptor impurities, high difficulty in the process of the GaN-based heterogeneous material and the like of the traditional P-channel device, introduces the bottom grid into the traditional AlGaN/GaN HEMT device based on two-dimensional electron gas conduction to form Schottky contact with the P-type doping region, better controls the same channel with the top grid, and realizes the HEMT device with the P-channel characteristic. In one aspect, the device is placed in an off state by a top gate bias voltage. The bias voltage of the bottom grid electrode is reduced, the electric field generated by the top grid electrode is weakened, the two-dimensional electron gas of the channel is regenerated, and the characteristic of the P-type channel device is realized. On the other hand, in the on state, the bottom gate bias voltage is further reduced, and the depth of the heterojunction interface triangular potential well is increased, so that the on-state current of the device is increased. The invention realizes a novel semiconductor device with a P-type channel characteristic based on a double gate, avoids the difficult problems that the traditional HEMT device cannot realize two-dimensional hole gas and the HEMT device with the P-type channel is difficult to manufacture, and provides a new idea for realizing the HEMT device with the P-type channel characteristic.

Drawings

Fig. 1 is a schematic structural diagram of a novel semiconductor device with P-type channel characteristics based on a dual gate.

Fig. 2 is a schematic structural diagram of another novel semiconductor device with P-type channel characteristics based on a double gate.

Fig. 3 is a schematic diagram of the change of electron concentration at the heterojunction of the device with the change of bottom gate voltage.

Fig. 4 is a graph of transfer characteristics.

Reference numbers in the figures: 1. a substrate layer; 2. a buffer layer; 3. a bottom gate; 4. a P-type doped region; 5. a channel layer; 6. a barrier layer; 7. a passivation layer; 8. a source electrode; 9. a drain electrode; 10. a top gate.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.

Example 1:

referring to fig. 1, a novel semiconductor device with P-type channel characteristics based on a double gate is a lateral device and comprises a substrate layer 1, a buffer layer 2, a channel layer 5, a barrier layer 6, a passivation layer 7, a source electrode 8, a drain electrode 9, a top gate 10, a bottom gate 3 and a P-type doped region 4.

The substrate layer 1, the buffer layer 2, the channel layer 5, the barrier layer 6 and the passivation layer 7 are sequentially stacked from bottom to top. The source electrode 8 and the drain electrode 9 are located at both ends above the buffer layer 2 or the channel layer 5, i.e., the source electrode 8 and the drain electrode 9 may be located at both ends of the channel layer 5, the barrier layer 6, and the passivation layer 7 above the buffer layer 2, or the source electrode 8 and the drain electrode 9 may be located at both ends of the barrier layer 6 and the passivation layer 7 above the channel layer 5. The source electrode 8 and the drain electrode 9 are ohmic contacts. The top gate 10 is located on the passivation layer 7 and between the source 8 and drain 9 electrodes. The novel semiconductor device is characterized by further comprising a bottom grid 3 which extends from the bottom of the substrate layer 1 to the middle lower part of the buffer layer 2. The P-type doped region 4 is located on the buffer layer 2 and covers the outer side of the bottom gate 3. The bottom gate 3 and the P-type doped region 4 form a schottky contact and are located right below the top gate 10, and the projection of the top gate 10 is onto the bottom gate 3, and the top gate 10 and the bottom gate 3 control the same channel. For better effect, in the preferred embodiment of the present invention, the symmetrical middle lines of the top gate 10 and the bottom gate 3 coincide, i.e. the two symmetrical middle lines are on the same longitudinal straight line, and the widths of the top gate 10 and the bottom gate 3 are the same.

Example 2:

referring to fig. 2, another novel semiconductor device with P-type channel characteristics based on a dual gate is a lateral device, and includes a substrate layer 1, a buffer layer 2, a channel layer 5, a barrier layer 6, a passivation layer 7, a source electrode 8, a drain electrode 9, a top gate 10, a bottom gate 3, and a P-type doped region 4. The source electrode 8 and the drain electrode 9 are located at both ends above the buffer layer 2 or the channel layer 5, i.e., the source electrode 8 and the drain electrode 9 may be located at both ends of the channel layer 5, the barrier layer 6, and the passivation layer 7 above the buffer layer 2, or the source electrode 8 and the drain electrode 9 may be located at both ends of the barrier layer 6 and the passivation layer 7 above the channel layer 5. The source electrode 8 and the drain electrode 9 are ohmic contacts. The top gate 10 is located on the passivation layer 7 and between the source 8 and drain 9 electrodes. The P-type doped region 4 is located at the middle lower portion of the buffer layer 2, and the top of the bottom gate 3 is attached to the bottom of the P-type doped region 4. The bottom gate 3 and the P-type doped region 4 are schottky contacts. The bottom gate 3 and the P-type doped region 4 are located right below the top gate 10, and the projection of the top gate 10 is onto the bottom gate 3, and the top gate 10 and the bottom gate 3 control the same channel. For better effect, in the preferred embodiment of the present invention, the symmetrical middle lines of the top gate 10 and the bottom gate 3 coincide, i.e. the two symmetrical middle lines are on the same longitudinal straight line, and the widths of the top gate 10 and the bottom gate 3 are the same.

One or a combination of more of GaN, AlN, AlGaN, InGaN and InAlN can be used as the materials of the substrate layer 1, the buffer layer 2, the channel layer 5 and the barrier layer 6; the passivation layer 7 may be made of SiN, which is a material commonly used in the art_xAlso, A1 can be used₂O₃Or AlN. According to the invention, the conventional AlGaN/GaN HEMT device is introduced into the bottom grid 3 through an etching process, and the P-type doped region 4 is introduced through epitaxial growth, so that the process flow compatible with the conventional GaN device is realized.

In the invention, the concentration of the P-type doped region 4 influences the control effect of the top gate 10 of the device on the channel, and the control effect is stronger when the concentration is higher. Fig. 3 is a diagram of the change of electron concentration at the AlGaN/GaN heterojunction interface when the bottom gate 3 of the device is connected to different low potentials, and it can be seen from the diagram that as the voltage of the bottom gate 3 is further reduced, the electron concentration of the channel at the heterojunction interface gradually rises, and the device is turned on again, because the top gate control channel is gradually weakened, which shows the P-channel device characteristic, and the transfer characteristic curve thereof is as shown in fig. 4, and it can be seen from the diagram that the device conduction current gradually increases as the bottom gate voltage is reduced.

The working principle of the invention is as follows: when the drain 9 of the device structure is connected with a negative voltage, zero voltage is applied to the top grid 10, the device is in a conducting state, and the movement direction of electrons points to the source 8 from the drain 9. At this time, if a negative bias voltage is applied to the top gate 10, an electric field pointing from the bottom gate to the top gate is generated, and under the combined action of the bias voltage and the P-doped buffer layer 2 region, the conduction band barrier at the AlGaN/GaN heterojunction interface is increased to be above the fermi level, so that the two-dimensional electron gas concentration at the channel is gradually reduced until the device is turned off. At this time, the bias voltage of the bottom gate 3 is reduced, the electric field generated by the bias of the top gate 10 is weakened, the conduction band barrier at the AlGaN/GaN heterojunction interface is reduced to be below the Fermi level along with the further reduction of the bias voltage of the bottom gate 3, the two-dimensional channel electron gas is generated again, the device can better control the device channel to complete the switching from off to on through the bottom gate 3 forming Schottky contact, as shown in FIG. 4, and therefore the P-channel device characteristic of electron conduction is realized through the combined action of the bottom gate 3 and the top gate 10 on the two-dimensional channel electron gas. In conclusion, compared with the prior art, the semiconductor device provided by the invention avoids the problems that the traditional P channel device is difficult to manufacture, the hole mobility is low, the acceptor impurity is difficult to activate, the process difficulty of the GaN-based heterogeneous material is high and the like, and realizes the P channel characteristic semiconductor device based on the double gates.

The invention controls the same channel through the bottom grid 3 and the top grid 10, and realizes the HEMT device with P channel characteristic, namely: when the device is turned off, the top grid 10 is connected with a low potential, the two-dimensional electron gas in the channel disappears, and an electric field pointing to the top grid from the bottom grid is generated at the channel. When the bottom grid 3 starts to fall from zero potential, the electric field of the bottom grid 3 pointing to the top grid 10 starts to be weakened, as the potential of the bottom grid 3 further falls, the channel two-dimensional electron gas is generated again, the device is controlled by the bottom grid 3 to complete the conversion from off to on, and therefore the characteristic of the P channel device of electron conduction is realized through the combined action of the bottom grid 3 and the top grid 10 on the channel two-dimensional electron gas.

It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.