阅读说明：本技术 晶体管结构及其制备方法 (Transistor structure and preparation method thereof ) 是由 化梦媛 于 2021-09-07 设计创作，主要内容包括：本申请涉及一种晶体管结构及其制备方法,包括栅极结构；栅极结构包括由下至上依次叠置的栅极、顶栅介质层及栅电极,且所述栅极与所述顶栅介质层相接触,所述顶栅介质层与所述栅电极相接触。本申请提供的晶体管结构通过在栅极的上层引入顶栅介质层,将原本应位于栅极上表面的峰值电场埋入顶栅介质层与栅极之间,避免半导体器件制备工艺过程对栅极上表面的影响,从而改善栅极的可靠性,提升半导体器件制备工艺的兼容性,简化半导体器件制备的工艺流程。(The application relates to a transistor structure and a preparation method thereof, comprising a grid structure; the grid structure comprises a grid, a top grid dielectric layer and a grid electrode which are sequentially overlapped from bottom to top, wherein the grid is in contact with the top grid dielectric layer, and the top grid dielectric layer is in contact with the grid electrode. According to the transistor structure, the top gate dielectric layer is introduced into the upper layer of the gate, and the peak electric field which should be located on the upper surface of the gate originally is buried between the top gate dielectric layer and the gate, so that the influence of the manufacturing process of the semiconductor device on the upper surface of the gate is avoided, the reliability of the gate is improved, the compatibility of the manufacturing process of the semiconductor device is improved, and the manufacturing process of the semiconductor device is simplified.)

1. A transistor structure comprising a gate structure; wherein the content of the first and second substances,

the grid structure comprises a grid, a top grid dielectric layer and a grid electrode which are sequentially overlapped from bottom to top, the grid is in contact with the top grid dielectric layer, and the top grid dielectric layer is in contact with the grid electrode.

2. The transistor structure of claim 1, wherein the gate comprises a P-type gallium nitride gate or a P-type aluminum gallium nitride gate.

3. The transistor structure of claim 1, wherein said gate electrode forms an ohmic contact or a schottky contact with said top gate dielectric layer, and said gate electrode forms a homojunction contact or a heterojunction contact with said top gate dielectric layer.

4. The transistor structure of claim 1, wherein said top gate dielectric layer is a single layer structure;

when the top gate dielectric layer and the grid form homojunction contact, the top gate dielectric layer comprises a doped gallium nitride layer or a doped aluminum gallium nitride layer;

when the top gate dielectric layer is in heterojunction contact with the gate, the top gate dielectric layer comprises a gallium nitride layer, a gallium oxide layer, a gallium oxynitride layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an indium gallium nitride layer or an aluminum indium gallium nitride layer.

5. The transistor structure of claim 1, wherein said top gate dielectric layer is a multi-layer structure of multiple dielectric layers stacked in sequence;

the material of each dielectric layer in the top gate dielectric layer is different, or the material of each dielectric layer is the same but the doping type of each dielectric layer is different.

6. The transistor structure of any of claims 1 to 5, further comprising:

a substrate;

the stress buffer layer is positioned on the substrate;

the two-dimensional electron gas structure is positioned on the stress buffer layer;

the source electrode is positioned on one side of the grid electrode structure and is in contact with the two-dimensional electron gas structure;

and the drain electrode is positioned on one side of the grid electrode structure, which is far away from the source electrode, and is in contact with the two-dimensional electron gas structure.

7. The transistor structure of claim 6, further comprising a passivation layer;

the passivation layer is positioned on the two-dimensional electron gas structure;

the grid structure, the source electrode and the drain electrode are all positioned in the passivation layer.

8. The transistor structure of claim 6, wherein the two-dimensional electron gas structure comprises:

the channel layer is positioned on the stress buffer layer;

a barrier layer on the channel layer;

the passivation layer is positioned on the barrier layer;

the source electrode and the drain electrode are both contacted with the barrier layer, or the source electrode and the drain electrode penetrate through the barrier layer and are contacted with the channel layer.

9. A method for manufacturing a transistor structure includes forming a gate structure;

the method for forming the gate structure comprises the following steps:

forming a grid electrode and a top grid dielectric layer, wherein the top grid dielectric layer is positioned on the grid electrode and is in contact with the grid electrode;

and forming a gate electrode on the top gate dielectric layer, wherein the gate electrode is in contact with the top gate dielectric layer.

10. The method of claim 9, wherein the step of forming the gate and top gate dielectric layer comprises the steps of:

forming a gate material layer;

forming a top gate dielectric material layer on the upper surface of the gate material layer;

and patterning the top gate dielectric material layer and the gate material layer to obtain the gate and the top gate dielectric layer.

11. The method for manufacturing a transistor structure according to claim 9, further comprising, before forming the gate and the top gate dielectric layer, the steps of:

providing a substrate;

forming a stress buffer layer on the substrate;

and forming a two-dimensional electron gas structure on the stress buffer layer.

12. The method for manufacturing a transistor structure according to claim 9, further comprising, before forming a gate electrode on the top gate dielectric layer:

and respectively forming a source electrode and a drain electrode which are respectively positioned at two opposite sides of the grid structure.

13. The method according to claim 9, wherein a gate electrode is formed on the top gate dielectric layer, and a source and a drain are formed at the same time, wherein the source and the drain are respectively located at two opposite sides of the gate structure.

Technical Field

The present disclosure relates to semiconductor devices, and particularly to a transistor structure and a method for fabricating the same.

Background

Gallium nitride (GaN) materials have excellent material characteristics, so that the GaN materials have wide application prospects in the field of next-generation high-frequency high-voltage electronic power devices. Because the gallium nitride material has a larger forbidden band width (about 3.4eV) and can form a low-resistance Two-dimensional electron gas (2 DEG) with an aluminum gallium nitride (AlGaN) heterojunction, the electronic power device based on the gallium nitride material has the advantages of high temperature resistance, high pressure resistance, high frequency, high speed and the like compared with the traditional silicon-based device. At present, a device prepared based on two-dimensional electron gas formed by a heterojunction has a normally-on characteristic, so that the normally-off device is more urgent in consideration of failure safety and simplification of a drive circuit design.

In the traditional transistor device, the peak electric field is positioned on the upper surface of the grid electrode under the positive grid voltage, which means that the distribution of the peak electric field can be easily influenced by the surface process, so that the performance of the transistor device is easily influenced by the surface process, the problem of uneven electric field is caused, and the reliability of long-time work of the grid electrode of the transistor device is greatly limited; in addition, the working voltage for reliable operation of the gate of the conventional transistor device is only about 7V, which increases the design difficulty of the driving circuit, and further limits the development of the transistor device.

Content of application

In view of the above, it is necessary to provide a transistor structure and a method for manufacturing the same, which address the gate degradation problem or other problems of the transistors in the background art.

According to some embodiments, an aspect of the present application provides a transistor structure comprising a gate structure; wherein the content of the first and second substances,

the grid structure comprises a grid, a top grid dielectric layer and a grid electrode which are sequentially overlapped from bottom to top, the grid is in contact with the top grid dielectric layer, and the top grid dielectric layer is in contact with the grid electrode.

In one embodiment, the gate comprises a P-type gallium nitride gate or a P-type aluminum gallium nitride gate.

In one embodiment, the gate electrode and the top gate dielectric layer form an ohmic contact or a Schottky contact, and the gate electrode and the top gate dielectric layer form a homojunction contact or a heterojunction contact.

In one embodiment, the top gate dielectric layer is of a single-layer structure;

when the top gate dielectric layer and the grid form homojunction contact, the top gate dielectric layer comprises a doped gallium nitride layer or a doped aluminum gallium nitride layer;

when the top gate dielectric layer is in heterojunction contact with the gate, the top gate dielectric layer comprises a gallium nitride layer, a gallium oxide layer, a gallium oxynitride layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an indium gallium nitride layer or an aluminum indium gallium nitride layer.

In one embodiment, the top gate dielectric layer is a multilayer structure of a plurality of dielectric layers which are sequentially stacked;

the material of each dielectric layer in the top gate dielectric layer is different, or the material of each dielectric layer is the same but the doping type of each dielectric layer is different.

In one embodiment, the transistor structure further comprises:

a substrate;

the stress buffer layer is positioned on the substrate;

the two-dimensional electron gas structure is positioned on the stress buffer layer;

the source electrode is positioned on one side of the grid electrode structure and is in contact with the two-dimensional electron gas structure;

and the drain electrode is positioned on one side of the grid electrode structure, which is far away from the source electrode, and is in contact with the two-dimensional electron gas structure.

In one embodiment, the transistor structure further comprises a passivation layer;

the passivation layer is positioned on the two-dimensional electron gas structure;

the grid structure, the source electrode and the drain electrode are all positioned in the passivation layer.

In one embodiment, the two-dimensional electron gas structure comprises:

the channel layer is positioned on the stress buffer layer;

a barrier layer on the channel layer;

the passivation layer is positioned on the barrier layer;

the source electrode and the drain electrode are both contacted with the barrier layer, or the source electrode and the drain electrode penetrate through the barrier layer and are contacted with the channel layer.

In another aspect, the present application also provides a method of fabricating a transistor structure according to some embodiments, including forming a gate structure;

the method for forming the gate structure comprises the following steps:

forming a grid electrode and a top grid dielectric layer, wherein the top grid dielectric layer is positioned on the grid electrode and is in contact with the grid electrode;

and forming a gate electrode on the top gate dielectric layer, wherein the gate electrode is in contact with the top gate dielectric layer.

In one embodiment, the forming of the gate and the top gate dielectric layer includes the following steps:

forming a gate material layer;

forming a top gate dielectric material layer on the upper surface of the gate material layer;

and patterning the top gate dielectric material layer and the gate material layer to obtain the gate and the top gate dielectric layer.

In one embodiment, before the forming of the gate and the top gate dielectric layer, the method further includes the following steps:

providing a substrate;

forming a stress buffer layer on the substrate;

and forming a two-dimensional electron gas structure on the stress buffer layer.

In one embodiment, before forming the gate electrode on the top gate dielectric layer, the method further includes the following steps:

and respectively forming a source electrode and a drain electrode which are respectively positioned at two opposite sides of the grid structure.

In one embodiment, a gate electrode is formed on the top gate dielectric layer, and a source and a drain are formed at the same time, wherein the source and the drain are respectively located at two opposite sides of the gate structure.

In one embodiment, after the forming of the gate and the top gate dielectric layer, the method further includes the following steps:

forming a passivation material layer on the two-dimensional electron gas structure, wherein the passivation material layer covers the upper surface of the two-dimensional electron gas structure, the grid electrode and the top grid dielectric layer;

forming a gate electrode on the top gate dielectric layer comprises the following steps:

forming a first opening in the passivation material layer, wherein the top gate dielectric layer is exposed out of the first opening;

and forming the gate electrode in the first opening.

In one embodiment, before forming the gate electrode on the top gate dielectric layer, the method further includes the following steps:

forming second openings in the passivation material layer, wherein the second openings are located on two opposite sides of the first openings;

and respectively forming a source electrode and a drain electrode in the second opening, wherein the source electrode and the drain electrode are respectively positioned at two opposite sides of the grid structure.

In one embodiment, a first opening is formed in the passivation material layer, and a second opening is formed in the passivation material layer at the same time to obtain the passivation layer, wherein the second opening is located on two opposite sides of the first opening;

and forming a source electrode and a drain electrode in the second opening respectively while forming the gate electrode in the first opening, wherein the source electrode and the drain electrode are respectively positioned at two opposite sides of the gate structure.

The transistor structure and the preparation method thereof provided by the application at least have the following beneficial effects:

according to the transistor structure, the top gate dielectric layer is introduced into the upper layer of the gate, and the peak electric field which should be located on the upper surface of the gate originally is buried between the top gate dielectric layer and the gate, so that the influence of the manufacturing process of the semiconductor device on the upper surface of the gate is avoided, the reliability of the gate is improved, the compatibility of the manufacturing process of the semiconductor device is improved, and the manufacturing process of the semiconductor device is simplified.

According to the preparation method of the transistor structure, the top gate dielectric layer is formed on the grid electrode, and the peak electric field which is originally positioned on the upper surface of the grid electrode is embedded between the top gate dielectric layer and the grid electrode, so that the influence of the preparation process of the semiconductor device on the upper surface of the grid electrode is avoided, the reliability of the grid electrode is improved, the compatibility of the preparation process of the semiconductor device is improved, and the preparation process of the semiconductor device is simplified.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic cross-sectional view of a transistor structure;

fig. 2 is a flow chart of a method for fabricating a transistor structure according to an embodiment of the present application;

fig. 3 is a schematic cross-sectional structure diagram of the structure obtained in step S3 in the method for manufacturing a transistor structure according to an embodiment of the present application;

fig. 4 is a flowchart of step S4 in a method for manufacturing a transistor structure according to an embodiment of the present application;

fig. 5 is a schematic cross-sectional structure diagram of the structure obtained in step S403 in the method for manufacturing a transistor structure according to an embodiment of the present application;

fig. 6 is a schematic cross-sectional structure diagram of the structure obtained in step S5 in the method for manufacturing a transistor structure according to an embodiment of the present application;

fig. 7 to 10 are schematic cross-sectional structures of structures obtained in steps S6 in a method for manufacturing a transistor structure according to an embodiment of the present application; fig. 10 is a schematic cross-sectional structure diagram of a transistor structure according to an embodiment of the present disclosure;

fig. 11 to 14 are schematic cross-sectional structures of a transistor structure according to another embodiment of the present application.

Description of reference numerals:

1', a substrate; 2', a stress buffer layer; 301', a channel layer; 302', a barrier layer; 4', a passivation layer; 5', a source electrode; 6', a drain electrode; 701', a grid; 703', a gate electrode; 1. a substrate; 2. a stress buffer layer; 3. a two-dimensional electron gas structure; 301. a channel layer; 302. a barrier layer; 4. a passivation layer; 411. a layer of passivation material; 421. a first opening; 5. a source electrode; 6. a drain electrode; 7. a gate structure; 701. a gate electrode; 702. a top gate dielectric layer; 703. a gate electrode; 712. an N-type gallium nitride layer; 722. a P-type gallium nitride layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," other elements or layers, it can be directly on the other elements or layers or intervening elements or layers may be present.

Spatial relationship terms, such as "on. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application, such that variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

A conventional transistor device is shown in fig. 1, and includes a substrate 1', a stress buffer layer 2', a channel layer 301', a barrier layer 302', and a passivation layer 4 'stacked in sequence from bottom to top, and further includes a gate structure (not labeled in fig. 1) located in the passivation layer 4', a source 5 'and a drain 6', where the source 5 'and the drain 6' are located at two opposite sides of the gate structure; the gate structure includes a gate 701 'and a gate electrode 703' stacked in sequence from bottom to top and contacting each other. However, in the conventional transistor device, the peak electric field is located on the upper surface of the gate 701' under the forward gate voltage, which means that the distribution of the peak electric field can be easily influenced by the surface process, so that the performance of the transistor device is easily influenced by the surface process, the problem of uneven electric field is caused, and the reliability of long-time operation of the gate of the transistor device is greatly limited; the reliable working voltage of the gate 701' of the conventional transistor device is only about 7V, which increases the design difficulty of the driving circuit, and further limits the development of the transistor device.

The conventional method for implementing a normally-off device includes a hole-type (P-type) gallium nitride gate structure, as shown in fig. 1, the P-type gallium nitride gate structure uses P-type gallium nitride or aluminum gallium nitride as a gate to deplete two-dimensional electron gas under a gate region to implement the normally-off device, and because the P-type gallium nitride gate structure has the advantages of small on-resistance of a gate region channel, simple process, stable threshold value and the like, industrialization has been achieved at present. P-type gallium nitride gate High Electron Mobility Transistors (HEMTs) are mainly classified into two types according to the contact type of the gate electrode metal and the P-type gallium nitride gate: ohmic contact type and schottky contact type. The schottky contact type is currently gaining more attention because it has lower forward gate leakage than the ohmic contact type. However, under the constant voltage gate stress, the schottky contact P-type gan gate hemt may have gate degradation and even breakdown after a certain time.

In a traditional transistor, a P-type gallium nitride grid is directly contacted with a grid electrode metal to form a Schottky junction, so that different grid electrode metals have great influence on the performance of a transistor device; and because the formation of the source/drain ohmic contact requires high-temperature annealing, the gate electrode and the P-type gallium nitride gate contact under the high-temperature annealing are degraded, so that the gate electrode has to be prepared after the source/drain, and cannot be prepared at the same time.

In view of this, the present application provides, in accordance with some embodiments, a method of fabricating a transistor structure, the method comprising the step of forming a gate structure.

Specifically, referring to fig. 2, the step of forming the gate structure may include:

s4: forming a grid electrode and a top grid dielectric layer, wherein the top grid dielectric layer is positioned on the grid electrode and is in contact with the grid electrode;

s6: and forming a gate electrode on the top gate dielectric layer, wherein the gate electrode is in contact with the top gate dielectric layer.

In the preparation method of the transistor structure provided by the embodiment, the top gate dielectric layer is formed on the gate, so that the depletion region of the obtained transistor structure can be widened towards two directions, the uniform distribution of the peak electric field in space under the forward gate voltage is realized, and the peak electric field which is originally positioned between the gate and the gate electrode is buried between the top gate dielectric layer and the gate, so that the reliability of the gate is improved; by forming the top gate dielectric layer on the gate, the top gate dielectric layer can also have a good protection effect on the gate, so that the influence of the preparation process (such as a high-temperature process or a surface process) of a semiconductor device on the upper surface of the gate can be avoided, meanwhile, the influence of different gate electrodes on the performance of the semiconductor device can be avoided, the compatibility of the preparation process of the semiconductor device is improved, and the process flow is simplified.

Further, in the conventional transistor structure, since the gate electrode is in direct contact with the gate electrode, all of the voltage drop may exist in the gate electrode when the gate structure is pressurized; according to the preparation method of the transistor structure, the spatial distribution of the peak electric field under the forward gate voltage can be changed through the top gate dielectric layer, so that the peak electric field can be uniformly regulated, the depletion region of the obtained transistor structure can be widened towards two directions, and the breakdown voltage of the gate structure is improved.

In one example, the gate may include, but is not limited to, a P-type gallium nitride gate, a P-type aluminum gallium nitride gate, or the like.

Referring to fig. 2, in an embodiment, step S4 may further include the following steps:

s1: providing a substrate 1;

s2: forming a stress buffer layer 2 on a substrate 1;

s3: a two-dimensional electron gas structure 3 is formed on the stress buffer layer 2, as shown in fig. 3.

In one example, the substrate 1 may include, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide substrate, and the like, and the material of the substrate 1 is not limited in the present application.

Specifically, a two-dimensional electron gas is formed in the two-dimensional electron gas structure 3; in the method for manufacturing the transistor structure provided by the embodiment, the two-dimensional electron gas formed in the two-dimensional electron gas structure 3 can be exhausted through the P-type gallium nitride gate or the P-type aluminum gallium nitride gate, so that the device is in a normally-off state, and the safer operation characteristic of the transistor structure is improved.

In an example, the stress buffer layer 2 may include, but is not limited to, any one or a combination of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), or the like, and the material of the stress buffer layer 2 is not limited in this application.

Continuing to refer to fig. 3, in one embodiment, step S3 may include the following steps:

a channel layer 301 and a barrier layer 302 are formed on the stress buffer layer 2 in this order from bottom to top.

In the method for manufacturing the transistor provided in the above embodiment, the two-dimensional electron gas is formed between the barrier layer 302 and the channel layer 301, and the gate can be normally off by depleting the two-dimensional electron gas thereunder.

In one example, the channel layer 301 may include, but is not limited to, a gallium nitride channel layer; in another example, barrier layer 302 may include, but is not limited to, an aluminum gallium nitride barrier layer; in the present application, the material of the channel layer 301 and the material of the barrier layer 302 are not limited.

For step S4, in one embodiment, referring to fig. 4, step S4 may include the following steps:

s401: forming a gate material layer 711;

s402: forming a top gate dielectric material layer 712 on the top surface of the gate material layer 711;

s403: the top gate dielectric material layer 712 and the gate material layer 711 are patterned to obtain the gate electrode 701 and the top gate dielectric layer 702, as shown in fig. 5, the top gate dielectric layer 702 is located on the gate electrode 701 and contacts the gate electrode 701.

Specifically, the top gate dielectric material layer 712 and the gate material layer 711 may be defined by, but not limited to, photolithography to form a gate region, and then the top gate dielectric material layer 712 and the gate material layer 711 outside the gate region are sequentially etched by using an etching process to form the top gate dielectric layer 702 and the gate 701.

In one embodiment, the top gate dielectric layer 702 may be a single layer structure, as shown in fig. 5.

In one embodiment, the gate electrode 701 may form a homojunction contact or a heterojunction contact with the top gate dielectric layer 702.

In the preparation method of the transistor structure provided by the embodiment, the gate 701 and the top gate dielectric layer 702 form homojunction contact or heterojunction contact, so that the gate 701 and the top gate dielectric layer 702 can form a P-N junction structure, a good depletion region expansion effect can be achieved in both the gate 701 and the top gate dielectric layer 702, and the peak electric field under the forward gate voltage is distributed more uniformly in space.

On the basis of the above embodiment, when the top gate dielectric layer 702 forms a homojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include, but is not limited to, any one of a doped gallium nitride layer or a doped aluminum gallium nitride layer, that is, when the top gate dielectric layer 702 forms a homojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include any one of a heavily doped N-type gallium nitride layer or a heavily doped N-type aluminum gallium nitride layer; when the top gate dielectric layer 702 forms a heterojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include, but is not limited to, any one of a gallium nitride layer, a gallium oxide layer, a gallium oxynitride layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an indium gallium nitride layer, or an aluminum indium gallium nitride layer.

In one embodiment, the top gate dielectric layer 702 may be a multi-layer structure of multiple dielectric layers stacked in sequence.

On the basis of the above embodiment, the material of each dielectric layer in the top gate dielectric layer 702 is different, or the material of each dielectric layer is the same but the doping type of each dielectric layer is different.

For example, referring to fig. 11, in one embodiment, the top gate dielectric layer 702 may include, but is not limited to, an N-type gallium nitride layer 712, a P-type gallium nitride layer 722, and an N-type gallium nitride layer 712 stacked in sequence from bottom to top, which is not limited in this application, and in an actual manufacturing process, the thicknesses and doping concentrations of the respective dielectric layers may be reasonably configured to ensure electrical isolation between P-N junctions.

Referring to fig. 6, in one embodiment, the step S4 may be followed by the following steps:

s5: a passivation material layer 411 is formed on the two-dimensional electron gas structure 3, and the passivation material layer 411 covers the upper surface of the two-dimensional electron gas structure 3, the gate 701 and the top gate dielectric layer 702.

In an example, the passivation material layer 411 may include, but is not limited to, any one or a combination of a silicon oxide layer (SiO2), a silicon nitride layer (SiNx), a silicon oxynitride layer (SiON), an aluminum oxide layer (Al2O3), an aluminum nitride layer (AlN) or an aluminum oxynitride layer (AlON), and the like, and the material and the structure of the passivation material layer 411 are not limited in this application.

Referring to fig. 7 to 10 in conjunction with S6 of fig. 2, a gate electrode 703 is formed on the top gate dielectric layer 702, and the gate electrode 703 contacts the top gate dielectric layer 702 in step S6. Specifically, in an example, as shown in fig. 10, the gate structure 7 may include a gate 701, a top gate dielectric layer 702, and a gate electrode 703 stacked in sequence from bottom to top.

Specifically, in one embodiment, step S6 may include the following steps:

forming a first opening 421 in the passivation layer 411, wherein the first opening 421 exposes the top gate dielectric layer 702, as shown in fig. 8;

a gate electrode 703 is formed in the first opening 421 as shown in fig. 10.

In one embodiment, before step S6, the source 5 and the drain 6 may be formed, respectively, and the source 5 and the drain 6 are located on two opposite sides of the gate structure 7, respectively.

Specifically, in one example, before the step of forming the gate electrode 703 in the first opening 421, second openings may be formed in the passivation material layer 411, where the second openings are located on two opposite sides of the first opening 421; and a source 5 and a drain 6 are formed in the second opening, as shown in fig. 9, the source 5 and the drain 6 are located on two opposite sides of the gate structure 7.

In another possible embodiment, the source 5 and the drain 6 may be formed at the same time in step S6, and the source 5 and the drain 6 are respectively located at two opposite sides of the gate structure 7.

Specifically, in one example, a second opening may be formed in the passivation material layer 411 at the same time as the first opening 421 is formed in the passivation material layer 411 to obtain the passivation layer 4, and the second opening is located at two opposite sides of the first opening 421, as shown in fig. 8.

In addition to the above embodiments, the gate electrode 703 is formed in the first opening 421, and the source 5 and the drain 6 are formed in the second opening (not shown in fig. 8), respectively, and the source 5 and the drain 6 are located on two opposite sides of the gate structure 7, as shown in fig. 10.

Specifically, in one embodiment, the first opening 421 and the second opening can be formed at the same time, and the source 5, the drain 6, and the gate electrode 703 can be formed simultaneously by a one-step process; that is, the source electrode 5, the drain electrode 6, and the gate electrode 703 may be separately formed or simultaneously formed.

In one example, the gate electrode 703 may form an ohmic contact, a schottky contact, or other contact with the top gate dielectric layer 702, and the application is not limited to the form of the contact formed between the gate electrode 703 and the top gate dielectric layer 702.

Specifically, in one embodiment, the gate electrode 703 may form an ohmic contact with the top gate dielectric layer 702.

In the method for manufacturing the transistor structure provided in the above embodiment, the ohmic contact is formed between the gate electrode 703 and the top gate dielectric layer 702, so that the source 5 and the drain 6 can be formed at the same time of step S6, the process steps are reduced, and the cost is reduced.

In one example, the source 5, the drain 6 and the gate electrode 703 may be formed by, but not limited to, photolithography, etching, deposition and/or lift-off, and the manner of forming the source 5, the drain 6 and the gate electrode 703 is not limited in this application.

In one example, the source 5 and drain 6 may both be in contact with the barrier layer 302, as shown in fig. 10, 13, and 14; in another example, as shown in fig. 12, the source electrode 5 and the drain electrode 6 may both contact the channel layer 301 through the barrier layer 302; this is not a limitation of the present application.

It is noted that in one example, the coverage of the gate electrode 703 may be smaller than that of the top gate dielectric layer 702, as shown in fig. 10; in another example, the coverage of the gate electrode 703 may also be equal to the top gate dielectric layer 702, as shown in fig. 13; in yet another example, the coverage of the gate electrode 703 may also be larger than the top gate dielectric layer 702, as shown in fig. 14; this is not a limitation of the present application.

In one embodiment, the coverage of the gate electrode 703 may be smaller than that of the top gate dielectric layer 702; in the manufacturing method of the transistor provided in the above embodiment, since the coverage of the gate electrode 703 is smaller than that of the top gate dielectric layer 702, the gate electrode 703 can be prevented from being prematurely broken down, and the breakdown voltage of the gate structure 7 is further increased.

The present application further provides a transistor structure, which may include a gate structure 7, according to some embodiments, with continued reference to fig. 10.

Specifically, the gate structure 7 may include a gate 701, a top gate dielectric layer 702, and a gate electrode 703 that are stacked in sequence from bottom to top, where the gate 701 is in contact with the top gate dielectric layer 702, and the top gate dielectric layer 702 is in contact with the gate electrode 703.

In the transistor structure provided by the embodiment, the top gate dielectric layer is introduced on the gate, so that the depletion region of the obtained transistor structure can be widened towards two directions, the uniform distribution of the peak electric field under the forward gate voltage on the space is realized, and the peak electric field which is originally positioned between the gate and the gate electrode is buried between the top gate dielectric layer and the gate, so that the reliability of the gate is improved; by introducing the top gate dielectric layer on the gate, the gate can be well protected, the influence of the preparation process (such as a high-temperature process or a surface process) of the semiconductor device on the upper surface of the gate can be avoided, the influence of different gate electrodes on the performance of the semiconductor device can be avoided, the compatibility of the preparation process of the semiconductor device is improved, and the process flow is simplified.

Further, in the conventional transistor structure, since the gate electrode is in direct contact with the gate electrode, all of the voltage drop may exist in the gate electrode when the gate structure is pressurized; according to the transistor structure provided by the embodiment, the uniform regulation and control of the peak electric field are realized by changing the spatial distribution of the peak electric field under the forward grid, so that the depletion region of the transistor structure can be widened towards two directions, and the breakdown voltage of the grid structure is improved.

In one embodiment, the gate 701 may include, but is not limited to, a P-type gallium nitride gate or a P-type aluminum gallium nitride gate.

In one example, the P-type gan gate may include, but is not limited to, a magnesium (Mg) doped gan gate or an aluminum gallium nitride gate, and the specific material of the P-type gan gate is not limited in this application.

In one embodiment, the P-type gallium nitride gate includes a high temperature anneal activated P-type gallium nitride layer.

The transistor structure provided in the above embodiment may avoid passivating the doping (such as magnesium doping) in the P-type gan gate during the growth of the top gate dielectric layer 702 by annealing the activated P-type gan layer at a high temperature.

In one example, the high temperature annealing temperature is 800 ℃ to 1200 ℃, such as 800 ℃, 900 ℃, 1000 ℃, 1100 ℃, or 1200 ℃, etc., and the temperature of the high temperature annealing is not limited in this application.

In one example, the gate electrode 703 may form an ohmic contact, a schottky contact, or other contact with the top gate dielectric layer 702, and the application is not limited to the form of the contact formed between the gate electrode 703 and the top gate dielectric layer 702.

Specifically, in one embodiment, the gate electrode 703 may form an ohmic contact with the top gate dielectric layer 702.

In the transistor structure provided by the embodiment, the ohmic contact is formed between the gate electrode 703 and the top gate dielectric layer 702, so that the source 5, the drain 6 and the gate electrode 703 can be simultaneously formed by one-step process in the process of preparing the transistor structure, the process steps are reduced, and the cost is reduced.

In one embodiment, the gate electrode 701 may form a homojunction contact or a heterojunction contact with the top gate dielectric layer 702.

In the transistor structure provided by the embodiment, the gate 701 and the top gate dielectric layer 702 form homojunction contact or heterojunction contact, so that the gate 701 and the top gate dielectric layer 702 can form a P-N junction structure, a good depletion region expansion effect can be achieved in both the gate 701 and the top gate dielectric layer 702, and the peak electric field under the forward gate voltage is distributed more uniformly in space.

In an example, the gate electrode 701 and the top gate dielectric layer 702 may further have a junction termination structure therebetween, such as a super junction, a metal field plate, a trench or a graded junction, and the like, which is not limited in this application. According to the application, the damage of a high electric field on the side wall of the gate structure 7 to the gate structure 7 can be reduced through the junction terminal structure between the gate 701 and the top gate dielectric layer 702.

It should be noted that the material and structure of the top gate dielectric layer 702 are not limited in this application.

In one embodiment, the top gate dielectric layer 702 may be a single layer structure.

On the basis of the above embodiment, when the top gate dielectric layer 702 forms a homojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include, but is not limited to, any one of a doped gallium nitride layer or a doped aluminum gallium nitride layer, that is, when the top gate dielectric layer 702 forms a homojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include any one of a heavily doped N-type gallium nitride layer or a heavily doped N-type aluminum gallium nitride layer; when the top gate dielectric layer 702 forms a heterojunction contact with the gate electrode 701, the top gate dielectric layer 702 may include, but is not limited to, any one of a gallium nitride layer, a gallium oxide layer, a gallium oxynitride layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an indium gallium nitride layer, or an aluminum indium gallium nitride layer.

In one embodiment, the top gate dielectric layer 702 may be a multi-layer structure of multiple dielectric layers stacked in sequence.

On the basis of the above embodiment, the material of each dielectric layer in the top gate dielectric layer 702 is different, or the material of each dielectric layer is the same but the doping type of each dielectric layer is different.

For example, referring to fig. 11, in one embodiment, the top gate dielectric layer 702 may include, but is not limited to, an N-type gallium nitride layer 712, a P-type gallium nitride layer 722, and an N-type gallium nitride layer 712 stacked in sequence from bottom to top, which is not limited in this application, and in an actual manufacturing process, the thicknesses and doping concentrations of the respective dielectric layers may be reasonably configured to ensure electrical isolation between P-N junctions.

In one embodiment, the gate electrode 703 may include, but is not limited to, any one or a combination of a polysilicon gate electrode, a metal gate electrode, or a metal gate electrode after high temperature annealing, and the material and the structure of the gate electrode 703 are not limited in this application.

Referring to fig. 10, in one embodiment, the transistor may further include a substrate 1, a stress buffer layer 2, a two-dimensional electron gas structure 3, a source 5, and a drain 6.

Specifically, the stress buffer layer 2 is positioned on the substrate 1; the two-dimensional electron gas structure 3 is positioned on the stress buffer layer 2; the source electrode 5 is positioned on one side of the grid electrode structure 7 and is in contact with the two-dimensional electron gas structure 3; the drain electrode 6 is located on a side of the gate structure 7 away from the source electrode 5 and is in contact with the two-dimensional electron gas structure 3.

In one example, the stress buffer layer 2 may include, but is not limited to, any one or a combination of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), or the like.

Specifically, a two-dimensional electron gas is formed in the two-dimensional electron gas structure 3; the transistor structure provided by the embodiment can exhaust the two-dimensional electron gas formed in the two-dimensional electron gas structure 3 through the P-type gallium nitride grid or the P-type aluminum gallium nitride grid, so that the device is in a normally-off state, and the safer operation characteristic of the transistor structure is improved.

In one example, the source electrode 5 and the drain electrode 6 may include, but are not limited to, a conductive film.

Continuing to refer to fig. 10, in one embodiment, the transistor may further include a passivation layer 4.

Specifically, the passivation layer 4 is positioned on the two-dimensional electron gas structure 3; the gate structure 7, the source 5 and the drain 6 are located within the passivation layer 4.

In an example, the passivation layer 4 may include, but is not limited to, any one or a combination of a silicon oxide layer (SiO2), a silicon nitride layer (SiNx), a silicon oxynitride layer (SiON), an aluminum oxide layer (Al2O3), an aluminum nitride layer (AlN) or an aluminum oxynitride layer (AlON), and the like, and the material and the structure of the passivation layer 4 are not limited in this application. The passivation layer 4 may be used to reduce current collapse.

With continued reference to fig. 10, in one embodiment, the two-dimensional electron gas structure 3 may include a channel layer 301 and a barrier layer 302.

Specifically, the channel layer 301 is located on the stress buffer layer 2; a barrier layer 302 is located on the channel layer 301.

In the transistor provided in the above embodiment, a two-dimensional electron gas is formed between the barrier layer 302 and the channel layer 301, and the gate 701 can be normally off by depleting the two-dimensional electron gas thereunder.

In one embodiment, a passivation layer 4 is on the barrier layer 302.

In one example, the source 5 and drain 6 may both be in contact with the barrier layer 302, as shown in fig. 10, 13, and 14; in another example, as shown in fig. 12, the source electrode 5 and the drain electrode 6 may both contact the channel layer 301 through the barrier layer 302; this is not a limitation of the present application.

In one example, the channel layer 301 may include, but is not limited to, a gallium nitride channel layer, and the material of the channel layer 301 is not limited in this application.

In one example, the barrier layer 302 may include, but is not limited to, an aluminum gallium nitride barrier layer, and the material of the barrier layer 302 is not limited in this application.

It is noted that in one example, the coverage of the gate electrode 703 may be smaller than that of the top gate dielectric layer 702, as shown in fig. 10; in another example, the coverage of the gate electrode 703 may also be equal to the top gate dielectric layer 702, as shown in fig. 13; in yet another example, the coverage of the gate electrode 703 may also be larger than the top gate dielectric layer 702, as shown in fig. 14; this is not a limitation of the present application.

In one embodiment, the coverage of the gate electrode 703 may be smaller than that of the top gate dielectric layer 702; in the manufacturing method of the transistor provided in the above embodiment, since the coverage of the gate electrode 703 is smaller than that of the top gate dielectric layer 702, the gate electrode 703 can be prevented from being prematurely broken down, and the breakdown voltage of the gate structure 7 is further increased.

It should be understood that, although the steps in the flowcharts of fig. 2 and 4 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2 and 4 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the other steps or stages.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.