阅读说明：本技术 薄膜晶体管、显示基板及显示装置 (Thin film transistor, display substrate and display device ) 是由 王成龙 方业周 李峰 姚磊 闫雷 李凯 候林 朱晓刚 高云 彭艳召 叶腾 杨桦 于 2020-06-30 设计创作，主要内容包括：本公开提供一种薄膜晶体管、显示基板及显示装置,属于显示技术领域。本公开的薄膜晶体管,其包括：基底,位于所述基底上的栅极、有源层、源极和漏极；其中,所述栅极包括依次设置所述基底上、且电连接的第一栅极和第二栅极；所述有源层位于所述第一栅极和所述第二栅极之间；且所述第一栅极和所述第二栅极在所述基底上的正投影均与所述有源层在所述基底上正投影部分重叠；所述第一栅极和所述第二栅极在所述基底上的正投影部分重叠。(The disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the technical field of display. The thin film transistor of the present disclosure includes: the substrate is positioned on the grid electrode, the active layer, the source electrode and the drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and orthographic projections of the first grid electrode and the second grid electrode on the substrate are partially overlapped with orthographic projections of the active layer on the substrate; orthographic projections of the first grid and the second grid on the substrate are partially overlapped.)

1. A thin film transistor, comprising: the substrate is positioned on the grid electrode, the active layer, the source electrode and the drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and orthographic projections of the first grid electrode and the second grid electrode on the substrate are partially overlapped with orthographic projections of the active layer on the substrate;

orthographic projections of the first grid and the second grid on the substrate are partially overlapped.

2. The thin film transistor according to claim 1, wherein a first gate insulating layer is provided between the layer where the first gate electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; a connecting part is arranged on one of the first grid and the second grid; wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate;

the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting portion electrically connects the first gate electrode and the second gate electrode through the first through hole.

3. The thin film transistor of claim 1, wherein the active layer includes a channel region, a source contact region and a drain contact region separately provided at both sides of the channel region; and the ion doping concentration of the source electrode contact region and the drain electrode contact region is greater than that of the channel region.

4. The thin film transistor of claim 3, wherein the active layer further comprises a first auxiliary region between the channel region and the source contact region, a second auxiliary region between the channel region and the drain contact region; the first auxiliary region and the second auxiliary region are not overlapped with the orthographic projection of the grid electrode on the substrate; wherein the ion doping concentration of the first auxiliary region and the second auxiliary region is less than the ion doping concentration of the source contact region and the drain contact region.

5. The thin film transistor of claim 4, wherein the first and second auxiliary regions each have an ion doping concentration greater than or equal to that of the channel region.

6. The thin film transistor according to claim 1, wherein a light-shielding layer is provided on a side of the active layer adjacent to the substrate; the light shielding layer is at least partially overlapped with the projection of the active layer on the substrate.

7. The thin film transistor according to claim 6, wherein the light shielding layer is provided in the same layer as the first gate electrode and is made of the same material; wherein, the orthographic projection of the light shielding layer and the first grid electrode on the substrate approximately covers the orthographic projection of the active layer on the substrate.

8. A display substrate comprises pixel units arranged in an array; a thin film transistor according to any one of claims 1 to 7 included in each pixel cell.

9. The display substrate according to claim 8, wherein a first gate insulating layer is provided between the layer where the first gate electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; the first grid electrodes in the pixel units on the same row are connected to form a first grid electrode strip; second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;

a second through hole penetrating through the first gate insulating layer and the second gate insulating layer is arranged between any two adjacent pixel units in the row direction; the first grid bar and the second grid bar in the same row of the pixel units are connected through the second through hole.

10. The display substrate according to claim 8, wherein a first gate insulating layer is provided between the layer where the first gate electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; the first grid electrodes in the pixel units on the same row are connected to form a first grid electrode strip; second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;

two ends of each first grid bar in the extending direction are respectively provided with a second through hole penetrating through the first grid insulating layer and the second grid insulating layer; the first grid bars and the second grid bars overlapped with the first grid bars in projection on the substrate are connected through the second through holes.

11. The display substrate according to claim 8, wherein a connection portion is provided on one of the first gate electrode and the second gate electrode; wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate; the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part electrically connects the first gate and the second gate through the first through hole;

any two adjacent connecting parts in the row direction are positioned on different sides in the column direction of the pixel unit where the connecting parts are positioned.

12. The display substrate according to claim 8, wherein a connection portion is provided on one of the first gate electrode and the second gate electrode; wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate; the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part electrically connects the first gate and the second gate through the first through hole;

the connecting part is arranged on the first grid electrode in one of any two adjacent pixel units, and the connecting part is arranged on the second grid electrode in the other one of the two adjacent pixel units.

13. A VR display device comprising the display substrate of any one of claims 8-12.

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a thin film transistor, a display substrate and a display device.

Background

Since a Virtual Reality (abbreviated as VR) display device has features of high resolution, fast response, high refresh frequency, high brightness backlight, high contrast, etc., its market is getting bigger and bigger, and the shipment volume is increasing year by year.

In the manufacturing process of a thin film transistor used in an existing low-temperature polysilicon VR display device, a wet etching process is used to form a gate on the surface of a polysilicon material layer, and at this time, on the premise that a photoresist covered on the surface of the gate is not removed, the photoresist on the surface of the gate is used as a mask to perform ion implantation on the polysilicon material layer to form a source contact region and a Drain contact region of an active layer, and then the photoresist on the surface of the gate is removed, and then a Lightly Doped Drain (LDD) process is performed on the polysilicon material layer to form a Lightly Doped Drain structure (i.e., an LDD structure).

The inventor finds that the electron mobility of the thin film transistor used in the conventional low-temperature polysilicon VR display device is high, and the leakage current Ioff of the pixel where the thin film transistor is located is large due to the influence of high backlight brightness, so that the production yield of the low-temperature polysilicon VR display device is reduced.

Disclosure of Invention

The present disclosure is directed to at least one of the problems of the prior art, and provides a thin film transistor, a display substrate and a display device.

In a first aspect, an embodiment of the present disclosure provides a thin film transistor, which includes: the substrate is positioned on the grid electrode, the active layer, the source electrode and the drain electrode on the substrate; the grid electrode comprises a first grid electrode and a second grid electrode which are sequentially arranged on the substrate and electrically connected; the active layer is positioned between the first grid electrode and the second grid electrode; and orthographic projections of the first grid electrode and the second grid electrode on the substrate are partially overlapped with orthographic projections of the active layer on the substrate;

orthographic projections of the first grid and the second grid on the substrate are partially overlapped.

A first grid insulating layer is arranged between the layer where the first grid electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; a connecting part is arranged on one of the first grid and the second grid; wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate;

the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting portion electrically connects the first gate electrode and the second gate electrode through the first through hole.

The active layer comprises a channel region, a source contact region and a drain contact region which are respectively arranged at two sides of the channel region; and the ion doping concentration of the source electrode contact region and the drain electrode contact region is greater than that of the channel region.

Wherein, the overlapped area of the orthographic projection of the active layer and the grid electrode on the substrate is the channel area; the active layer further comprises a first auxiliary region between the channel region and the source contact region, and a second auxiliary region between the channel region and the drain contact region; the first auxiliary region and the second auxiliary region are not overlapped with the orthographic projection of the grid electrode on the substrate; wherein the ion doping concentration of the first auxiliary region and the second auxiliary region is less than the ion doping concentration of the source contact region and the drain contact region.

Wherein the ion doping concentration of the first auxiliary region and the ion doping concentration of the second auxiliary region are both greater than or equal to the ion doping concentration of the channel region.

A light shielding layer is arranged on one side of the active layer close to the substrate; the light shielding layer is at least partially overlapped with the projection of the active layer on the substrate.

The light shielding layer and the first grid electrode are arranged on the same layer and are made of the same material; wherein, the orthographic projection of the light shielding layer and the first grid electrode on the substrate approximately covers the orthographic projection of the active layer on the substrate.

In a second aspect, an embodiment of the present disclosure provides a display substrate, which includes pixel units arranged in an array; each pixel unit comprises the thin film transistor.

A first grid insulating layer is arranged between the layer where the first grid electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; the first grid electrodes in the pixel units on the same row are connected to form a first grid electrode strip; second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;

a second through hole penetrating through the first gate insulating layer and the second gate insulating layer is arranged between any two adjacent pixel units in the row direction; the first grid bar and the second grid bar in the same row of the pixel units are connected through the second through hole.

A first grid insulating layer is arranged between the layer where the first grid electrode is located and the layer where the active layer is located; a second grid insulation layer is arranged between the layer where the active layer is located and the layer where the second grid is located; the first grid electrodes in the pixel units on the same row are connected to form a first grid electrode strip; second grid electrodes in the pixel units in the same row are connected to form a second grid electrode strip;

two ends of each first grid bar in the extending direction are respectively provided with a second through hole penetrating through the first grid insulating layer and the second grid insulating layer; the first grid bars and the second grid bars overlapped with the first grid bars in projection on the substrate are connected through the second through holes.

Wherein, the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate; the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part electrically connects the first gate and the second gate through the first through hole;

any two adjacent connecting parts in the row direction are positioned on different sides in the column direction of the pixel unit where the connecting parts are positioned.

Wherein a connecting part is arranged on one of the first grid and the second grid, wherein the orthographic projection of the connecting part on the substrate protrudes out of the overlapping region of the orthographic projections of the first grid and the second grid on the substrate; the thin film transistor further comprises a first through hole penetrating through the first gate insulating layer and the second gate insulating layer, and the connecting part electrically connects the first gate and the second gate through the first through hole; the connecting part is arranged on the first grid electrode in one of any two adjacent pixel units, and the connecting part is arranged on the second grid electrode in the other one of the two adjacent pixel units.

In a third aspect, embodiments of the present disclosure provide a VR display device, which includes the above display substrate.

Drawings

Fig. 1 is a cross-sectional view of a thin film transistor of an embodiment of the present disclosure;

fig. 2 is a schematic perspective view of a gate and an active layer of a thin film transistor in an embodiment of the disclosure;

fig. 3a is a top view of a thin film transistor according to an embodiment of the disclosure with a light-shielding layer formed thereon;

FIG. 3b is a cross-sectional view A-A' of FIG. 3 a;

fig. 4a is a top view of a thin film transistor according to an embodiment of the present disclosure forming a first gate thereof;

FIG. 4B is a cross-sectional view of B-B' of FIG. 4 a;

fig. 5a is a top view of a thin film transistor of an embodiment of the present disclosure forming an active layer thereof;

FIG. 5b is a cross-sectional view of C-C' of FIG. 5 a;

fig. 6a is a top view of a thin film transistor of an embodiment of the present disclosure forming a first via thereof;

FIG. 6b is a cross-sectional view of D-D' of FIG. 6 a;

fig. 7a is a top view of a thin film transistor of an embodiment of the present disclosure forming a second gate thereof;

FIG. 7b is a cross-sectional view of E-E' of FIG. 7 a;

fig. 8 is a schematic view of ion doping of a source contact region and a drain contact region of a thin film transistor according to an embodiment of the disclosure;

FIG. 9 is a schematic view of a second via disposed in a display substrate according to an embodiment of the disclosure;

fig. 10 is a schematic diagram of forming a second gate bar in a display substrate according to an embodiment of the disclosure;

fig. 11 is a schematic view of a display substrate according to an embodiment of the disclosure.

Wherein the reference numerals are: 10. a substrate; 111. a first gate electrode; 112. a second gate electrode; 12. an active layer; 13. a source electrode; 14. a drain electrode; 15. a buffer layer; 16. a first gate insulating layer; 17. a second gate insulating layer; 18. a first interlayer insulating layer; 19. a second interlayer insulating layer; 20. a light-shielding layer; 21. a planarization layer; 22. a pixel electrode; 23. a third interlayer insulating layer; 24. a common electrode; 100. a first gate bar; 200. a second gate bar; 30. a connecting portion; 40. a first via hole; 50. a second via hole; 60. a photoresist pattern.

Detailed Description

For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Before describing the thin film transistor, the method for manufacturing the thin film transistor, the array substrate, and the display device in the embodiments of the present disclosure, the following points are described.

In an embodiment of the present disclosure, a patterning process, such as a photolithographic patterning process, includes: coating photoresist on a structural layer to be patterned, wherein the coating of the photoresist film can adopt a spin coating, blade coating or roller coating mode; then, exposing the photoresist by using a mask plate, and developing the exposed photoresist layer to obtain a photoresist pattern; then etching the structural layer by using the photoresist pattern, and optionally removing the photoresist; finally, the residual photoresist is stripped to form a required structure.

In the embodiments of the present disclosure, the "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern using the same film forming process and then performing a one-time patterning process using the same mask. The sequential patterning process may include multiple exposure, development or etching processes depending on the specific pattern, and the specific pattern of the formed layer may be continuous or discontinuous, and may be at different heights or have different thicknesses.

In the embodiment of the present disclosure, the thin film transistor may be an N-type thin film transistor, or may be a P-type thin film transistor; the N-type thin film transistor is characterized in that N-type ion doping is carried out on an active layer of the thin film transistor; the P-type thin film transistor refers to P-type ion doping on an active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal. In the following embodiments, the thin film transistor is described as an N-type thin film transistor, but the present disclosure is not limited to the N-type thin film transistor.

The thin film transistor, the method for manufacturing the thin film transistor, the array substrate, and the display device in the embodiments of the present disclosure are described below with reference to the drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 1 is a cross-sectional view of a thin film transistor of an embodiment of the present disclosure; fig. 2 is a schematic perspective view of a gate electrode and an active layer of a thin film transistor in an embodiment of the disclosure.

In a first aspect, as shown in fig. 1 and 2, embodiments of the present disclosure provide a thin film transistor, including: a substrate 10 on which a gate electrode, an active layer 12, a source electrode 13, and a drain electrode 14 are disposed; the thin film transistor in the embodiment of the present disclosure is specifically a dual-gate thin film transistor, and the gate electrode of the thin film transistor specifically includes a first gate electrode 111 and a second gate electrode 112, which are sequentially disposed on the substrate 10 and electrically connected to each other; the active layer 12 is located between the first gate 111 and the second gate 112, and the orthographic projections of the first gate 111 and the second gate 112 on the substrate 10 are overlapped with the orthographic projection of the active layer 12 on the substrate 10; in particular, in the disclosed embodiment the orthographic projections of the first gate 111 and the second gate 112 on the substrate 10 partially overlap.

It should be noted that the overlapping region of the gate and the orthographic projection of the active layer 12 on the substrate 10 defines a channel region Q1 of the active layer 12; in the embodiment of the present disclosure, the channel region Q1 of the active layer 12 is a region where the active layer 12 overlaps with orthographic projections of the first gate 111 and the second gate 112 on the substrate 10. Two ends of the channel region Q1 of the active layer 12 are a source contact region Q2 and a drain contact region Q3 of the active layer 12, respectively. The source electrode 13 and the drain electrode 14 of the tft are connected to the source contact region Q2 and the drain contact region Q3 of the active layer 12, respectively. A first gate insulating layer 16 is provided between the layer where the first gate electrode 111 is located and the layer where the active layer 12 is located; a second gate insulating layer 17 is provided between the layer of the active layer 12 and the layer of the second gate electrode 112. The first and second gate electrodes 111 and 112 may be electrically connected through a first via hole 40 penetrating the first and second gate insulating layers 16 and 17.

In the thin film transistor of the embodiment of the present disclosure, since the first gate electrode 111 and the second gate electrode 112 are electrically connected, when a high level signal is applied to one of the first gate electrode 111 and the second gate electrode 112, an electric field is generated in the first gate insulating layer 16 and the second gate insulating layer 17, electric lines of force in the first gate electrode 111 are directed from the first gate electrode 111 to the lower surface of the active layer 12 (the surface close to the substrate 10) and induced charges are generated in the lower surface of the active layer 12; the electric field lines in the second gate insulating layer 17 are directed from the second gate electrode 112 to the upper surface (surface facing away from the substrate 10) of the active layer 12, and generate induced charges on the upper surface of the active layer 12; with the application of high level signals on the first gate 111 and the second gate 112, the upper and lower surfaces of the active layer 12 will be changed from depletion layer to electron accumulation layer to form inversion layer, when strong inversion is achieved (i.e. when the turn-on voltage is reached), the voltage applied between the source 13 and the drain 14 will cause carriers to pass through the active channel region Q1, so that the tft is in on state. Meanwhile, it can be seen that, since the first gate electrode 111 and the second gate electrode 112 in the thin film transistor are respectively disposed on the upper and lower surfaces of the active layer 12, the electron mobility of the thin film transistor is higher than that of a single-gate thin film transistor, and the on performance of the thin film transistor is better.

In addition, in the thin film transistor of the embodiment of the present disclosure, the orthographic projections of the first gate electrode 111 and the second gate electrode 112 on the substrate 10 are partially overlapped, and since the electrical signals applied to the first gate electrode 111 and the second gate electrode 112 are the same, there is no electric field at the overlapped position of the two, and therefore, the orthographic projection of the active layer 12 on the substrate 10 and the orthographic projection of the first gate electrode 111 and the second gate electrode 112 on the substrate 10 (i.e., the a region shown in fig. 2) have no electric field driving, and when the transistor is turned off, since the active layer 12 has the a region, the leakage current of the thin film transistor can be effectively reduced.

In some embodiments, the connection portion 30 is disposed on one of the first and second gate electrodes 111 and 112, and at least a portion of an orthogonal projection of the first via 40 penetrating the first and second gate insulating layers 16 and 17 on the substrate 10 falls within an orthogonal projection of the connection portion 30 on the substrate 10. It should be noted that the connection portion 30 may be a protruding structure connected to the first gate 111 or the second gate 112, so that an orthographic projection of the connection portion on the substrate 10 protrudes from an overlapping region of the orthographic projections of the first gate 111 and the second gate 112 on the substrate.

Specifically, when the connection portion 30 is disposed on the first gate 111, the first gate 111 is connected to the connection portion 30, and an orthographic projection of the connection portion 30 on the substrate 10 overlaps with an orthographic projection of the second gate 112 on the substrate 10, for example: the orthographic projection of the connecting part 30 on the substrate 10 and the orthographic projection of the second grid 112 on the substrate 10 are covered; the connection portion 30 is connected to the second gate 112 through the first via 40, so as to complete the electrical connection between the first gate 111 and the second gate 112; when the connection portion 30 is disposed on the second gate 112, the second gate 112 is connected to the connection portion 30, and an orthographic projection of the connection portion 30 on the substrate 10 overlaps with an orthographic projection of the first gate 111 on the substrate 10, for example: the orthographic projection of the connecting part 30 on the substrate 10 and the orthographic projection of the first grid 111 on the substrate 10 are covered; the connection portion 30 is connected to the first gate 111 through the second via 50, thereby completing the electrical connection between the first gate 111 and the second gate 112; the reason why the connection portion 30 is used to electrically connect the first gate electrode 111 and the second gate electrode 112 is that, in order to ensure the electron mobility of the thin film transistor, the size of the overlapping region of the first gate electrode 111 and the second gate electrode 112 should not be too wide, and therefore, in order to make the first gate electrode 111 and the second gate electrode 112 electrically connected well, the connection portion 30 is added to connect the two, thereby ensuring the electron mobility of the thin film transistor.

It should be noted that the first via hole 40 may be a metal via hole, that is, a layer of metal is formed on a sidewall of the first via hole 40 to electrically connect the first gate 111, the connection portion 30, and the second gate 112; of course, the first gate 111, the connection portion 30, and the second gate 112 may be electrically connected by filling the first via 40 with a metal conductive material.

In some embodiments, when the connection portion 30 is disposed on the first gate 111, the first gate 111 and the connection portion 30 are integrally formed, that is, the first gate 111 and the connection portion 30 are disposed on the same layer and have the same material, so that a pattern including the first gate 111 and the connection portion 30 can be formed in one patterning process. Similarly, when the connection portion 30 is disposed on the second gate 112, the second gate 112 and the connection portion 30 are integrally formed, that is, the second gate 112 and the connection portion 30 are disposed on the same layer and have the same material, so that a pattern including the second gate 112 and the connection portion 30 can be formed in one patterning process. 4a is a top view of the thin film transistor of the embodiment of the present disclosure forming the first gate 111 thereof; the first gate 111 and the connection portion 30 shown in fig. 4a are described as an example in the embodiment of the present disclosure.

In some embodiments, the active layer 12 includes a channel region Q1 and source and drain contact regions Q2 and Q3 located across the channel region Q1; the ion doping concentration of the source contact region Q2 and the drain contact region Q3 is greater than that of the channel region Q1, which is favorable for the source contact region Q2 and the drain contact region Q3 of the active layer 12 to have good ohmic contact with the source electrode 13 and the drain electrode 14 connected thereto, respectively. Specifically, the active layer 12 may be channel-doped after the active layer 12 is patterned for the first time to adjust the threshold voltage Vth of the thin film transistor. After the second gate electrode 112 is patterned, the source contact region Q2 and the drain contact region Q3 of the active layer 12 are heavily doped such that the ion doping concentration of the source contact region Q2 and the drain contact region Q3 forming the active layer 12 is greater than the ion doping concentration of the channel region Q1.

In some embodiments, as shown in fig. 2, the active layer 12 includes not only the channel region Q1, the source contact region Q2, and the drain contact region Q3 described above; and further includes a first auxiliary region Q4 between the channel region Q1 and the source contact region Q2, and a second auxiliary region Q5 between the channel region Q1 and the drain contact region Q3; it can be understood that the overlapping region of the orthographic projection of the active layer 12 and the gate electrode on the substrate 10 defines the channel region Q1 of the active layer 12, that is, the position of the overlapping region of the active layer 12 and the orthographic projection of the first gate electrode 111 and the second gate electrode 112 is the channel region Q1 of the active layer 12, and the orthographic projection of the source contact region Q2, the drain contact region Q3, the first auxiliary region Q4 and the second auxiliary region Q5 on the substrate 10 overlaps with both the first gate electrode 111 and the second gate electrode 112 for the active layer 12. The ion doping concentrations of the first auxiliary region Q4 and the second auxiliary region Q5 are smaller than the ion doping concentrations of the source contact region Q2 and the drain contact region Q3; therefore, the first auxiliary region Q4 and the second auxiliary region Q5 of the active layer 12 have semiconductor characteristics, and compared with the source contact region Q2 and the drain contact region Q3, the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped (i.e., the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped again after channel doping), and at the same time, the first auxiliary region Q4 and the second auxiliary region Q5 do not overlap with the orthographic projections of the first gate 111 and the second gate 112 on the substrate 10, so when the transistor is turned off, since the active layer 12 has the first auxiliary region Q4 and the second auxiliary region Q5, the leakage current of the thin film transistor can be effectively reduced.

Of course, the first auxiliary region Q4 and the second auxiliary region Q5 correspond to channel doping, that is, the ion doping concentration of the first auxiliary region Q4 and the second auxiliary region Q5 is the same as the doping concentration of the channel region Q1, that is, when the channel region Q1, the source contact region Q2 and the drain contact region Q3 of the active layer 12 are subjected to the first patterning of the active layer 12, the first auxiliary region Q4 and the second auxiliary region Q5 are lightly doped at the same time to adjust the threshold voltage Vth of the thin film transistor.

Fig. 3a is a top view of a thin film transistor according to an embodiment of the present disclosure, in which a light-shielding layer 20 is formed; FIG. 3b is a cross-sectional view A-A' of FIG. 3 a; in some embodiments, as shown in fig. 3a and 3b, in order to avoid light from irradiating the active layer 12 and causing a large leakage current in the thin film transistor, the light shielding layer 20 is formed on a side of the active layer 12 close to the substrate 10, and an orthographic projection of the light shielding layer 20 on the substrate 10 at least covers a portion of the channel region Q1 of the active layer 12.

In one example, the light shielding layer 20 is disposed on a side of the first gate electrode 111 close to the substrate 10, and the buffer layer 15 is disposed between the light shielding layer 20 and the first gate electrode 111, and an orthographic projection of the light shielding layer 20 on the substrate 10 completely covers an orthographic projection of the channel region Q1 of the active layer 12 on the substrate 10.

In another example, the light shielding layer 20 may be disposed on the same layer as the first gate electrode 111, and an orthographic projection of the light shielding layer 20 and the first gate electrode 111 on the substrate 10 substantially completely covers an orthographic projection of the channel region Q1 of the active layer 12 on the substrate 10. It should be noted that the reason why the orthographic projection of the light shielding layer 20 and the first gate 111 on the substrate 10 substantially completely covers the orthographic projection of the channel region Q1 of the active layer 12 on the substrate 10 is that a certain gap exists between the light shielding layer 20 and the first gate 111 to prevent the light shielding layer 20 and the first gate 111 from being electrically connected to affect the switching characteristics of the thin film transistor.

In order to make the structures of the layers of the thin film transistor in the embodiment of the present disclosure clearer, the thin film transistor in the embodiment of the present disclosure is further described with reference to the following method for manufacturing the thin film transistor.

The embodiment of the present disclosure provides a method for manufacturing a thin film transistor, which specifically includes the following steps:

step one, providing a substrate 10, and forming a pattern including a light-shielding layer 20 on the substrate 10 through a patterning process, as shown in fig. 3a and 3 b.

In some embodiments, the material of the light shielding layer 20 may be a light shielding metal material including, but not limited to, Mo. Taking the material of the light shielding layer 20 as metal Mo as an example, the first step may specifically include: a Mo metal material is deposited on the substrate 10, and a pattern including the light shielding layer 20 is formed by performing exposure, development, and etching processes directly under a position corresponding to the channel region Q1 of the active layer 12 to be formed.

The substrate 10 in the embodiment of the present disclosure is a transparent insulating substrate 10, and the material of the substrate 10 includes, but is not limited to, glass, quartz, and other suitable materials may also be used.

Step two, fig. 4a is a top view of the thin film transistor of the embodiment of the present disclosure forming the first gate 111;

FIG. 4B is a cross-sectional view of B-B' of FIG. 4 a; as shown in fig. 4a and 4b, a buffer layer 15 is formed on the substrate 10 on which the light-shielding layer 20 is formed, and a pattern of a first gate 111 including a gate is formed on a side of the buffer layer 15 away from the substrate 10 through a patterning process.

In the embodiment of the present disclosure, the material of the buffer layer 15 may be selected to be similar to the lattice structure of Si, for example, Si_xN_yOr Si_xO_y: silicon nitride or silicon oxide. Specifically, the structure may be a single-layer structure with silicon nitride or silicon oxide, or a composite film structure with silicon nitride or silicon oxide may be adopted.

The first gate 111 is made of a conductive material such as molybdenum Mo, a molybdenum-niobium alloy, aluminum Al, an aluminum-neodymium alloy, titanium Ti, or copper Gu. The first gate 111 material layer may have a single-layer structure or a multi-layer structure, such as a Ti/Al/Ti tri-layer structure.

In some embodiments, step two may specifically include: a buffer layer 15 is formed on the substrate 10 formed with the light-shielding layer 20 by means including, but not limited to, deposition to provide a heat insulating layer and a heat conducting layer when the active layer 12 is subsequently annealed. A first gate metal material layer is formed on the substrate 10 on which the buffer layer 15 is formed, and a pattern including the first gate electrode 111 and the connection part 30 is formed through exposure, development, and etching processes.

Step three, fig. 5a is a top view of the thin film transistor of the embodiment of the present disclosure forming the active layer 12 thereof; FIG. 5b is a cross-sectional view of C-C' of FIG. 5 a; as shown in fig. 5a and 5b, a first gate insulating layer 16 is formed on the substrate 10 on which the first gate electrode 111 is formed, and a pattern including the active layer 12 is formed through a patterning process on a side of the first gate insulating layer 16 facing away from the substrate 10.

In the embodiment of the present disclosure, the material of the first gate insulating layer 16 may be selected to be similar to the lattice structure of Si, for example, Si_xN_yOr Si_xO_y: silicon nitride or silicon oxide. Specifically, the structure may be a single-layer structure with silicon nitride or silicon oxide, or a composite film structure with silicon nitride or silicon oxide may be adopted.

In the embodiment of the present disclosure, the material of the active layer 12 is amorphous silicon, polysilicon, or an oxide semiconductor. The polycrystalline silicon may be high-temperature polycrystalline silicon or low-temperature polycrystalline silicon, and the oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Gallium Zinc Oxide (GZO), or the like. In the embodiment of the present disclosure, the active layer 12 is made of low temperature polysilicon.

In some embodiments, step three may specifically include: firstly, a gate insulating layer and an amorphous silicon film (a-Si) are sequentially formed by a deposition mode, wherein the deposition mode comprises a plasma enhanced chemical vapor deposition mode and a low-pressure chemical vapor deposition mode.

Next, the amorphous silicon film is crystallized by using an excimer laser crystallization method, a metal induced crystallization method or a solid phase crystallization method to transform the amorphous silicon film into a polysilicon film (P-Si), and then the polysilicon film (P-Si) is doped (P-type doping or N-type doping) to determine the conductivity type of the channel region Q1 of the TFT. Wherein, the doping of the amorphous silicon film in the step is channel doping, and specifically, the amorphous silicon film can be doped with 3-valent boron ions. Here, since the ion concentration of the amorphous silicon film to be doped determines the threshold voltage Vth of the thin film transistor, the ion concentration to be doped needs to be adjusted in accordance with the threshold voltage Vth of the thin film transistor.

In addition, the excimer laser crystallization mode and the metal induced crystallization mode in the step are two methods of low-temperature polysilicon, and are more common methods for converting amorphous silicon into polysilicon. However, the method of converting amorphous silicon into polysilicon of the present disclosure is not limited to the method using low-temperature polysilicon as long as the active layer 12 can be converted into a desired polysilicon thin film.

Finally, a layer of photoresist is formed on the polysilicon film, the photoresist is exposed and developed, and then the polysilicon film is dry-etched to form a pattern including the active layer 12.

Step four, fig. 6a is a top view of the thin film transistor of the embodiment of the present disclosure forming the first via hole 40; FIG. 6b is a cross-sectional view of D-D' of FIG. 6 a; as shown in fig. 6a and 6b, a second gate insulating layer 17 is formed on the substrate 10 on which the active layer 12 is formed, and a first via hole 40 penetrating through the first gate insulating layer 16 and the second gate insulating layer 17 is formed at a position of the second gate insulating layer 17 corresponding to the connection portion 30, and the second gate electrode 112 may be connected to the connection portion 30 through the first via hole 40 for subsequent formation, so as to complete electrical connection of the first gate electrode 111 and the second gate electrode 112.

Here, the material of the second gate insulating layer 17 may be the same as the material of the first gate insulating layer 16, and thus, the material of the second insulating layer will not be described here.

In some embodiments, step four may specifically include: the second gate insulating layer 17 is deposited, and a first via hole 40 penetrating through the first gate insulating layer 16 and the second gate insulating layer 17 is formed at a position corresponding to the connection portion 30 through exposure, development, and etching processes.

Step five, fig. 7a is a top view of the thin film transistor of the embodiment of the present disclosure forming the second gate 112 thereof; FIG. 7b is a cross-sectional view of E-E' of FIG. 7 a; as shown in fig. 7a and 7b, a pattern including the second gate electrode 112 is formed through a patterning process on the substrate 10 on which the second gate insulating layer 17 is formed. The formed second gate 112 is connected to the connection portion 30 through the first via 40, and the second gate 112 overlaps with an orthographic projection portion of the first gate 111 on the substrate 10.

The material and the manufacturing process of the second gate 112 may be the same as those of the first gate 111, and therefore, the forming process of the second gate 112 will not be described herein.

And sixthly, performing ion implantation (namely heavy doping) on the source contact region Q2 and the drain contact region Q3 of the active layer 12 on the substrate 10 on which the second gate 112 is formed to enhance the ohmic contact between the active layer 12 and the source electrode 13 and the drain electrode 14 and ensure that P-Si forms good ohmic contact with the source electrode 13 and the drain electrode 14.

In some embodiments, fig. 8 is a schematic view of ion doping of a source contact region Q2 and a drain contact region Q3 of a thin film transistor according to an embodiment of the present disclosure; as shown in fig. 8, the sixth step may specifically include forming a photoresist layer on a side of the second gate electrode 112 facing away from the substrate 10, exposing the photoresist layer to light, forming a photoresist pattern 60, performing ion implantation using the photoresist pattern 60 as a mask for the source contact region Q2 and the drain contact region Q3 of the active layer 12, and heavily doping the source contact region Q2 and the drain contact region Q3 of the active layer 12 by including, but not limited to, phosphorus ions having a valence of 5 to enhance ohmic contact of the active layer 12 with the source electrode 13 and the drain electrode 14.

In addition, in some embodiments, the width of the patterned photoresist is greater than the line width of the gates formed by the first gate 111 and the second gate 112, so that after the source contact region Q2 and the drain contact region Q3 are heavily doped, a section of the active layer 12 structure is not heavily doped between the channel region Q1 and the source contact region Q2, and between the channel region Q1 and the drain contact region Q3, which are the first auxiliary region Q4 and the second auxiliary region Q5, respectively; the first auxiliary region Q4 and the second auxiliary region Q5 both have only the implantation of the boron ions with 3 valence, and the first auxiliary region Q4 and the second auxiliary region Q5 both do not overlap with the projections of the first gate 111 and the second gate 112 on the substrate 10, so the first auxiliary region Q4 and the second auxiliary region Q5 are equivalent to the lightly doped drain structure, and the leakage current can be effectively reduced, as shown in fig. 2. It should be noted that the first auxiliary region Q4 and the second auxiliary region Q5 may only include one doping during channel doping, or may perform a light doping step on the first auxiliary region Q4 and the second auxiliary region Q5 after heavy doping, and the ion concentration of the doped first auxiliary region Q4 and the doped second auxiliary region Q5 depends on the switching characteristic requirement of the thin film transistor.

The ion implantation method includes an ion implantation method with a mass analyzer, an ion cloud implantation method without a mass analyzer, a plasma implantation method, or a solid diffusion implantation method. That is, in the present embodiment, the active layer 12 with good semiconductor properties is finally formed by performing a plurality of steps such as crystallization, doping, and ion implantation on the low temperature polysilicon material.

Seventhly, as shown in fig. 1, after heavily doping the source contact region Q2 and the drain contact region Q3 of the active layer 12, forming a first interlayer insulating layer 18 on the substrate 10 on which the second gate 112 is formed, and exposing, developing and etching the position where the first interlayer insulating layer 18 is formed and the source contact region Q2, so as to form a source 13 contact via hole penetrating through the first interlayer insulating layer 18 and the second gate insulating layer 17; then, a pattern including the source electrode 13 is formed through a patterning process, and the source electrode 13 is connected with the source electrode 13 through a source electrode 13 contact via hole; next, on the substrate 10 on which the source electrode 13 is formed, forming a second interlayer insulating layer 19, and exposing, developing, and etching a position where the second interlayer insulating layer 19 is formed corresponding to the drain contact region Q3 to form a source electrode 13 contact via hole penetrating through the second interlayer insulating layer 19, the first interlayer insulating layer 18, and the second gate insulating layer 17; a pattern including the drain electrode 14 is then formed through a patterning process, at which time the drain electrode 14 is connected to the drain electrode 14 through a drain electrode 14 contact via.

It should be noted that the source electrode 13 and the drain electrode 14 formed in the seventh step are of a layered structure, that is, are separately arranged in a two-layer structure, wherein the preparation sequence of the source electrode 13 and the drain electrode 14 can be changed, and in the embodiment of the present disclosure, the drain electrode 14 is formed on the source electrode 13 as an example, so that the size of the thin film transistor can be reduced, which is beneficial to improving the aperture ratio of the display substrate of the thin film transistor; of course, it is also possible to form the source electrode 13 and the drain electrode 14 of the thin film transistor in the same layer through a single patterning process.

In some embodiments, an activation hydrogenation process may be performed to repair the crystal lattice of the active layer 12 when forming the source 13 contact via hole penetrating the first interlayer insulating layer 18 and the second gate insulating layer 17.

In step seven, the materials of the first interlayer insulating layer 18 and the second interlayer insulating layer 19 may be the same as the material of the first gate insulating layer 16, and thus, the description thereof will not be repeated. The materials and the manufacturing processes of the source electrode 13 and the drain electrode 14 are the same as those of the gate electrode, and thus the description thereof is not repeated.

The fabrication of the thin film transistor in the embodiments of the present disclosure is completed.

In a second aspect, embodiments of the present disclosure provide a display substrate, where the display substrate may be used in a VR display device, the display substrate includes pixel units arranged in an array, and each pixel unit may include any one of the above thin film transistors.

Since the display substrate in the embodiment of the disclosure includes any one of the above thin film transistors, the leakage current of the thin film transistor is small, and the performance of the display substrate is good.

In some embodiments, fig. 9 is a schematic diagram of a second via 50 disposed in a display substrate according to an embodiment of the disclosure; fig. 10 is a schematic diagram of forming a second gate bar 200 in a display substrate according to an embodiment of the disclosure; as shown in fig. 9 and 10, a first gate insulating layer 16 is provided between the first gate electrode 111 and the layer where the active layer 12 is located, and a second gate insulating layer 17 is provided between the layer where the active layer 12 is located and the layer where the second gate electrode 112 is located; wherein, the first gates 111 in the pixel units in the same row are connected to form a first gate bar 100; the second gates 112 in the pixel units in the same row are connected to form the first gate bar 100. A second via hole 50 penetrating through the first gate insulating layer 16 is formed between any two adjacent pixel units; the first gate 111 and the second gate bar 200 located in the same row of pixel units are electrically connected through the second via hole 50. The second via hole 50 penetrating the first gate insulating layer 16 is provided between any two adjacent pixel cells, so as to ensure that the first gate bar 100 and the second gate bar 200 are electrically connected well, so that the input of the scanning signal is the same as the input of the electrical signal on the first gate bar 100 and the second gate bar 200. Meanwhile, in the embodiment of the present disclosure, since the second via hole 50 and the first via hole 40 electrically connecting the first gate 111 and the second gate 112 both penetrate the first gate insulating layer 16, the first via hole 40 and the second via hole 50 can be formed in the same patterning process, which does not increase the number of process steps.

Of course, the second via holes 50 penetrating through the first gate insulating layer 16 and the second gate insulating layer 17 may be formed only at two ends of the first gate bar 100 and the second gate bar 200, so that the first gate 111 and the second gate bar 200 are electrically connected, and at this time, the gate scan signal may be introduced from two ends of the first gate bar 100 and the second gate bar 200, which may complete the electrical connection of the first gate bar and the second gate bar 200 through fewer via holes, thereby contributing to enhancing the toughness of the substrate.

In some embodiments, as shown in fig. 9, for the thin film transistor in each pixel unit, a connection portion 30 is provided on one of the first gate electrode 111 and the second gate electrode 112, and a first via 40 penetrating through the first gate insulating layer 16 and the second gate insulating layer 17 electrically connects the first gate electrode 111 and the second gate electrode 112 through the first connection portion 30. In the embodiment of the present disclosure, the connection portion 30 is disposed on the first gate 111 of one of the thin film transistors in any two adjacent pixel units in the same row, and the connection portion 30 is disposed on the second gate 112 of the other one of the thin film transistors, so that the scan signals input on the first gate 111 and the second gate 112 in the same row are kept the same. Of course, it is also possible to use the connection portion 30 on the first gate 111 in all the pixel units in the same row, and use the connection portion 30 on the second gate 112 in all the pixels in the adjacent row, which are within the scope of the embodiments of the present disclosure.

In addition, the connection portions 30 in any two adjacent pixel units in the row direction are located at different sides in the column direction of the pixel unit where each is located, for example: the connecting portion 30 of one pixel unit is located at the left side of the pixel unit, and the connecting portion 30 of the adjacent pixel unit is located at the right side of the pixel unit. Of course, it is also possible that the connection portions 30 in the respective pixel units are located on the same side of the respective pixel units, and all of them are within the protection scope of the embodiments of the present disclosure.

In the embodiment of the present disclosure, fig. 11 is a schematic view of a display substrate according to the embodiment of the present disclosure, and as shown in fig. 11, a pixel electrode 22 and a common electrode 24 are further disposed in each pixel unit on the display substrate; in some embodiments, a planarization layer 21 is disposed on a side of the thin film transistor where the drain electrode 14 is located, the side being away from the substrate 10, a third via hole is formed in the planarization layer 21 at a position corresponding to the drain electrode 14, and the pixel electrode 22 is formed on a side of the planarization layer 21, the side being away from the substrate 10, and is connected to the drain electrode 14 of the thin film transistor through the third via hole; a third interlayer insulating layer 23 is arranged on the side of the layer where the pixel electrode 22 is arranged and away from the substrate 10; a common electrode 24 may also be provided on the side of the third interlayer insulating layer 23 facing away from the substrate 10. The pixel electrode 22 is a plate electrode, and the common electrode 24 is a slit electrode. Of course, when both the pixel electrode 22 and the common electrode 24 are provided on the display substrate, both may be slit electrodes. When the pixel electrode 22 and the common electrode 24 are both slit electrodes, they may be disposed in the same layer, or may be disposed in layers, as long as they are alternately disposed. In the embodiment of the present disclosure, the common electrode 24 may not be disposed on the display substrate, or may be disposed on an opposite casing substrate, where the opposite casing substrate in the embodiment of the present disclosure includes, but is not limited to, a color film substrate.

In a third aspect, an embodiment of the present disclosure provides a display device, which includes the display substrate described above. The display device in the disclosed embodiments includes, but is not limited to, a VR display device. The thin film transistor in the display panel of the display device adopts the thin film transistor, so that the leakage current is small and the display effect is better.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.