阅读说明：本技术 一种复合结构的垂直氧化镓异质结二极管及其制作方法 (Vertical gallium oxide heterojunction diode with composite structure and manufacturing method thereof ) 是由 周弘 董鹏飞 张进成 刘志宏 郝跃 于 2021-09-28 设计创作，主要内容包括：本发明公开了一种复合结构垂直氧化镓异质结二极管,主要解决现有氧化镓导热性差、击穿电压高,且与低电阻不可兼得的问题。其自下而上包括阴极电极、n-Ga-(2)O-(3)衬底层、n-Ga-(2)O-(3)外延层、边缘终端、p-NiO-(x)低掺层、p-NiO-(x)高掺层、阳极电极、场板介质和场板金属。该n-Ga-(2)O-(3)衬底层减薄至原来的二分之一厚度；该p-NiO-(x)低掺层的掺杂浓度为1×10～(17)cm～(-3)-9×10～(18)cm～(-3),厚度为200nm-400nm；该p-NiO-(x)高掺层的掺杂浓度1×10～(19)cm～(-3)-9×10～(19)cm～(-3),厚度为100nm-200nm。本发明提高了击穿电压,减小了反向漏电,提升了开关比,可用于制备大功率集成电路。(The invention discloses a vertical gallium oxide heterojunction diode with a composite structure, which mainly solves the problems that the existing gallium oxide has poor thermal conductivity and high breakdown voltage, and cannot be compatible with low resistance. Which comprises a cathode electrode and n-Ga from bottom to top 2 O 3 Substrate layer, n-Ga 2 O 3 Epitaxial layer, edge termination, p-NiO x Low doped layer, p-NiO x A highly doped layer, an anode electrode, a field plate dielectric and a field plate metal. The n-Ga 2 O 3 The substrate layer is thinned to half of the original thickness; the p-NiO x Low doped layerHas a doping concentration of 1X 10 17 cm ‑3 ‑9×10 18 cm ‑3 The thickness is 200nm-400 nm; the p-NiO x The doping concentration of the high-doped layer is 1 multiplied by 10 19 cm ‑3 ‑9×10 19 cm ‑3 The thickness is 100nm-200 nm. The invention improves breakdown voltage, reduces reverse leakage, improves switching ratio, and can be used for preparing high-power integrated circuits.)

1. A vertical gallium oxide heterojunction diode with a composite structure comprises from bottom to top: cathode electrode (1), n-Ga₂O₃Substrate layer (2), n-Ga₂O₃Epitaxial layer (3), edge terminal (4), p-NiO_xLow doped layer (5), p-NiO_xHigh doped layer (6) and anode electrode (7), its characterized in that:

the n-Ga₂O₃The substrate layer (2) is thinned to the thickness of 10nm-600um so as to increase the heat conduction capability of the substrate layer;

the p-NiO_xA low doped layer (5) with a doping concentration N_A1＝1×10¹⁷cm^-3-9×10¹⁸cm^-3The thickness is 200nm-400 nm;

the p-NiO_xA highly doped layer (6) with a doping concentration N_A2＝1×10¹⁹cm^-3-9×10¹⁹cm^-3The thickness is 100nm-200 nm;

and a field plate structure which is vertically distributed by a field plate medium (8) and a field plate metal (9) is arranged on the anode electrode (7) so as to enhance the voltage endurance capability of the device.

2. The diode according to claim 1, wherein the cathode electrode (1) is made of Ti with a thickness of 20nm-100nm and Au with a thickness of 100nm-400 nm.

3. The diode of claim 1, wherein n-Ga₂O₃The thickness of the epitaxial layer (3) is 5-20um, and the doping concentration N_D＝5×10¹⁵cm^-3-5×10¹⁶cm^-3。

4. Diode according to claim 1, wherein the edge termination (4) is formed by Mg ion implantation with a concentration of 1 x 10 Mg ions implanted¹⁹cm^-3-1×10²⁰cm^-3The maximum depth of implantation is 200nm-700 nm.

5. The diode of claim 1, wherein:

the anode electrode (7) adopts Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-400 nm;

the field plate medium (8) adopts SiO with the thickness of 200-400nm₂；

The field plate metal (9) adopts Ni with the metal thickness of 20nm-100nm and Au with the metal thickness of 100nm-500 nm.

6. A manufacturing method of a vertical gallium oxide heterojunction diode with a composite structure is characterized by comprising the following steps:

1) selecting n-Ga having epitaxial layer and substrate layer₂O₃Epitaxial wafer, epitaxial layer doping concentration N_D＝5×10¹⁵cm^-3-5×10¹⁶cm^-3The thickness is 5-20um, the materials are sequentially put into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 5-10 min respectively, then are washed by a large amount of deionized water, and then are dried by nitrogen;

2) cleaning the n-Ga₂O₃n-Ga of epitaxial wafer₂O₃Thinning the substrate layer:

n-Ga is mixed with₂O₃Epitaxial layer spin coatingPhotoresist is used for soft baking to serve as a protective layer; then n-Ga is added₂O₃Adhering the epitaxial layer on the tray of thinning machine with paraffin, grinding to reduce thickness to 10nm-600um, and directly polishing with polishing machine to n-Ga₂O₃Polishing the substrate layer;

sequentially placing the thinned and polished sample wafer into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 5-10 min respectively, then flushing with deionized water, and then blowing with nitrogen for drying;

3) and (3) manufacturing a cathode electrode on the substrate layer of the cleaned n-Ga2O3 epitaxial wafer:

evaporation of E-Beam System at n-Ga by Electron Beam₂O₃Ti with the thickness of 20nm-100nm and Au with the thickness of 100nm-400nm are deposited on the substrate layer;

sequentially placing the sample wafer after metal deposition into acetone solution and anhydrous ethanol solution, ultrasonic cleaning for 5-10 min, washing with deionized water, blow-drying with nitrogen, and N₂In the environment, setting the annealing temperature in the furnace to be 420-500 ℃, and annealing for 30s-5min to form good ohmic contact;

4) manufacturing an edge terminal:

placing the annealed sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 5min-10min, then washing with a large amount of deionized water, and then drying with nitrogen;

firstly coating photoresist on the cleaned n-Ga2O3 epitaxial wafer outside the injection region₂O₃On the epitaxial layer, obtaining a region to be injected which is not protected by the photoresist through pre-baking, alignment, exposure, development and pattern detection;

adhering the sample cathode electrode on the tray of ion implanter with paraffin wax for Mg ion implantation to maximum depth of 200-700 nm and Mg ion concentration in the implanted area of 1 × 10¹⁹cm^-3-1×10²⁰cm^-3Forming an edge termination, the implanted region being annular and having a central region of unimplanted n-Ga₂O₃An epitaxial layer;

5) growing p-NiO_x：

Placing the injected sample wafer into acetone, heating in water bath at 55-65 deg.C for 20min, sequentially placing into acetone solution and anhydrous ethanol solution, ultrasonic cleaning for 5-10 min, washing with deionized water, and blow-drying with nitrogen;

sputtering a layer of N with the doping concentration of 200nm-400nm in thickness by a magnetron sputtering method in sequence_A1＝1×10¹⁷cm^-3-9×10¹⁸cm^-3p-NiO of (2)_xAnd a layer with a thickness of 100nm-200nm and a doping concentration of N_A2＝1×10¹⁹cm^-3-9×10¹⁹cm^-3Highly doped p-NiO of_x；

6) High doped p-NiO in growth_xCarrying out photoetching to form an anode region, depositing Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-400nm in the anode region by an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form a circular anode electrode;

7) placing the stripped sample wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water in sequence, respectively ultrasonically cleaning for 5-10 min, and drying by using nitrogen;

8) growing a layer of SiO with the thickness of 200nm-400nm on one surface of the sample wafer anode by using PECVD equipment₂As a field plate dielectric;

9) etching a circular through hole on a plate medium of the field above the anode:

SiO will grow₂Sequentially placing the sample wafer into acetone solution and absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5min-10min, washing with a large amount of deionized water, and blow-drying with nitrogen;

coating photoresist on SiO to be etched₂On the layer, obtaining an opening area to be etched which is not protected by the photoresist through pre-baking, alignment, exposure, development and pattern detection;

etching SiO on the anode by RIE etching machine₂Etching to expose the anode metal, wherein the area of the opening is smaller than that of the anode electrode, so that the edge of the anode metal is still SiO₂The following steps of (1);

placing the etched and perforated sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 5min-10min, then flushing with a large amount of deionized water, and then blow-drying with nitrogen;

10) growing field plate metal:

photoetching one side of the sample wafer with the opening to form a field plate metal area, enabling the field plate metal area to be larger than the area of an anode electrode, enabling the field plate metal edge to be arranged on the outer side of the anode metal edge and surrounding the anode metal edge, depositing Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-500nm in the opening area through an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form a field plate structure;

and sequentially placing the sample wafer with the field plate structure into an acetone solution and an absolute ethyl alcohol solution, respectively carrying out ultrasonic cleaning for 5-10 min, then washing with deionized water, and then blowing with nitrogen to dry to finish the device manufacturing.

7. The method of claim 6, wherein the low temperature deposition equipment ICP-CVD used in 5) is used for depositing the p-NiO film, and the process conditions are as follows:

reaction chamber pressure: 10-15mTorr

Ionization voltage: 1.8-4.5KV

Plasma ionization electrode: ni

Reaction chamber gas: o is₂、N₂、Ar。

8. The method of claim 6, wherein the SiO is grown by PECVD in 8)₂The process conditions are as follows:

reaction chamber pressure: 1500mTorr-2500mTorr

Reaction chamber gas: SiH₄、N₂O、N₂

Reaction chamber gas flow rate ratio: SiH₄:N₂O:N₂＝4-8sccm:710-1500sccm:180-400sccm

Temperature: 300-350 deg.C

RF power: 15W-30W.

9. The method of claim 6, wherein RIE is used in 9) to etch SiO₂The process conditions are as follows:

reaction chamber pressure: 1600mTorr-2000mTorr

Reaction chamber gas: SF₆、CHF₃、He

Reaction chamber gas flow rate ratio: SF₆:CHF₃:He＝5.5-10sccm:32-70sccm:150-300sccm

RF power: 100W-300W.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a vertical gallium oxide heterojunction diode with a composite structure, which can be used for manufacturing a high-power integrated circuit.

Technical Field

Gallium oxide has five crystal forms of alpha, beta, gamma, delta and epsilon, wherein monoclinic beta-Ga₂O₃Has the best thermal stability, and other metastable phases are easy to be converted into beta-Ga at high temperature₂O₃Therefore, most studies are now around β -Ga₂O₃And (4) unfolding. beta-Ga₂O₃The silicon nitride has an ultra-large forbidden band width (4.4-4.9eV), and the ionization rate is low, so that the breakdown field strength is high, about 8MV/cm, which is more than 20 times that of Si and more than twice that of SiC and GaN. Furthermore, beta-Ga₂O₃The quality factor of the GaN-based material is more than 8 times that of 4H-SiC and more than 4 times that of GaN; the optimum value of high frequency Baliga is 150 times that of Si, 3 times that of 4H-SiC and 1.5 times that of GaN. Since Ga is₂O₃The theoretical value of the on-resistance of the material is very low, so that under the same condition, Ga is used₂O₃The conduction loss of the unipolar device made of the material is at least one order of magnitude lower than that of SiC and GaN devices, which is beneficial to improving the efficiency of the device.

Analysis in general, beta-Ga₂O₃Is a power semiconductor material with great development prospect and is based on beta-Ga₂O₃The power semiconductor device has great potential in high-frequency, high-voltage and high-power application.

Ideal n-type and p-type semiconductors are the premise and the basis for preparing high-quality semiconductor devices, and Varley et al experimentally confirm that due to different growth environments, atoms of Si, Ge, Sn, F, Cl and the like are easily introduced in the growth process of gallium oxide, and the atoms can make the gallium oxide show n-type conductivity. At present, beta-Ga₂O₃Effective n-type doping can be realized only, n-type doping elements with good doping effect are Si and Sn, and the regulation and control of n-type gallium oxide crystal carriers in a larger range can be realized by doping Si and Sn. Compared with the n-type doping of gallium oxide crystals, the p-type doping is difficult to realize, and especially the p-type doping with higher carrier concentration is difficult to realize. The reasons for the difficulty in obtaining effective p-type doping are mainly: the influence of n-type background carriers; lack of effective shallow level acceptor impurities; acceptor impurity ions are easy to passivate, the activation rate is low, and the self-defect effect exists. Therefore, research on gallium oxide-based devices has also focused primarily on n-type β -Ga₂O₃The research results of the substrate device on p-type conductive single crystals, thin films and p-type channel devices are few, and the development and application of the gallium oxide substrate device are restricted due to the lack of p-type doping and poor thermal conductivity.

Disclosure of Invention

The invention aims to provide a method based on p-NiO aiming at overcoming the defects of the prior art_xAnd n-type Ga₂O₃A vertical gallium oxide heterojunction diode with a composite structure for forming heterojunction to improve breakdown voltage of the device, reduce on-resistance, and improve Ga₂O₃The heat conductivity effectively improves the performance of the device.

The technical idea of the invention is as follows: the gallium oxide substrate layer is thinned by using a thinning machine, the interface is processed by using a polishing machine, the heat conduction capability of the device is improved, the on-resistance is reduced, Mg ion injection is adopted as an edge terminal, and Ga is subjected to ion implantation₂O₃Growing a layer of low-doped p-NiO on the epitaxial layer_xThen a layer of highly doped p-NiO is grown_xUsing a double layer of p-NiO_xTo weaken Ga at the junction₂O₃Electric field intensity, and the Ga at the junction is further weakened by matching with the field plate structure₂O₃The electric field intensity improves the breakdown voltage of the device. Since Ga is₂O₃And NiO_xAll have high doped layers, so the on-resistance can be further reduced due to the conductivity modulation effect.

According to the above thought, the technical scheme of the invention is as follows:

1. vertical gallium oxide heterojunction diode with composite structure from bottomAnd the method comprises the following steps: cathode electrode, n-Ga₂O₃Substrate layer, n-Ga₂O₃Epitaxial layer, edge termination, p-NiO_xLow doped layer, p-NiO_xHigh doped layer and positive pole electrode, its characterized in that:

the n-Ga₂O₃The substrate layer is thinned to be 10nm-600um in thickness so as to increase the heat conduction capability of the substrate layer;

the p-NiO_xLow doped layer, doping concentration N_A1＝1×10¹⁷cm^-3-9×10¹⁸cm^-3The thickness is 200nm-400 nm;

the p-NiO_xHighly doped layer, doping concentration N_A2＝1×10¹⁹cm^-3-9×10¹⁹cm^-3The thickness is 100nm-200 nm;

and the anode electrode is provided with a field plate structure which is vertically distributed by a field plate medium and field plate metal so as to enhance the voltage resistance of the device.

Furthermore, the cathode electrode adopts Ti with the thickness of 20nm-100nm and Au with the thickness of 100nm-400 nm.

Further, the n-Ga₂O₃Epitaxial layer with thickness of 5-20um and doping concentration N_D＝5×10¹⁵cm^-3-5×10¹⁶cm^-3。

Further, the edge terminal is formed by Mg ion implantation with an implanted Mg ion concentration of 1 × 10¹⁹cm^-3-1×10²⁰cm^-3The maximum depth of implantation is 200nm-700 nm.

Furthermore, the anode electrode adopts Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-400 nm.

Furthermore, the field plate medium adopts SiO with the thickness of 200-400nm₂。

Furthermore, the field plate metal adopts Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-500 nm.

2. A manufacturing method of a vertical gallium oxide heterojunction diode with a composite structure is characterized by comprising the following steps:

1) selecting n-Ga having epitaxial layer and substrate layer₂O₃Epitaxial wafer, epitaxial layer doping concentration N_D＝5×10¹⁵cm^-3-5×10¹⁶cm^-3The thickness is 5-20um, the materials are sequentially put into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 5-10 min respectively, then are washed by a large amount of deionized water, and then are dried by nitrogen;

2) cleaning the n-Ga₂O₃n-Ga of epitaxial wafer₂O₃Thinning the substrate layer:

n-Ga is mixed with₂O₃Spin-coating photoresist on the epitaxial layer, and soft-baking to obtain a protective layer; then n-Ga is added₂O₃Adhering the epitaxial layer on the tray of thinning machine with paraffin, grinding to reduce thickness to 10nm-600um, and directly polishing with polishing machine to n-Ga₂O₃Polishing the substrate layer;

sequentially placing the thinned and polished sample wafer into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 5-10 min respectively, then flushing with deionized water, and then blowing with nitrogen for drying;

3) and (3) manufacturing a cathode electrode on the substrate layer of the cleaned n-Ga2O3 epitaxial wafer:

evaporation of E-Beam System at n-Ga by Electron Beam₂O₃Ti with the thickness of 20nm-100nm and Au with the thickness of 100nm-400nm are deposited on the substrate layer;

sequentially placing the sample wafer after metal deposition into acetone solution and anhydrous ethanol solution, ultrasonic cleaning for 5-10 min, washing with deionized water, blow-drying with nitrogen, and N₂In the environment, setting the annealing temperature in the furnace to be 420-500 ℃, and annealing for 30s-5min to form good ohmic contact;

4) manufacturing an edge terminal:

placing the annealed sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 5min-10min, then washing with a large amount of deionized water, and then drying with nitrogen;

firstly coating photoresist on the cleaned n-Ga2O3 epitaxial wafer outside the injection region₂O₃On the epitaxial layer, obtaining the photoresist unprotected photoresist by prebaking, aligning, exposing, developing and detecting the patternA region to be implanted;

adhering the sample cathode electrode on the tray of ion implanter with paraffin wax for Mg ion implantation to maximum depth of 200-700 nm and Mg ion concentration in the implanted area of 1 × 10¹⁹cm^-3-1×10²⁰cm^-3Forming an edge termination, the implanted region being annular and having a central region of unimplanted n-Ga₂O₃An epitaxial layer;

5) growing p-NiO_x：

Placing the injected sample wafer into acetone, heating in water bath at 55-65 deg.C for 20min, sequentially placing into acetone solution and anhydrous ethanol solution, ultrasonic cleaning for 5-10 min, washing with deionized water, and blow-drying with nitrogen;

sputtering a layer of N with the doping concentration of 200nm-400nm in thickness by a magnetron sputtering method in sequence_A1＝1×10¹⁷cm^-3-9×10¹⁸cm^-3p-NiO of (2)_xAnd a layer with a thickness of 100nm-200nm and a doping concentration of N_A2＝1×10¹⁹cm^-3-9×10¹⁹cm^-3Highly doped p-NiO of_x；

6) High doped p-NiO in growth_xCarrying out photoetching to form an anode region, depositing Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-400nm in the anode region by an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form a circular anode electrode;

7) placing the stripped sample wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water in sequence, respectively ultrasonically cleaning for 5-10 min, and drying by using nitrogen;

8) growing a layer of SiO with the thickness of 200nm-400nm on one surface of the sample wafer anode by using PECVD equipment₂As a field plate dielectric;

9) etching a circular through hole on a plate medium of the field above the anode:

SiO will grow₂Sequentially placing the sample wafer into acetone solution and absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5min-10min, washing with a large amount of deionized water, and blow-drying with nitrogen;

coating photoresist on the substrate to be etchedSiO₂On the layer, obtaining an opening area to be etched which is not protected by the photoresist through pre-baking, alignment, exposure, development and pattern detection;

etching SiO on the anode by RIE etching machine₂Etching to expose the anode metal, wherein the area of the opening is smaller than that of the anode electrode, so that the edge of the anode metal is still SiO₂The following steps of (1);

placing the etched and perforated sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 5min-10min, then flushing with a large amount of deionized water, and then blow-drying with nitrogen;

10) growing field plate metal:

photoetching one side of the sample wafer with the opening to form a field plate metal area, enabling the field plate metal area to be larger than the area of an anode electrode, enabling the field plate metal edge to be arranged on the outer side of the anode metal edge and surrounding the anode metal edge, depositing Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-500nm in the opening area through an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form a field plate structure;

and sequentially placing the sample wafer with the field plate structure into an acetone solution and an absolute ethyl alcohol solution, respectively carrying out ultrasonic cleaning for 5-10 min, then washing with deionized water, and then blowing with nitrogen to dry to finish the device manufacturing.

The invention has the following advantages:

1. the invention is characterized in that n-Ga₂O₃The substrate layer is thinned to ensure that the n-Ga₂O₃The total thickness is thinner, and the heat dissipation capability of the sample wafer is effectively enhanced.

2. The invention effectively reduces the peak electric field at the junction and increases the breakdown voltage of the device by combining the field plate structure with the double-layer p-type layer.

3. The invention is due to the fact that in n-Ga₂O₃The epitaxial layer adopts an ion implantation technology as an edge terminal, so that reverse electric leakage is reduced, breakdown voltage is further increased, and the on-off ratio is improved.

4. According to the invention, the gold half-contact adopts the high-doping semiconductor layer, so that good ohmic contact is formed, and the power consumption of the device is reduced.

5. In the invention, the electrodes are all high doped layers, so that the on-resistance can be further reduced by utilizing the conductance modulation effect.

Drawings

FIG. 1 is a block diagram of a composite structure vertical gallium oxide heterojunction diode of the present invention;

FIG. 2 is a top view of FIG. 1;

FIG. 3 is a schematic view of the process for preparing a vertical gallium oxide heterojunction diode with a composite structure according to the present invention.

Detailed Description

Embodiments of the composite-structure vertical gallium oxide heterojunction diode of the present invention are described in further detail below with reference to the accompanying drawings.

Referring to fig. 1 and 2, the vertical gallium oxide heterojunction diode with a composite structure of the invention comprises a cathode electrode 1 and n-Ga₂O₃Substrate layer 2, n-Ga₂O₃Epitaxial layer 3, edge termination 4, p-NiO_xLow doped layer 5, p-NiO_xHigh doped layer 6, anode electrode 7, field plate dielectric 8, field plate metal 9. Wherein, the cathode electrode 1 is positioned at the bottommost part of the device and adopts Ti with the thickness of 20nm-100nm and Au with the thickness of 100nm-400 nm; n-Ga₂O₃The substrate layer 2 is positioned on the cathode electrode 1, and ohmic contact is formed between the substrate layer and the cathode electrode; n-Ga₂O₃Epitaxial layer 3 is located on n-Ga₂O₃On the substrate 2; edge termination 4 at n-Ga₂O₃Inside the epitaxial layer 3, the shape is annular, and the center of the epitaxial layer is non-implanted n-Ga₂O₃An epitaxial layer with a depth of 200nm-700 nm; p-NiO_xThe low doped layer 5 is positioned on the n-Ga₂O₃On the epitaxial layer 3; p-NiO_xThe high doped layer 6 is positioned in the p-NiO_xA low doped layer 5; the anode electrode 7 adopts 20nm-100nm of Ni and 100nm-400nm of Au, which are positioned in p-NiO_xOhmic contact is formed on the high-doped layer 6; the anode electrode 7 is vertically positioned right above the edge terminal 4 and has an area larger than n-Ga in the center of the edge terminal 4₂O₃The electrode edge is above the edge termination 4; the field plate medium 8 is SiO with the thickness of 200nm-400nm₂Covering the anode metal 7 and p-NiO_xA highly doped layer 6; is located atSiO over anode metal 7₂A circular through hole is formed so that the metal is exposed on the surface, and the area of the through hole is smaller than that of the anode metal 7 so that the through hole can be surrounded by the edge of the anode metal 7; the field plate metal 9 is made of Ni with the thickness of 20nm-100nm and Au with the thickness of 100nm-500nm, is positioned on the field plate medium 8, is connected with the anode metal 7 through a through hole of the field plate medium 8, and has the area larger than that of the anode metal 7, so that the metal edge of the field plate metal 9 can surround the anode metal 7.

Referring to fig. 2, the present invention provides the following three examples of fabricating a vertical gallium oxide heterojunction diode with a composite structure:

example 1, a thickness of 300um was made thinner, a thickness of 300nm and a concentration of N_A1＝1×10¹⁸cm^-3p-NiO of (2)_xA low doped layer with a thickness of 100nm and a doping concentration of N_A2＝1×10¹⁹cm^-3p-NiO of (2)_xA high doped layer with a gallium oxide epitaxial layer thickness of 10um and a doping concentration of N_D＝6×10¹⁵cm^-3And the anode metal radius is a gallium oxide heterojunction transistor of 75 um.

Step 1, cleaning the epitaxial wafer, as shown in fig. 3 (a).

And selecting a gallium oxide homoepitaxial wafer, sequentially putting the gallium oxide homoepitaxial wafer into an acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5min, washing with deionized water, and then drying with nitrogen.

And 2, thinning the substrate layer of the cleaned n-Ga2O3 epitaxial wafer, as shown in FIG. 3 (b).

n-Ga is mixed with₂O₃And spin-coating photoresist on the epitaxial layer, and soft-baking to obtain a protective layer. Then n-Ga is added₂O₃Adhering the epitaxial layer on the tray of thinning machine with paraffin wax, grinding to thin to 300um, and directly polishing with polishing machine to n-Ga₂O₃Polishing the substrate layer;

and sequentially putting the thinned and polished sample wafer into an acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 5min, then flushing with deionized water, and then drying with nitrogen.

Step 3, in n-Ga₂O₃A cathode electrode is formed on the substrate of the homoepitaxial wafer, as shown in fig. 3 (c).

Depositing Ti/Au with the thickness of 60nm/120nm on the substrate layer of the cleaned n-Ga2O3 epitaxial wafer by an electron Beam evaporation E-Beam system;

sequentially placing the sample wafer after metal deposition into acetone solution and absolute ethyl alcohol solution, respectively ultrasonically cleaning for 8min, washing with deionized water, blow-drying with nitrogen, and then N₂In the environment, the annealing temperature in the furnace is set to 475 ℃, and annealing is carried out for 1min to form good ohmic contact.

And 4, photoetching to obtain a region to be implanted which is not protected by the photoresist, as shown in fig. 3 (d).

Step 5, making an edge terminal, as shown in fig. 3 (e).

Performing Mg ion implantation on the region to be implanted formed after the completion of the photoetching, wherein the implantation depth is 500nm, and the Mg ion concentration is 5 multiplied by 10¹⁹cm^-3And then placing the sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 8min, washing with deionized water, and drying with nitrogen.

Step 6, sputtering double-layer p-NiO_xAs shown in fig. 3 (f).

Sequentially placing the injected sample wafer into an acetone solution, heating in a water bath at 60 ℃ for 20min, sequentially placing the sample wafer into the acetone solution and the absolute ethyl alcohol solution, respectively ultrasonically cleaning for 8min, washing with deionized water, and then drying with nitrogen;

then magnetron sputtering is carried out on the n-Ga with the edge terminal₂O₃A layer with the thickness of 300nm and the concentration of N is grown on the epitaxial layer_A＝1×10¹⁸cm^-3p-NiO of (2)_xA low-doped layer;

in p-NiO_xSputtering a layer with the thickness of 100nm and the doping concentration of N on the low-doped layer_A＝1×10¹⁹cm^-3p-NiO of (2)_xAnd (4) a high-doping layer.

Step 7, make anode and wash, as in fig. 3 (g).

In the presence of high NiO doping_xCarrying out photoetching on the layer with the radius of 75um to form an anode region, depositing Ni/Au with the thickness of 60nm/120nm in the anode region by an electron Beam evaporation E-Beam system, and depositing metalThe sample wafer is put into acetone solution for stripping to form an anode electrode;

and (3) sequentially putting the stripped sample wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 8min, and drying by using nitrogen.

And 8, manufacturing a field plate to finish the manufacture of the device.

Growing SiO with thickness of 300nm by PECVD equipment₂As field plate medium, covering NiO_xAnd anode metal, as in fig. 3 (h);

in SiO₂Performing photoetching, forming holes above the anode metal, and forming SiO above the anode metal₂Etching away by using RIE etching machine to expose the anode metal under the small hole with radius of 55um, and surrounding the edge of the small hole by the anode metal edge to form the field plate dielectric through hole, as shown in figure 3 (i).

SiO in the opening₂Photoetching the layer with the radius of 95um to form a field plate metal area, depositing Ni/Au with the thickness of 100nm/300nm on the anode area by an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into acetone solution for stripping to form field plate metal, as shown in figure 3 (j);

and (3) sequentially putting the stripped sample wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 5min, and blow-drying by using nitrogen to finish the manufacture of the device.

Example 2 preparation of P-NiO with a reduced thickness of 350um and a thickness of 200nm_xLow doped layer of N concentration_A1＝2×10¹⁸cm^-380nm doping concentration of N_A2＝2×10¹⁹cm^-3p-NiO of (2)_xHigh doped layer with gallium oxide epitaxial layer thickness of 7.5um and doping concentration N_D＝7×10¹⁵cm^-3And an anode metal of gallium oxide heterojunction transistor with a radius of 50 um.

Step one, the epitaxial wafer is cleaned, as shown in fig. 3 (a).

The specific implementation of this step is the same as step 1 of example 1.

And step two, thinning the substrate layer of the cleaned n-Ga2O3 epitaxial wafer, as shown in figure 3 (b).

2.1) reacting n-Ga₂O₃Spin-coating photoresist on the epitaxial layer, soft baking to obtain a protective layer, and coating n-Ga₂O₃Adhering the epitaxial layer on the tray of thinning machine with paraffin, grinding to thin to 350um, and directly polishing n-Ga with polishing machine₂O₃Polishing the substrate layer;

2.2) putting the thinned and polished sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 5min, then flushing with deionized water, and then blowing with nitrogen.

Step three, in n-Ga₂O₃A cathode electrode is formed on the substrate of the homoepitaxial wafer, as shown in fig. 3 (c).

3.1) depositing Ti/Au with the thickness of 50nm/100nm on the substrate layer of the cleaned n-Ga2O3 epitaxial wafer by an electron Beam evaporation E-Beam system;

3.2) putting the sample wafer after the metal deposition into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 7min, then flushing with deionized water, and then drying with nitrogen; then N is added₂In the environment, the annealing temperature in the furnace is set to be 465 ℃, and annealing is carried out for 2min to form good ohmic contact.

And step four, manufacturing an edge terminal.

4.1) photoetching to obtain a region to be implanted which is not protected by the photoresist, as shown in figure 3 (d).

4.2) carrying out Mg ion implantation on the region to be implanted formed after the completion of the photoetching, wherein the implantation depth is 600nm, and the Mg ion concentration is 6 multiplied by 10¹⁹cm^-3And forming an edge terminal, then placing the sample wafer into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 10min, washing with deionized water, and blow-drying with nitrogen, as shown in figure 3 (e).

Step five, sputtering double-layer p-NiO_xAs shown in fig. 3 (f).

5.1) sequentially putting the injected sample wafer into an acetone solution, heating in a water bath at 65 ℃ for 25min, sequentially putting the sample wafer into the acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 8min, washing with deionized water, and then drying with nitrogen;

5.2) magnetron sputtering of n-Ga having edge terminations₂O₃Growth on epitaxial layerA long layer with the thickness of 200nm and the concentration of N_A1＝2×10¹⁸cm^-3p-NiO of (2)_xA low-doped layer;

5.3) in p-NiO_xSputtering a layer with the thickness of 80nm and the doping concentration of N on the low-doped layer_A2＝2×10¹⁹cm^-3p-NiO of (2)_xAnd (4) a high-doping layer.

And step six, manufacturing an anode and cleaning, as shown in figure 3 (g).

6.1) high NiO doping_xPhotoetching the layer to form an anode area, wherein the etched radius is 50um, depositing Ni/Au with the thickness of 50nm/100nm in the anode area by an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form an anode electrode;

6.2) putting the sample wafer forming the anode electrode into an acetone solution, an absolute ethyl alcohol solution and deionized water in sequence, respectively ultrasonically cleaning for 5min, and drying by using nitrogen.

And seventhly, manufacturing a field plate to finish the manufacture of the device.

7.1) growing SiO with a thickness of 350nm by using PECVD equipment₂As field plate medium, covering NiO_xAnd anode metal, as in fig. 3 (h);

7.2) on SiO₂Through holes are formed thereon, as shown in fig. 3 (i).

In SiO₂Performing photoetching, forming holes above the anode metal, and forming SiO above the anode metal₂Etching by using an RIE etching machine to expose the anode metal below the small hole with the radius of 35um, wherein the edge of the small hole is surrounded by the edge of the anode metal to form a field plate medium through hole;

7.3) making field plate metal to complete the device fabrication, as shown in FIG. 3(j)

SiO in the opening₂And photoetching the layer to form a field plate metal area, wherein the photoetching radius is 65um, depositing Ni/Au with the thickness of 90nm/400nm on the anode area by an electron Beam evaporation E-Beam system, and putting a sample wafer after metal deposition into acetone solution for stripping to form field plate metal.

And 7.4) sequentially putting the stripped sample wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 8min, and blow-drying by using nitrogen to finish the manufacture of the device.

Example 3 production of p-NiO with a reduced thickness of 400um and a thickness of 260nm_xLow doped layer of N concentration_A1＝1×10¹⁷cm^-3120nm doping concentration of N_A2＝5×10¹⁹cm^-3p-NiO of (2)_xHigh doped layer with gallium oxide epitaxial layer thickness of 5um and doping concentration N_D＝1×10¹⁶cm^-3And the anode metal radius is 100 um.

Step A, cleaning the epitaxial wafer, as shown in FIG. 3 (a).

The specific implementation of this step is the same as step 1 of example 1.

Step B, cleaning the back n-Ga of the n-Ga2O3 epitaxial wafer₂O₃The substrate layer is subjected to a thinning process, as shown in fig. 3 (b).

n-Ga is mixed with₂O₃And spin-coating photoresist on the epitaxial layer, and soft-baking to obtain a protective layer. Then n-Ga is added₂O₃Adhering the epitaxial layer on the tray of thinning machine with paraffin wax, grinding to thin to 400um, and directly polishing with polishing machine to n-Ga₂O₃Polishing the substrate layer;

and sequentially putting the thinned and polished sample wafer into an acetone solution and an absolute ethyl alcohol solution, respectively ultrasonically cleaning for 10min, then flushing with deionized water, and then drying with nitrogen.

Step C in n-Ga₂O₃A cathode electrode is formed on the substrate of the homoepitaxial wafer, as shown in fig. 3 (c).

Firstly, extending the back n-Ga of the wafer on n-Ga2O3 by an E-Beam evaporation system₂O₃Ti/Au with the thickness of 30nm/120nm is deposited on the substrate layer; then placing the sample wafer after the metal deposition into an acetone solution and an absolute ethyl alcohol solution in sequence, respectively ultrasonically cleaning for 10min, washing with deionized water, and drying with nitrogen; then N in the furnace at 480 DEG C₂Annealing is carried out for 2min in the environment, and good ohmic contact is formed.

Step D, manufacturing an edge terminal

First, the area to be implanted is obtained by photolithography, which is not protected by the photoresist, as shown in FIG. 3(d)) (ii) a Then, the depth of the region to be implanted formed after the completion of the photoetching is 400nm, and the concentration is 2 multiplied by 10¹⁹cm^-3Forming an edge termination by Mg ion implantation, as shown in fig. 3 (e); and then the sample is sequentially placed into an acetone solution and an absolute ethyl alcohol solution for ultrasonic cleaning for 10min respectively, and is respectively washed and dried by deionized water and nitrogen.

Step E, sputtering double-layer p-NiO_xAs shown in fig. 3 (f).

Sequentially placing the injected sample wafer into acetone solution, and maintaining the water bath temperature of 55 deg.C for 20 min; then sequentially putting the mixture into acetone solution and absolute ethyl alcohol solution for ultrasonic cleaning for 10min, flushing with deionized water and drying with nitrogen; then magnetron sputtering is carried out on the n-Ga with the edge terminal₂O₃A layer with the thickness of 260nm and the concentration of N is grown on the epitaxial layer_A1＝1×10¹⁷cm^-3p-NiO of (2)_xA low-doped layer;

in p-NiO_xSputtering a layer with the thickness of 120nm and the doping concentration of N on the low-doped layer_A2＝5×10¹⁹cm^-3p-NiO of (2)_xAnd (4) a high-doping layer.

Step F, making an anode and cleaning, as shown in FIG. 3 (g).

In the presence of high NiO doping_xPhotoetching an anode area with the radius of 100um on the layer, depositing Ni/Au with the thickness of 30nm/120nm on the anode area through an electron Beam evaporation E-Beam system, and putting a sample wafer after metal deposition into an acetone solution for stripping to form an anode electrode; then the mixture is sequentially put into acetone solution, absolute ethyl alcohol solution and deionized water to be respectively ultrasonically cleaned for 10min, and the mixture is dried by nitrogen.

And G, manufacturing a field plate to finish the manufacture of the device.

Firstly, growing SiO with the thickness of 250nm by using PECVD equipment₂As field plate medium, covering NiO_xAnd anodic metal as in fig. 3 (h); then SiO₂Performing photoetching, forming holes above the anode metal, and forming SiO above the anode metal₂Etching by RIE etching machine to expose the anode metal under the small hole with radius of 90um, and surrounding the edge of the small hole with the anode metal edge to form field plate dielectric via hole, as shown in FIG. 3(i))；

Then SiO in the opening₂Photoetching the layer with the radius of 110um to form a field plate metal region; depositing Ni/Au with the thickness of 120nm/350nm in an anode region by an electron Beam evaporation E-Beam system, and putting the sample wafer after metal deposition into an acetone solution for stripping to form field plate metal as shown in figure 3 (j);

and finally, sequentially placing the silicon wafer into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively carrying out ultrasonic cleaning for 10min, and blowing the silicon wafer by using nitrogen to dry, thereby completing the manufacture of the device.

The foregoing is merely exemplary of the invention and is not to be construed as limiting the invention to the specific embodiments disclosed herein. It will be apparent to persons skilled in the relevant art that various modifications and changes in form and detail can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.