Gain programmable radio frequency amplifier
阅读说明：本技术 一种增益可编程的射频放大器 (Gain programmable radio frequency amplifier ) 是由 戴若凡 于 2021-09-29 设计创作，主要内容包括：本发明公开了一种增益可编程的射频放大器,包括：带隙基准,产生基准电流并输出至固定偏置电压电路；固定偏置电压电路,在基准电流的控制下产生电流电压可编程电路所需固定偏置电压；电流电压可编程电路,在n位增益控制信号的控制下将固定偏置电压转换为可编程偏置电流,并将固定偏置电压转换为第一可编程偏置电压；输入级偏置镜像模块,在电流电压可编程电路输出的可编程电流的控制下产生第二可编程偏置电压；输入级,在第二可编程偏置电压的控制下完成射频信号初步放大；输出级,在第一可编程偏置电压的控制下,将经输入级放大的射频信号进一步放大得到射频输出信号；低压差稳压电路,用于产生稳定电压供给输入级和输出级。(The invention discloses a gain programmable radio frequency amplifier, comprising: the band-gap reference generates reference current and outputs the reference current to the fixed bias voltage circuit; the fixed bias voltage circuit generates fixed bias voltage required by the current-voltage programmable circuit under the control of the reference current; the current-voltage programmable circuit is used for converting the fixed bias voltage into programmable bias current under the control of the n-bit gain control signal and converting the fixed bias voltage into first programmable bias voltage; the input stage bias mirror image module is used for generating a second programmable bias voltage under the control of the programmable current output by the current-voltage programmable circuit; the input stage finishes the preliminary amplification of the radio frequency signal under the control of a second programmable bias voltage; the output stage is used for further amplifying the radio-frequency signal amplified by the input stage under the control of the first programmable bias voltage to obtain a radio-frequency output signal; and the low dropout voltage stabilizing circuit is used for generating a stable voltage to supply the input stage and the output stage.)
1. A gain programmable radio frequency amplifier comprising:
a band-gap reference for generating a reference current (Iref) and outputting to the fixed bias voltage circuit;
a fixed bias voltage circuit for generating a fixed bias voltage (Vb) required by the current-voltage programmable circuit under control of the reference current (Iref);
current-voltage programmable circuit for controlling the gain of a signal (CT [1: n ]) in n bits]) Is converted into a programmable bias current (Ipc) and transmitted to the input of the input stage bias mirror module while at the same time controlling the gain of the n-bit gain control signal (CT [1: n ]) under control of]) Is controlled to convert said fixed bias voltage (Vb) into a first programmable bias voltage (Vpc) and to transfer it to the output stage to provide the bias voltage (Vg) required by the output stageMo)；
An input stage bias mirror module for generating a second programmable bias voltage (Vg) under control of a programmable current (Ipc) output by the current-voltage programmable circuitNin) And output to the input stage;
an input stage for applying a second programmable bias voltage (Vg)Nin) Under the control of (3) to complete a radio frequency signal (RF)in) Preliminary amplification of (1);
an output stage for amplifying a radio frequency signal (RF) amplified by the input stage under control of the first programmable bias voltage (Vpc)in) Further amplifying to obtain a radio frequency output signal (RF)out)；
And the low-dropout voltage stabilizing circuit is used for generating a stable voltage (Va) to supply the input stage and the output stage so as to obtain more stable gain control effect.
2. A gain programmable radio frequency amplifier as claimed in claim 1, characterized in that the current-voltage programmable circuit comprises a current programming circuit and a voltage programming circuit, the current programming circuit comprising n first programmable bias units (31i) each controlled by an n-bit gain control signal (CT [ i ]), i being 1, 2, … …, n, each first programmable bias unit outputting a sub-output bias current under control of the gain control signal (CT [ i ]) and a fixed bias voltage (Vb), the n sub-output bias currents being combined into the programmable bias current (Ipc) and being connected to the input of the input stage bias mirror module, the voltage programming circuit being adapted to generate the programmable bias voltage (Vpc) under control of the n-bit gain control signal (CT [1: n ]) and the fixed bias voltage (Vb), the programmable bias voltage (Vpc) is programmable by a k-bit second programmable bias unit (32j) and an (n-k) -bit programmable resistance adjustment ratio, where k is less than or equal to n.
3. A gain programmable radio frequency amplifier as in claim 2, wherein: each first programmable bias unit (31i) comprises a PMOS bias current input tube (P1i), an NMOS bias current input tube (N1i) and a PMOS bias current output tube (MP2i), a gain control signal CT [ i ] is connected to the grid of the PMOS bias current input tube (P1i) and the grid of the NMOS bias current input tube (N1i), the drain of the PMOS bias current input tube (P1i) and the drain of the NMOS bias current input tube (N1i) are connected to the grid of the PMOS bias current output tube (MP2i), the drains of the PMOS bias current output tubes (MP2i) are connected together to form the programmable bias current (Ipc) node, and the programmable bias current (Ipc) node is connected to the input stage bias mirror image module.
4. A gain programmable radio frequency amplifier as in claim 3, wherein: the width dimension of each PMOS bias current output tube (MP2i) has a different weight.
5. A gain programmable radio frequency amplifier as in claim 2, wherein: the voltage programming circuit comprises k second programmable bias units (32j), a fourth PMOS bias tube (MP4), a first programmable resistor (R1) and a second programmable resistor (R2), wherein j is 1, 2, … …, k, and k is less than or equal to N, each second programmable bias unit (32j) comprises a PMOS bias voltage input tube (P2j), an NMOS bias voltage input tube (N2j) and a PMOS bias voltage output tube (MP3j), a gain control signal CT [ j ] is connected to the grid of the PMOS bias voltage input tube (P2j) and the grid of the NMOS bias voltage input tube (N2j), the drain of the PMOS bias voltage input tube (P2j) and the drain of the NMOS bias voltage input tube (N2j) are connected to the grid of the PMOS bias voltage output tube (MP3j), the drain of each PMOS bias voltage output tube (MP3j) and the drain of the fourth PMOS bias tube (MP4) are connected to one end of the first programmable resistor (R1), the other end of the first programmable resistor (R1) and one end of the second programmable resistor (R2) form a programmable bias voltage (Vpc) node, the programmable bias voltage (Vpc) node is connected to the output stage, a gain control signal (CT [ k +1: n ]) is connected to the control ends of the first programmable resistor (R1) and the second programmable resistor (R2), the other end of the second programmable resistor (R2) is grounded, and the first programmable resistor (R1) and the second programmable resistor (R2) are (n-k) bit programmable resistors.
6. A gain programmable radio frequency amplifier as in claim 5, wherein: the input stage bias mirror module comprises a third NMOS bias tube (N)inb) And a first gate isolation resistor (Rg), the programmable bias current Ipc node being connected to a third NMOS bias transistor (N)inb) And one end of the first isolation resistor (Rg), and a third NMOS bias transistor (N)inb) The source of (a) is grounded, and the other end of the first isolation resistor (Rg) is connected to the input stage.
7. A gain programmable radio frequency amplifier as in claim 6, wherein: the input stage adopts an inductance degeneration common source structure.
8. A gain programmable radio frequency amplifier as in claim 7, wherein: the input stage comprises an input matching inductance (L)g) Input matching inductance (C)g) Input NMOS amplifier tube (N)in) And emitter degeneration inductor (L)s) Said input NMOS amplifier tube (N)in) Source and input matching capacitance (C)g) Is connected to a first isolating resistor (Rg, the input matching capacitor (C)g) The other end of (a) is coupled to the inductor (L) through the inputg) Connected to an input radio frequency signal (RF)in) Said input NMOS amplifier tube (N)in) Source degeneration inductance (L) through emitters) Ground, said input NMOS amplifier tube (N)in) Is connected to the output stage.
9. A gain programmable radio frequency amplifier as in claim 8, wherein: the output stage adopts a common-gate structure.
10. A gain programmable radio frequency amplifier as in claim 9, wherein: the output stage comprises an output load inductor (L)d) An output coupling capacitor (C)o) Output NMOS amplifier tube (M)o) Gate decoupling capacitance (C)b) And a second gate isolation resistor (Rb), the output NMOS amplifier tube (M)o) Is connected with the input NMOS amplifier tube (N)in) One end of the second grid isolation resistor (Rb) is connected with the programmable bias voltage (Vpc) node, and the other end is connected with the output NMOS amplifier tube (M)o) Gate and gate decoupling capacitance (C)b) One end of the output NMOS amplifier tube (M)o) Is connected to the output load inductor (L)d) And an output coupling capacitor (C)o) One terminal of (1), the output coupling capacitor (C)o) The other end of (2) is a radio frequency output signal (RF)out)。
Technical Field
The present invention relates to a radio frequency amplifier, and more particularly, to a gain programmable radio frequency amplifier.
Background
The amplifier system is used as a key signal receiving module, the sensitivity of receiving the minimum signal is determined by high gain, and the maximum signal and the linearity are received by low gain, so that the programmable design of gain power consumption is very important to the sensitivity and the dynamic range of the receiving system. Therefore, the amplifier is subjected to gain programmable optimization design, the dynamic range of the system can be improved, the system design is simplified, and the system cost is reduced. Meanwhile, the gain programmable design can optimize the gain power consumption energy efficiency ratio, reduce the system power consumption and prolong the endurance.
As shown in fig. 1, the conventional rf amplifier is composed of a Band Gap Reference (BGR)10, a bias mirror block 20, an input stage 30, an output stage 40, and a bias circuit 50. Wherein, the Band-Gap Reference (Band-Gap Reference) is used for generating a Reference current Iref and outputting the Reference current Iref to the bias mirror module 20; the bias mirror module 20 is formed by an input bias NMOS transistor NinbAnd a first gate isolation resistor Rg for generating a stable bias voltage Vg under the control of the reference current IrefNinAnd output to the gate of input stage 30; the input stage 30 is an inductive-degeneration common-source structure, and is composed of an input matching inductor LgInput matching capacitor CgInput NMOS amplifier tube NinAnd emitter degeneration inductor LsIs formed for carrying out radio frequency signals RFinPreliminary amplification of (1); the output stage 40 is a common-gate structure and is composed of an output load inductor LdAn output coupling capacitor CoOutput NMOS amplifier tube MoGrid decoupling capacitor CbAnd a second gate isolation resistor Rb for amplifying the RF signal RF amplified by the input stage 30inFurther amplifying to obtain a radio frequency output signal RFout(ii) a A bias circuit 50 for providing a desired bias voltage Vg to the output stage 40Mo。
However, as can be seen from fig. 1, the conventional rf amplifier employs a fixed bias current and voltage circuit, has fixed power consumption and gain, does not have variable gain, and has a non-adjustable power consumption energy efficiency ratio.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a gain programmable radio frequency amplifier, which realizes the optimization of high-efficiency gain power consumption energy efficiency ratio under the bias variable programming, gain programmable regulation control and power consumption digital programming control of an input and output stage of the amplifier.
To achieve the above and other objects, the present invention provides a gain programmable rf amplifier, comprising:
a band-gap reference for generating a reference current (Iref) and outputting to the fixed bias voltage circuit;
a fixed bias voltage circuit for generating a fixed bias voltage (Vb) required by the current-voltage programmable circuit under control of the reference current (Iref);
current-voltage programmable circuit for controlling the gain of a signal (CT [1: n ]) in n bits]) Is converted into a programmable bias current (Ipc) and transmitted to the input of the input stage bias mirror module while at the same time controlling the gain of the n-bit gain control signal (CT [1: n ]) under control of]) Is controlled to convert said fixed bias voltage (Vb) into a first programmable bias voltage (Vpc) and to transfer it to the output stage to provide the bias voltage (Vg) required by the output stageMo)；
An input stage bias mirror module for generating a second programmable bias voltage (Vg) under control of a programmable current (Ipc) output by the current-voltage programmable circuitNin) And output to the input stage;
an input stage for applying a second programmable bias voltage (Vg)Nin) Under the control of (3) to complete a radio frequency signal (RF)in) Preliminary amplification of (1);
an output stage for amplifying a radio frequency signal (RF) amplified by the input stage under control of the first programmable bias voltage (Vpc)in) Further amplifying to obtain a radio frequency output signal (RF)out)；
And the low-dropout voltage stabilizing circuit is used for generating a stable voltage (Va) to supply the input stage and the output stage so as to obtain more stable gain control effect.
Preferably, the current-voltage programmable circuit comprises a current programming circuit and a voltage programming circuit, the current programming circuit comprises n first programmable bias units (31i) respectively controlled by n bits of gain control signals (CT [ i ]), i being 1, 2, … …, n, each first programmable bias unit outputs a sub-output bias current under the control of the gain control signal (CT [ i ]) and a fixed bias voltage (Vb), n sub-output bias currents are combined into the programmable bias current (Ipc) and connected to the input terminal of the input stage bias mirror module, the voltage programming circuit is used for generating a programmable bias voltage (Vpc) under the control of the n bits of gain control signals (CT [1: n ]) and the fixed bias voltage (Vb), the programmable bias voltage (Vpc) is realized by k bits of second programmable bias units (32j) and (n-k) bits of programmable resistance adjustment ratio, wherein k is less than or equal to n.
Preferably, each first programmable bias unit (31i) comprises a PMOS bias current input tube (P1i), an NMOS bias current input tube (N1i) and a PMOS bias current output tube (MP2i), the gain control signal CT [ i ] is connected to the gate of the PMOS bias current input tube (P1i) and the gate of the NMOS bias current input tube (N1i), the drain of the PMOS bias current input tube (P1i) and the drain of the NMOS bias current input tube (N1i) are connected to the gate of the PMOS bias current output tube (MP2i), the drains of the PMOS bias current output tubes (MP2i) are connected together to form the programmable bias current (Ipc) node, and the programmable bias current (Ipc) node is connected to the input bias mirror module.
Preferably, the width dimension of each PMOS bias current output tube (MP2i) has a different weight.
Preferably, the voltage programming circuit comprises k second programmable bias units (32j), a fourth PMOS bias pipe (MP4), a first programmable resistor (R1) and a second programmable resistor (R2), j is 1, 2, … …, k is less than or equal to N, each second programmable bias unit (32j) comprises a PMOS bias voltage input pipe (P2j), an NMOS bias voltage input pipe (N2j), a PMOS bias voltage output pipe (MP3j), a gain control signal CT [ j ] is connected to the gate of the PMOS bias voltage input pipe (P2j) and the gate of the NMOS bias voltage input pipe (N2j), the drain of the PMOS bias voltage input pipe (P2j) and the drain of the NMOS bias voltage input pipe (N2j) are connected to the gate of the PMOS bias voltage output pipe (MP3j), the drain of each PMOS bias voltage output pipe (MP3j) is connected to the drain of the fourth PMOS bias pipe (MP4) and to one end of the first programmable resistor (R1), the other end of the first programmable resistor (R1) and one end of the second programmable resistor (R2) form a programmable bias voltage (Vpc) node, the programmable bias voltage (Vpc) node is connected to the output stage, a gain control signal (CT [ k +1: n ]) is connected to the control ends of the first programmable resistor (R1) and the second programmable resistor (R2), the other end of the second programmable resistor (R2) is grounded, and the first programmable resistor (R1) and the second programmable resistor (R2) are (n-k) bit programmable resistors.
Preferably, the input stage bias mirror module comprises a third NMOS bias transistor (N)inb) And a first gate isolation resistor (Rg), the programmable bias current Ipc node being connected to a third NMOS bias transistor (N)inb) And one end of the first isolation resistor (Rg), and a third NMOS bias transistor (N)inb) The source of (a) is grounded, and the other end of the first isolation resistor (Rg) is connected to the input stage.
Preferably, the input stage adopts an inductive degeneration common source structure.
Preferably, the input stage comprises an input matching inductance (L)g) Input matching inductance (C)g) Input NMOS amplifier tube (N)in) And emitter degeneration inductor (L)s) Said input NMOS amplifier tube (N)in) Source and input matching capacitance (C)g) Is connected to a first isolating resistor (Rg, the input matching capacitor (C)g) The other end of (a) is coupled to the inductor (L) through the inputg) Connected to an input radio frequency signal (RF)in) Said input NMOS amplifier tube (N)in) Source degeneration inductance (L) through emitters) Ground, said input NMOS amplifier tube (N)in) Is connected to the output stage.
Preferably, the output stage adopts a common gate structure.
Preferably, the output stage comprises an output load inductance (L)d) An output coupling capacitor (C)o) Output NMOS amplifier tube (M)o) Gate decoupling capacitance (C)b) And a second gate isolation resistor (Rb), the output NMOS amplifier tube (M)o) Is connected with the input NMOS amplifier tube (N)in) One end of the second grid isolation resistor (Rb) is connected with the programmable bias voltage (Vpc) node, and the other end is connected with the output NMOS amplifier tube (M)o) Gate and gate decoupling capacitance (C)b) One end of the output NMOS amplifier tube (M)o) Is connected to the output load inductor (L)d) And an output coupling capacitor (C)o) One terminal of (1), the output coupling capacitor (C)o) The other end of (2) is a radio frequency output signal (RF)out)。
Compared with the prior art, the gain programmable radio frequency amplifier realizes programmability by controlling the input programmable current Ipc of the input stage bias mirror module by the n-bits first programmable bias unit and the output stage bias voltage Vpc by the kbits second programmable bias unit and the n-kbits programmable resistance regulation ratio, thereby realizing the purpose of optimizing the high-efficiency gain power consumption energy efficiency ratio under the bias variable programming, the gain programmable regulation control and the power consumption digital programming control of the input stage and the output stage of the amplifier.
Drawings
Fig. 1 is a circuit configuration diagram of a conventional rf amplifier;
FIG. 2 is a circuit diagram of a gain programmable RF amplifier according to the present invention;
FIG. 3 is a circuit diagram of an n-bits gain programmable RF amplifier according to an embodiment of the present invention;
fig. 4a and 4b are schematic diagrams of simulation results according to an embodiment of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a circuit diagram of a gain programmable rf amplifier according to the present invention. As shown in fig. 2, the gain-programmable rf amplifier of the present invention includes a Band Gap Reference (BGR)10, a fixed bias voltage circuit 20, a current-voltage programmable circuit 30, an input stage bias mirror module 40, an input stage 50, an output stage 60, and a low dropout regulator (LDO) 70.
Wherein, a Band-Gap Reference (BGR)10 is used to generate a Reference current Iref and output the Reference current Iref to the fixed bias voltage circuit 20; the fixed bias voltage circuit 20 comprises a first NMOS bias transistor MN1, a second NMOS bias transistor MN2, and a third NMOS bias transistorA PMOS bias MP1 for generating a fixed bias voltage Vb required by the current-voltage programmable circuit 30 under the control of the reference current Iref; a current-voltage programmable circuit 30 for controlling the gain of the signal CT [1: n ] in n bits]Converts the fixed bias voltage Vb into a programmable bias current Ipc and transmits the programmable bias current Ipc to the input terminal of the input stage bias mirror module 40 while applying the n-bit gain control signals CT [1: n ]]Converts the fixed bias voltage Vb into a programmable bias voltage Vpc and transmits it to the output stage 60 to provide the bias voltage Vg required by the output stageMoIn the present invention, current-voltage programmable circuit 30 uses a fixed bias Vb to control the gain of input n-bit gain control signal CT [1: n ]]The digital programming control of the bias mirror current Ipc of the input stage and the programmable bias voltage Vpc of the output stage of the amplifier is adjustable; the input stage bias mirror module 40 is formed by a third NMOS bias transistor NinbAnd a first gate isolation resistor Rg for generating a programmable bias voltage Vg under the control of a programmable current Ipc output by the current-voltage programmable circuit 30NinAnd output to the gate of input stage 50; the input stage 50 is an inductive-degeneration common-source structure, and is composed of an input matching inductor LgInput matching capacitor CgInput NMOS amplifier tube NinAnd emitter degeneration inductor LsIs formed for carrying out radio frequency signals RFinPreliminary amplification of (1); the output stage 60 is a common-gate structure and is loaded with an output load inductor LdAn output coupling capacitor CoOutput NMOS amplifier tube MoGrid decoupling capacitor CbAnd a second gate isolation resistor Rb for amplifying the RF signal RF amplified by the input stage 30 under the control of the programmable bias voltage VpcinFurther amplifying to obtain a radio frequency output signal RFout(ii) a And a low dropout voltage regulator (LDO)70 for generating a regulated voltage Va to supply the input stage 50 and the output stage 60 of the rf to obtain a more stable gain control effect.
FIG. 3 is a circuit diagram of an RF amplifier with programmable n-bits gain according to an embodiment of the present invention. In an embodiment of the present invention, the current-voltage programmable circuit 30 is composed of a current programming circuit 31 and a voltage programming circuit 32. The current programming circuit 31 is composed of a plurality of first programmable bias units 31i, i is 1, 2, … …, N, and is respectively controlled by a gain control signal CT [ i ], each first programmable bias unit 31i is composed of a PMOS bias current input tube P1i, an NMOS bias current input tube N1i, and a PMOS bias current output tube MP2i, and is configured to generate sub-output bias currents under the control of the gain control signal CT [ i ] and a fixed bias voltage Vb, and the N sub-output bias currents are combined into a programmable bias current Ipc and connected to the input terminal of the input stage bias mirror module 40; the voltage programming circuit 32 is composed of k second programmable bias units 32j, a fourth PMOS bias tube MP4, a first programmable resistor R1 and a second programmable resistor R2, where j is 1, 2, … …, k is less than or equal to N, and is used for generating a programmable bias voltage Vpc under the control of an N-bit gain control signal CT [1: N ] and a fixed bias voltage Vb, specifically, each second programmable bias unit 32j is composed of a PMOS bias voltage input tube P2j, an NMOS bias voltage input tube N2j, and a PMOS bias voltage output tube MP3j, and is used for outputting a bias voltage to an input end of a voltage dividing network under the control of the k-bit gain control signal CT [1: k ] and the fixed bias voltage Vb, that is, a first programmable resistor R1 is connected with one end of a drain of the fourth PMOS bias tube MP4, a first programmable resistor R1 and a second programmable resistor R2 form the voltage dividing network, and the first programmable resistor (R1) and the second programmable resistor (R35k) are N-bit resistors (2), for changing respective resistance values under the control of the n-k bit gain control signal CT [ k +1: n ] to divide the bias voltages output by the second programmable bias unit 32j and the fourth PMOS bias transistor MP4 to generate the programmable bias voltage Vpc.
Specifically, an output reference current Iref of a bandgap reference (BGR)10 is connected to the drain and gate of a first NMOS bias transistor MN1 and the gate of a second NMOS bias transistor MN2, the source and substrate of the first NMOS bias transistor MN1 and the source and substrate of the second NMOS bias transistor MN2 are grounded, the drain of the second NMOS bias transistor MN2 and the drain and gate of the first PMOS bias transistor MP1 form a fixed bias voltage Vb node, the fixed bias voltage Vb node is connected to the source and substrate of an NMOS bias current input transistor N1i, the source and substrate of an NMOS bias voltage input transistor N2j and the gate of a fourth PMOS bias transistor 4, i is 1, 2, … …, N, j is 1, 2, … …, k;
the gain control signal CT [ i ] is connected to the gate of the PMOS bias current input tube P1i and the gate of the NMOS bias current input tube N1i, the drain of the PMOS bias current input tube P1i and the drain of the NMOS bias current input tube N1i are connected to the gate of the PMOS bias current output tube MP2i, i is 1, 2, … …, N;
the drains of the PMOS bias current output tubes MP21, MP22, … … and MP2N are connected together to form a programmable bias current Ipc node, and the programmable bias current Ipc node is connected to the third NMOS bias tube NinbThe drain electrode and the grid electrode of the first NMOS biasing tube N, and one end of the first isolation resistor RginbThe source of (2) is grounded;
a gain control signal CT [ j ] is connected to the gate of the PMOS bias voltage input tube P2j and the gate of the NMOS bias voltage input tube N2j, the drain of the PMOS bias voltage input tube P2j and the drain of the NMOS bias voltage input tube N2j are connected to the gate of the PMOS bias voltage output tube MP3j, j is 1, 2, … …, k is less than or equal to N, the drains of the PMOS bias voltage output tubes MP31, MP31, … …, MP3k are connected together, the drain of the fourth PMOS bias tube MP4 is connected to one end (voltage dividing network input end) of the first programmable resistor R1, the other end of the first programmable resistor R1 and one end of the second programmable resistor R2 form a programmable bias voltage Vpc node, the programmable bias voltage Vpc node is connected to one end of the second gate isolation resistor Rb, the gain control signal CT [ k +1: N ] is connected to the control ends of the first programmable resistor R1 and the second programmable resistor R2, the other end of the second programmable resistor R2 is grounded;
the other end of the first isolation resistor Rg is connected to the input NMOS amplifier tube NinGate and input matching capacitor CgOne terminal of (1) an input matching capacitor CgThe other end of (1) is coupled to the inductor L through the inputgConnected to an input radio frequency signal RFinNMOS amplifier tube NinSource electrode negative feedback inductance L through emitter electrodesGrounded NMOS amplifier tube NinDrain electrode of the NMOS amplifier tube M is connected with the output NMOSoA source and a substrate;
the other end of the second gate isolation resistor Rb is connected to the output NMOS amplifier tube MoGate and gate decoupling capacitor CbOne end of (1), output NMOS amplifier tube MoIs connected with an output load inductor LdAnd an output coupling capacitor CoOne terminal of (1), an output coupling capacitor CoThe other end of (2) being the radio frequency output signal RFout；
An input power supply Vdd is connected to a power supply end of a Band Gap Reference (BGR)10, a source and a substrate of a first PMOS bias tube MP1, a source and a substrate of a PMOS bias current input tube P1i, a source and a substrate of a PMOS bias current output tube MP2i, a source and a substrate of a PMOS bias voltage input tube P2j, a source and a substrate of a PMOS bias voltage output tube MP3, a source and a substrate of a fourth PMOS bias tube MP4, an input end of a low dropout regulator (LDO) circuit 70, and a gate decoupling capacitor CbAnd the other end of the output load inductor Ld is connected to an output end of a low dropout regulator (LDO)70, i.e., a power supply Va.
Fig. 4a and 4b are schematic diagrams of simulation results according to an embodiment of the present invention. In the embodiment, the 4-bits gain programmable amplifier and the power consumption control effective design are realized, the gain is programmably adjusted from 6dB to 21dB, and correspondingly, the current is changed from 0.5mA to 7.8 mA.
Therefore, in the invention, the input programmable current Ipc of the input stage bias mirror module 40 is controlled by the n-bits programmable bias unit, the width size of each PMOS bias current output tube MP2i has different weights, and the output stage bias voltage Vpc is programmable by the k-bits second programmable bias unit and the n-k bits programmable resistance regulation ratio, thereby realizing the purpose of optimizing the high-efficiency gain power consumption energy efficiency ratio under the control of amplifier input and output stage bias variable programming, gain programmable regulation control and power consumption digital programming.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
- 上一篇：一种医用注射器针头装配设备
- 下一篇：一种带有自检系统的线性高功率放大器及供电方法