阅读说明：本技术 基于忆阻器的电路和方法 (Memristor-based circuit and method ) 是由 A·贾比尔 S·坎德尔瓦尔 X·杨 于 2020-04-15 设计创作，主要内容包括：描述了一种基于忆阻器的电路,其中电压发生器被布置成向忆阻器施加一系列电压脉冲以逐渐地改变所述忆阻器的电阻。比较器被布置成：接收输入电气值；接收基于所述忆阻器的所述电阻的电气值；将所接收的值进行比较；并且基于比较,使得所述电压发生器能够向所述忆阻器施加所述电压脉冲直到满足所定义的条件。此电路可以用于使得所述忆阻器能够被编程到期望的电阻值,例如用作非易失性存储器。所述电路还可以使得一个忆阻器的所述电阻能够复制到另一个忆阻器。通过对施加的电压脉冲的数量进行计数,所述电路可以用作编码器或模数转换器。所述电路的其它变体使得能够构造解码器或数模转换器以及认证电路。(A memristor-based circuit is described, in which a voltage generator is arranged to apply a series of voltage pulses to a memristor to gradually change a resistance of the memristor. The comparator is arranged to: receiving an input electrical value; receiving an electrical value based on the resistance of the memristor; comparing the received values; and based on the comparison, enabling the voltage generator to apply the voltage pulse to the memristor until a defined condition is satisfied. This circuit may be used to enable the memristor to be programmed to a desired resistance value, for example, for use as a non-volatile memory. The circuit may also enable the resistance of one memristor to be replicated to another memristor. By counting the number of applied voltage pulses, the circuit can be used as an encoder or an analog-to-digital converter. Other variants of the circuit enable the construction of a decoder or digital-to-analog converter and an authentication circuit.)

1. A memristor-based circuit, comprising:

a memristor;

a voltage generator arranged to apply a series of voltage pulses to the memristor so as to incrementally change a resistance of the memristor; and

a comparator arranged to receive an input electrical value, receive an electrical value based on the resistance of the memristor, compare the received values, and enable application of the voltage pulse to the memristor by the voltage generator based on the comparison until a defined condition is satisfied.

2. The circuit of claim 1, wherein the input electrical value comprises an input voltage, and the electrical value based on the resistance of the memristor is a voltage obtained from a voltage divider circuit comprising the memristor.

3. The circuit of claim 1 or 2, wherein the memristor is a target memristor, and further comprising a source memristor in a voltage divider circuit to provide the input voltage, wherein the resistance of the source memristor is replicated into the resistance of the target memristor.

4. An encoder, comprising:

a circuit according to any one of claims 1 to 3; and

a counter arranged to count a number of voltage pulses applied to the memristor, and

and outputting the number.

5. An analog to digital converter comprising an encoder according to claim 4, wherein the input electrical value comprises an analog input and the pulse count value comprises a digital output.

6. A decoder, comprising:

the circuit of claim 1, which is devoid of a comparator; and

a counter arranged to receive a number as an input and arranged to cause the voltage generator to apply the number of voltage pulses to the memristor.

7. The decoder of claim 6, wherein the counter is a down counter initialized to an input number, the down counter configured to decrement each time the voltage generator applies a voltage pulse to the memristor, and configured to cause the voltage generator to stop applying the voltage pulse to the memristor when a count value reaches zero.

8. A digital to analog converter comprising a decoder according to claim 6 or 7, wherein the number of inputs received comprises a digital input and the electrical value based on the resistance of the memristor comprises an analog output.

9. An authentication circuit comprising the encoder of claim 4, without a memristor, wherein the authentication circuit is connectable to a memristor disposed in an external circuit, wherein inputting an electrical value comprises a challenge, and wherein outputting a quantity comprises a response based on the memristor of the external circuit.

10. An authentication circuit comprising the decoder of claim 6 or 7, without a memristor, wherein the authentication circuit is connectable to a memristor disposed in an external circuit, wherein the quantity received as an input comprises a challenge, and wherein the electrical value based on the resistance of the memristor of the external circuit comprises a response.

11. The authentication circuit of claim 9 or 10, wherein the external circuit comprises a chip marked or identified by the memristor.

12. A method, comprising:

receiving an input electrical value;

applying a series of voltage pulses to a memristor to incrementally change a resistance of the memristor;

receiving an electrical value based on the resistance of the memristor; and

the received values are compared, and based on the comparison, the voltage pulse is enabled to be applied to the memristor until a defined condition is satisfied.

13. The method of claim 12, wherein the input electrical value comprises an input voltage, and the electrical value based on the resistance of the memristor is a voltage obtained from a voltage divider circuit comprising the memristor.

14. The method of claim 12 or 13, wherein the memristor is a target memristor, and wherein a source memristor in a voltage divider circuit provides the input voltage, and whereby a resistance of the source memristor is replicated into the resistance of the target memristor.

15. A method, comprising:

receiving an input electrical value;

applying a series of voltage pulses to a memristor to incrementally change a resistance of the memristor;

receiving an electrical value based on the resistance of the memristor;

comparing the received values and, based on the comparison, enabling application of the voltage pulse to the memristor until a defined condition is satisfied; and

counting a number of voltage pulses applied to the memristor, and outputting the number.

16. A method, comprising:

receiving the quantity as an input;

applying a series of voltage pulses to a memristor to incrementally change a resistance of the memristor;

counting such that the number of voltage pulses applied to the memristor equals the number received as an input; and

outputting an electrical value based on a resulting resistance of the memristor.

Embodiments of the present invention may provide a simple and effective lightweight memristor replicator structure capable of replicating a resistance of a source memristor into a target memristor by repeatedly applying programming pulses. Such circuitry may be used to backup analog data, for example from memristor sensors, before or during conversion to digital form. The proposed circuit structure is very versatile and can be used not only to replicate memristors, but also to generate nonlinear digital codes and decode the codes back to the source memristor/voltage (within quantization limits). The architecture also provides a level of intrinsic security features due to the non-linear encoding. Memristors may provide physical unclonability, and thus embodiments of the present invention may be used in applications such as chip marking/identification, as well as to prevent unauthorized manufacturing. Due to its simple and general nature, embodiments of the present invention may be used in remote and low power devices that require a certain level of security, such as in remote sensor nodes and the like.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIGS. 1(a) and 1(b) respectively show a TiO-based material₂The structure and corresponding circuit symbol of the memristor of (1);

FIG. 2 is a schematic circuit diagram of a memristor circuit in accordance with an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a memristor replicator circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic circuit diagram of a memristor-based encoder (or analog-to-digital converter (ADC)) circuit, according to an embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a memristor-based decoder (or digital-to-analog converter (DAC)) circuit, according to an embodiment of the present disclosure;

FIG. 6 is a more detailed circuit diagram of a memristor-based replicator/encoder/decoder according to another embodiment of the present disclosure;

FIG. 7 shows a graph of encoded digital outputs for different memristor sizes;

FIG. 8 shows a graph of encoded digital outputs for different programming pulse voltages; and

FIGS. 9(a) and 9(b) are graphs showing the effect of encoding values on different program pulse widths.

In the drawings, the same components are denoted by the same reference numerals, and repeated description of the same components is omitted.

Memristors are referred to in the art as the following devices: its resistance (also called memristance) is changed by the current flowing through the device. The resistance having a minimum value R_ONAnd maximum value R_OFF. The resistance can be tuned by applying an appropriate voltage or current, andnon-volatile (resistance values are 'remembered'), so that memristors may be used as memory elements. The resistance may also be affected by external factors, so the memristor may be used as a sensor element.

Memristors can be made from a variety of materials, for example: TiO2₂(e.g., with doped and undoped regions and with a Pt electrode); Ag/Ag₅In₅Sb₆₀Te₃₀a/Ta; Ag-a-LSMO-Pt (Ag nano-single fibers in amorphous manganate films); other semiconducting metal oxides, such as aluminum oxide, copper oxide, silicon oxide, zinc oxide, tantalum oxide, hafnium oxide; amorphous perovskite oxides (e.g. a-SrTiO)₃) (ii) a And other ferroelectric and doped polymer materials, and graphene oxide. Embodiments of the present invention are not limited to any particular material, provided that memristive properties are present. A component that is a memristor is described herein as a memristor. In the following description, by way of example only, the examples are based on TiO₂Memristors.

Memristors typically exhibit nonlinear behavior. According to one model, the total resistance of a memristor is determined by the resistances of two regions: undoped region (TiO2) and doped region (TiO2)_2-X) As shown in fig. 1 (a). If the initial resistance of the memristor is R_initIf x is 0, R_init＝R_on(low resistance state), and for x ═ D, R_init＝R_off(high resistance state). The lengths (x and D) depicted in this figure will be used in the rest of the description.

In practical memristive devices, memristance depends on highly nonlinear tunneling effects. Thus, any change in tunnel barrier width changes the resistance to memristion and appears to vary exponentially by x. Instantaneous memristor R_MGiven in equation 1.

It is composed ofx_on≤x≤x_offAnd x_onAnd x_offAre the lower and upper limits of the undoped region.

Fig. 1(b) shows the notation of memristors. Here, P and N are their 'positive' and 'negative' terminals, respectively. When the instantaneous voltage V_P>V_offWhile the memristor switches to a high resistance state (R)_off) When V is_P<V_onIs switched to a low resistance state (R)_on) For V as in equation 2_in＝V_PAs defined. When V is_on<V_P<V_offWhile the state of the memristor is unchanged, i.e., in a 'hold' state.

Wherein K_off、K_on、α_on、α_offIs a constant, and V_onAnd V_offIs the threshold voltage. Function F_off(x) And F_on(x) Representing the dependence of the derivative of the state variable x. These functions behave as window functions that constrain the state variables to x e x_on,x_off]The limit of (2).

Applying a write voltage V_W(0<V_off<V_W) To transfer the potential barrier of the memristor from R_ONTo R_offIs shifted and a read voltage V is applied_R(V_ON<V_R<V_off) To read the resistance/voltage drop across the memristor, as given by equation 2.

Referring to FIG. 2, a basic circuit is depicted in which the voltage generator 10 is arranged to include a memristor M_DAnd a load resistor R_DLAcross which a voltage is applied. Memristor M_DIs initialized to be in a low resistance state R_ON. Next, voltage generator 10 receives a clock signal clk input at terminal 12, the clock signal clk being at time T_progHigh level and time T_holdRepeatedly switched between low levels, andgenerators 10 are each at T_progAnd T_holdDuring which the programming voltage V is output_progAnd a holding voltage V_hold. Taking into account the load R_DLWill V_progAdjusted high enough so that V_WAppearing in memristor M_DTwo ends. Similarly, V is_holdIs adjusted high enough so that V_RAppearing in memristor M_DTwo ends. Thus, the memory resistor M_DA series of voltage pulses is applied that incrementally change the resistance of the memristor.

The comparator 14 receives an input electrical value, in this case an input voltage, at a terminal 16. The comparator 14 also includes a memristor M_DThe voltage divider of (a) receives a voltage. During a time period T in which a programming voltage pulse is not applied to a memristor_holdDuring which the comparator compares the two received voltages, optionally with a weighting factor. When a defined condition is met, for example the voltage at the voltage divider equals or exceeds the input voltage at terminal 16, the output of the comparator causes the voltage generator 10 to stop applying further programming voltage pulses and the resistance of the memristor is now fixed.

Thus, memristor M_DCan be accurately and reproducibly 'programmed' to a value that depends on the value of the input voltage; different input voltages will result in different resistances.

FIG. 3 depicts a modification of the circuit of FIG. 2 in which the input terminal 16 is connected to include a source memristor M_SAnd a source load resistor R_SLA voltage divider of (2). The original memristor is now the target memristor M_D. In the preferred embodiment, the load resistor R_SLAnd R_DLAre matched and the source memristor M_SAnd target memristor M_DAre also matched. Source memristor M_SWith the resistance (memristance) value already set, for example, the source memristor may be a sensor whose resistance value is related to the property being sensed.

Voltage V_holdIs applied to the source memristor M_SAnd a memristor M_DIs initialized to be in a low resistance state R_ON. When the clock signal is now applied to terminal 12, the resistance of the target memristor passes the programming voltage pulse (at time period T)_progA period of V_prog) Incrementally until the two voltages input to comparator 14 are equal (at T)_holdDuring a time period) at which the process terminates. The result is a source memristor M_SIs copied to the target memristor M_D。

If different component values are used in the circuit, the memristor resistances will not necessarily be the same, but the resistance of the target memristor will be related to the resistance of the source memristor. This embodiment shows how a resistor can be used as an input electrical value to be copied to another resistor. However, embodiments of the invention may use other content as input electrical values, such as voltage or current. The resulting output may also be a resistance, voltage, current, or other electrical value.

For the embodiment of FIG. 3, if the source memristor is, for example, a sensor, the above-described replication process may be used to read and store the sensed values at specific times. The target memristor may be one of an array of such memristors that are selectable and each programmed sequentially over time to store a sensed value for subsequent retrieval. Of course, it is not necessary to have an active memristor, and any electrical value, such as the input voltage in the circuit of FIG. 2, may simply be read and stored.

This technique of reading and storing electrical values is advantageous because it does not require a large amount of digital circuitry and therefore can be compact and low power. This makes it particularly suitable for remote sensing applications.

In fig. 4 is shown another embodiment of the invention, which is based on the circuit of fig. 2 but with the addition of a counter 20. Counter 20 pair applied to memristor M_DProgramming voltage pulse V of_progUntil programming stops, and then outputs the number, for example, as an n-bit binary number. This number of outputs is related to the input analog electrical value (e.g., voltage) at terminal 16. Thus, the circuit functions as an analog-to-digital converter (ADC). The circuit also functions as an encoder to convert an input value to a unique number. The coding is non-linear becauseIt depends on, for example, the memristor M_DOf (and dependent on e.g. V)_prog、T_progSuch as parameters). This makes the encoding safe, since the actual output value is meaningless without knowing the memristor properties, i.e. without at least approaching or knowing these properties and parameters in advance, the quantity cannot be decoded back to obtain the original input value, and even the trend of the quantity is useless due to the non-linearity. Thus, the code (quantity) generated is effectively unique to the particular memristor used to generate it, and is therefore locked to that particular device.

Any embodiment described herein may of course be combined with any other embodiment or feature thereof as appropriate. Thus, the source memristive voltage divider of fig. 3 may be used with the circuit of fig. 4. This will enable the source memristor values to be read, backed up, and output as digital values at the same time, all with a single simple circuit.

Starting next with the encoder circuit of fig. 4, the circuit of fig. 5 provides a corresponding decoder. The number C is input to the counter 20 as an initial count value, and in this case the counter is configured to decrement the counter; memristor M_DIs initialized to be in a low resistance state R_ON. When the clock signal clk is applied to the terminal 12, the resistance of the target memristor is incrementally changed by the programming voltage pulse. The counter 20 is decremented each time a voltage pulse is applied. When the counter reaches zero, this is indicated as having voltage generator 10 stop applying further programming voltage pulses and instead apply only V_holdTo output of (c). Memristor M_DWith the exact C programming pulses applied thereto. The voltage at terminal 22 of the voltage divider is now an analog value based on the input quantity C, i.e. the quantity C has been uniquely decoded (non-linearly decoded) to the voltage at terminal 22. Therefore, this circuit also functions as a digital-to-analog converter (DAC).

The circuits of fig. 4 and 5 may also each function as an authenticator for authentication checking purposes. The inputs are analog voltage and digital (fig. 4 and 5), respectively, and the corresponding outputs are digital and analogA voltage. The inputs and outputs form challenge-response pairs (CRP). In one implementation, the memristor M_DIs provided in an external circuit, for example in a chip in a piece of electronic equipment or in an IC card, for example a bank card, and is connected to the rest of the respective circuit. The expected response (output) based on one or more challenges (inputs) is known to the entity seeking authentication. If the memristor is authentic, the correct response will be obtained (within a defined margin of error) and the chip/electronic device may be verified as authentic. If the original memristor is not used, the correct response will not be obtained and authentication may be denied. Unauthorized copies of memristors cannot be easily fabricated because the electronic properties of memristors are strongly dependent on fabrication parameters and are non-linear, as discussed further below. Thus, the chip/electronic device can be marked and identified using memristors and cloning cannot be performed.

FIG. 6 illustrates a method for modeling a source memristor M within a specified quantization limit_SCopy to target memristor M_DAn embodiment of a specific architecture of (1). Memristor M_S、M_DAnd a load resistor R_SLAnd R_DLTwo voltage dividers are formed. R_SLAnd R_DLAppear to be a close match. Voltage divider V_INSAnd V_INDThe output voltages of (c) are continuously compared by a comparator Comp. The architecture is simple, power efficient, and requires a small number of logic gates, comparators, level shifters (also known as voltage converters, and indeed a form of comparator, and performs the function of voltage generator 10 in the foregoing embodiments), and edge sensitive counters. In a preferred embodiment, the level shifter is "gated", i.e., enabled or disabled depending on whether power is supplied to the level shifter's power input line (indicated as ' Strobe ' in fig. 6).

A. Copying and encoding: let f_repIs the frequency of the replica of the clock (clk), and T_rep＝T_prog+T_hold＝1/f_repIs the clock cycle. At T_progAnd T_holdDuring which voltage V is alternately applied_progAnd V_hold. Will be provided withV_progIs adjusted to be high enough to have even a load R_DL，V_WAlso only present in the memristor M_DTwo ends. Similarly, V is_holdAdjusted high enough so that V_ROccurring simultaneously at memristor M_SAnd M_DTwo ends. Thus, by repeatedly applying these pulses based on equation 2, the memristor M_SIs copied to the memristor M_D. At each T_progPeriod, V_progWill M_DFrom R to R_onRegion direction R_offThe region is displaced by a small but non-linear amount and at a subsequent T_holdDuring the period, M is_DAnd M_SThe memristions of (a) are compared. The top counter counts the number of clock pulses required for replication.

The replication is performed by first applying the counter sum to the memristor M_DThe 'CLR' pulse of the negative terminal of (a) is reset to start. This pulse has sufficient amplitude such that a very short duration will memristor M_DReset to R_on. The first stage of the counter is used to generate the pulses and once the CLR is complete, the counter is reused for encoding. During CLR: disabling the level shifter via the strobe input; the AND gates a2 AND A3 block the input AND produce a constant zero. Thus, the clock signal clk is prevented from reaching the level shifter. As a result, the level shifter is at memristor M_DProduces a 0 at the P terminal of (1), while a high CLR pulse at the N terminal of the memristor will memristor M_DReset to R_on。

When CLR returns to 0, the level shifter AND gates a2 AND A3 are enabled AND copying begins. A2 passes clk to a level shifter, which is in the same cycle (T)_rep) In V_progAnd V_holdTo switch between. V_progAt T_progDuring which the memristor M will be recalled_DAnd the comparator Comp is at T_holdDuring which the resulting voltage and memristor M_SThe voltages at both ends are compared. At T_holdDuring this time, the comparator keeps producing 1 until memristor M_DVoltage across exceeds memristor M_SThe voltage across the terminals. This forces A3 and A4 to produce0 is generated, which causes A1 to pass clk to the level shifter. As a result, memristor M_DThe voltage across it gradually increases during each clock cycle until it exceeds the memristor M_SVoltage across the comparator at T_holdDuring which a 0 is generated. This forces A3 and a4 to generate a1 and the level shifter is disabled via the strobe. This prevents a1 from letting clk pass, thereby indicating the end of the copy. Essentially, the circuit enters a 'locked-out' state, which is represented by the memristor M_DVoltage control across the terminals. During replication, the counter counts the number of clock cycles required for replication, which is the memristor M_SThe encoded digital value of the analog voltage (resistance) of (1). Thus, the proposed architecture performs non-linear encoding of the analog voltage/resistance when replication occurs.

As described above, when the copy (or transcoding) is complete, the level shifter is disabled by stopping the application of power (Vdd) to the "strobe" input. This means that the level shifter produces an and 0V output instead of V_hold(ii) a Thus, zero voltage is applied to the memristor M_DTo avoid undesirably long durations of sustained voltage applied across the memristor. Power switching or gating may be accomplished using a single PMOS or NMOS transistor.

Thereafter, the second phase of the replication may begin with a CLR pulse that is applied to the memristor M_DA reset is performed, thereby bringing the system out of the locked state (level shifter enabled).

For a fixed V_progAccuracy depends on T_progAnd lower T, and_progresulting in higher accuracy but at the cost of increased replication/conversion time.

If source memristor M_SIs (or equivalently, voltage V)_INS) Is stable, the copy/encode process will naturally terminate. However, in which V_INSIn time-varying applications (e.g., in sensor applications), when the circuit attempts to match V_INSAnd V_INDThe counter may continue to increment, which may be undesirable. An alternative embodiment is to have the output of the comparator and the level shifter (voltage)A generator) between the inputs (e.g., between gate a4 and gate a 1) includes a latch (e.g., an SR flip-flop, a D flip-flop, etc.). When V is_INDAnd V_INSWhen matched, the latch will 'lock' the reading (counter value and/or memristance) at the first time instant, which may be appropriate for some applications. However, this may not be desirable in other situations, so another embodiment of the invention has a predetermined 'sense' period, and after the preset sense period has elapsed the clock is automatically stopped to then give a reading. The detection period can be made relative to T_repLong enough for V_INDWill have time to match V_INS。

B. And (3) decoding: if at the time of copying, the counter records a digital value C. Decoding is by first pairing the memristor M with CLR in C cycles_DZero clearing is performed and by at the same frequency f_rep＝1/(T_prog+T_hold) Below with the same V_progAnd V_holdThe memristor is 'programmed'. Part of the decoder logic appears in the dashed box labeled 'decode' in fig. 6. A down counter (not shown) initialized to C is used to count the number of clock cycles. After decoding, V_hold-V_DL(wherein V_DLIs R_DLThe voltage drop across) divided by the current gives the corresponding coding resistance within the quantization limit.

C. Safety and physical unclonability: the circuit architecture provides a level of intrinsic security by means of non-linear coding. The code value C being V_W、T_prog、T_holdAnd M_DA function of itself. Therefore, it is very challenging to guess what the resistance or voltage C represents without fully knowing these quantities. In addition, a derivative of M is obtained_DNearly exactly matching memristors provide further challenges and difficulties.

The architecture also provides physical unclonability by virtue of non-linearity and its sensitivity to process and parameter variations. As shown by experimental results, the non-linear code depends largely on the memristor M_DPhysical parameters of (e.g. length dimension D, threshold value)Voltage, etc. Any slight variations in these parameters are amplified by the count-based encoding mechanism and result in different codes (fig. 7). Thus, any two manufactured chips may produce different codes for the same input voltage/resistance, thereby making it very difficult to clone.

While this architecture is suitable for replicating memristors, it may also be used for non-linear encoding/decoding, and for challenge-response pair (CRP) based authentication. Substitute for memristor M_SIn FIG. 6, V_INSMay be an input voltage for use as a challenge. After encoding, the contents of the counter can be used as the only non-linear response. In addition, due to the physical unclonability of the chip, this response will vary from chip to chip, thus also providing a specification of chip identification/tagging. V_INSThe analog input voltage at (a) may be obtained from lightweight encryption hardware or a hash function generator (e.g., a linear feedback shift register) to improve security.

In the foregoing embodiments of the invention, the memristor M_DIs initialized to be in a low resistance state R_ONAnd the application of the voltage pulse will drive the resistance towards the high resistance state R_OFFGradually increased until a defined condition is met. However, by recalling the memristor M_DInitialisation to a high resistance state R_OFFAnd then applying a voltage pulse (of opposite polarity to that in the previous embodiment) to change the resistance to the low resistance state R in negative increments_ONAlternative embodiments of the present invention may operate equally well until a defined condition is met (e.g., as detected by a comparator having an inverted input terminal relative to the previous embodiment).

The experimental results are as follows: memristors are encoded using the above model, and the circuit is simulated. Experiments were performed using 32nm technology nodes, where V_prog＝41mV，V_hold＝20mV，T_prog＝2.5ns，R_SL＝R_DL＝1KΩ，R_ON＝1KΩ，R_off＝100KΩ，D＝3nm，K_off＝5e-4，K_ON＝-10,α_on＝3，α_off＝1，V_ONIs not more than-0.2 andand V is_off0.02. Table 1 shows that when M_SThe result was obtained when the temperature was changed from 10 K.OMEGA.to 90 K.OMEGA.. It is apparent that the encoded values are nonlinear in nature and are replicating the resistance to the target memristor M_DWhile maintaining a low percentage error.

Table 1: copy/encode (R)_on＝1KΩ,R_off＝100KΩ)。

The circuit architecture inherently provides a certain level of security by means of non-linear coding as shown in fig. 7. This figure also shows memristor M_DResulting in different analog-to-digital conversion characteristics.

FIG. 8 and FIGS. 9(a) and 9(b) show the change V, respectively_progAnd T_progWhile keeping the results of the other parameters fixed. It can be seen that the behavior of the architecture is always non-linear, i.e. it is specific to a particular V_progOr T_progAnd non-linear with respect to their differences.

Embodiments of a novel memristor replicator circuit architecture capable of replicating a source memristor to a target memristor have been disclosed herein. This architecture also enables the generation of non-linear digital codes and may provide additional security features and physical unclonability. The architecture is lightweight and relies on only a few logic components, namely two comparators (one acting as a level shifter) and one counter. Experimental results show that the architecture is superior to the existing design in terms of chip area, power consumption and performance reliability. The architecture is extremely versatile and can be used in applications for backing up analog data (e.g., sensed information), especially in remote sensor nodes, non-linear encoding, chip labeling/identification, and for preventing unauthorized chip manufacturing.