阅读说明：本技术 比较器低功率响应 (Comparator low power response ) 是由 尼汀·阿加瓦尔 文卡特·罗摩克里希纳·萨里帕利 文卡塔·拉马南德·R 于 2020-04-08 设计创作，主要内容包括：在所描述实例中,放大器(100)可经布置以响应于输入信号而产生第一级(110)输出信号。所述输入信号可经耦合以控制通过共同节点(114)从第一电流源I1耦合的第一电流以产生所述第一级输出信号。复本电路(120)可经布置以响应于所述输入信号且响应于从所述共同节点(114)接收的电流而产生复本负载信号。电流开关Q7可经布置以响应于所述复本负载信号而选择性地将来自第二电流源(140)的第二电流耦合到所述共同节点(114)。(In described examples, an amplifier (100) may be arranged to generate a first stage (110) output signal in response to an input signal. The input signal may be coupled to control a first current coupled from a first current source I1 through a common node (114) to generate the first stage output signal. A replica circuit (120) may be arranged to generate a replica load signal in response to the input signal and in response to a current received from the common node (114). A current switch Q7 may be arranged to selectively couple a second current from a second current source (140) to the common node (114) in response to the replica load signal.)

1. A circuit, comprising:

an input transistor pair comprising first and second transistors, wherein a first current terminal of the first transistor is coupled to a first current terminal of the second transistor and to a common node, wherein the common node is coupled to receive current from a first current source, wherein a control terminal of the first transistor is coupled to a first input signal of the input transistor pair, and wherein a control terminal of the second transistor is coupled to a second input signal of the input transistor pair;

a replica circuit comprising third and fourth transistors, wherein a first current terminal of the third transistor is coupled to a first current terminal of the fourth transistor and the common node, wherein a second current terminal of the third transistor is coupled to a feedback signal node, wherein a second current terminal of the fourth transistor is coupled to the feedback signal node, wherein a control terminal of the third transistor is coupled to the first input signal of the input transistor pair, and wherein a control terminal of the fourth transistor is coupled to the second input signal of the input transistor pair; and

a current switch having a first current terminal coupled to a power supply rail, a second current terminal coupled to the common node, and a control terminal coupled to the feedback signal node.

2. The circuit of claim 1, wherein the replica circuit is arranged to determine performance of the input transistor pair to produce a determined performance.

3. The circuit of claim 2, wherein the indication of determined performance is coupled to the control terminal of the current switch.

4. The circuit of claim 2, wherein the replica circuit is arranged to detect an undercurrent condition of the common node.

5. The circuit of claim 1, further comprising a bias generator arranged to generate a bias signal in response to an indication received from the feedback signal node.

6. The circuit of claim 5, wherein the bias signal is asserted to activate the current switch in response to a decrease in the indicated current received from the feedback signal node.

7. The circuit of claim 5, wherein the current switch is arranged to selectively couple current from a second current source to the common node in response to the bias signal.

8. The circuit of claim 1, comprising a current mirror having a first input coupled to a second current terminal of the first transistor and having a second input coupled to a second current terminal of the second transistor, wherein the first input of the current mirror is coupled to a first output of the input transistor pair, and wherein the second input of the current mirror is coupled to a second output of the input transistor pair.

9. The circuit of claim 8, further comprising first and second resistors coupled in series between the first input of the current mirror and the second input of the current mirror, wherein a node between the first and second resistors is coupled to bias respective control terminals of transistors of the current mirror.

10. The circuit of claim 8, further comprising a second stage, wherein the current mirror is a first current mirror, and wherein the second stage comprises a second current mirror having a master transistor and a slave transistor, wherein the master transistor and the slave transistor are biased in response to the first input of the current mirror, wherein a second stage output signal is generated in response to the second input of the current mirror and in response to a current supplied by the slave transistor.

11. The circuit of claim 10, wherein the second stage is a differential input of a single-ended output converter.

12. The circuit of claim 10, further comprising a third stage arranged to quantize the second stage output signal to convert the second stage output signal to a digital value and to output a digital signal in response to the digital value.

13. A circuit, comprising:

a first stage amplifier coupled to receive an input signal, wherein the first stage amplifier includes a common node coupling a first current from a first current source to at least one transistor of the first stage amplifier, wherein the first stage amplifier is coupled to generate a first stage output signal in response to the input signal;

a replica circuit coupled to receive current from the common node and arranged to generate a replica load signal in response to the input signal;

a bias generator coupled to generate a bias signal in response to the replica load signal; and

a current switch arranged to selectively couple a second current from a second current source to the common node in response to the bias signal.

14. The circuit of claim 13, wherein the bias voltage generator is coupled to assert the bias voltage signal to activate the current switch in response to a decrease in a voltage of a replica load signal.

15. The circuit of claim 13, further comprising the first and second current sources, wherein the first and second current sources are coupled in parallel between a power rail and the common node.

16. The circuit of claim 13, further comprising a second stage amplifier coupled to convert a differential input received from the first stage amplifier to a single-ended output of the second stage amplifier.

17. The circuit of claim 16, further comprising an output stage coupled to generate an output signal in response to the single-ended output of the second stage amplifier.

18. A method, comprising:

generating, by a first stage, a first stage output signal in response to an input signal, wherein the input signal is coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal;

generating, by a replica input transistor pair, a replica load signal in response to the input signal and in response to a current received from the common node; and

selectively coupling a second current from a second current source to the common node in response to the replica load signal.

19. The method of claim 18, wherein the replica load signal is generated in response to detecting an undercurrent response of an input transistor pair arranged to generate the first stage output signal.

20. The method of claim 19, wherein the replica load signal is generated in response to an emulation of the input transistor pair.

Background

Electronic circuits are designed to incorporate increasingly smaller design features. Smaller design features of electronic circuits may be used to achieve smaller form factors, increased functionality, and reduced power consumption of electronic circuits. Such electronic circuits may include amplifiers (including comparators) for controlling various systems. Some comparators are arranged as part of the control circuit. The stability and accuracy of such control circuits typically depends on the delay of the included comparators. However, reducing power consumption of circuitry including comparators may increase delay and/or reduce the accuracy of the output signals generated by the included comparators.

Disclosure of Invention

In described examples, an amplifier may be arranged to generate a first stage output signal in response to an input signal. The input signal may be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit may be arranged to generate a replica load signal in response to the input signal and in response to a current received from the common node. A current switch may be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

Drawings

FIG. 1 is a schematic diagram of an example comparator for low power response to input signal fluctuations.

FIG. 2 is a waveform diagram of an example simulation of a disabled low power response of an example comparator to a large input signal transition.

FIG. 3 is a waveform diagram of an example simulation of a low power response of an example comparator to a large input signal transition.

FIG. 4 is a waveform diagram of an example simulation of a disabled low power response of an example comparator to a small input signal transition.

FIG. 5 is a waveform diagram of an example simulation of a low power response of an example comparator to a small input signal transition.

FIG. 6 is a waveform diagram of another example simulation of a disabled low power response of an example comparator to a large input signal transition.

FIG. 7 is a waveform diagram of another example simulation of an enabled low power response of an example comparator to a large input signal transition.

Fig. 8 is a schematic diagram of another example Aux _ bias generator for the low power response of an example comparator.

FIG. 9 is a flow diagram of an example method for responding to input signal fluctuations for an example low power comparator.

Detailed Description

The electronic circuitry may comprise control circuitry. For example, the control circuit may generate the control signal in response to a feedback signal. The feedback signal may be generated by measuring (e.g., comparing) a signal generated in response to a quantity generated at least partially in response to the control signal.

In some electronic circuits, the feedback signal may be generated by amplifying a signal generated in response to an amount generated in response to the control signal (e.g., amplifying a voltage difference between respective conductors of a differential signal). The stability and accuracy of such control circuits depends on the delay (e.g., delay) of the circuitry used to generate the feedback signal. In general, reducing the power consumption of circuitry used to generate the feedback signal may increase the delay time and/or reduce the accuracy of the feedback signal.

In contrast, increasing the power consumption of the circuitry used to generate the feedback signal may reduce the delay time and/or increase the accuracy of the feedback signal. However, increasing the power consumption of the circuitry used to generate the feedback signal may result in reduced operating characteristics, such as increased power consumption and increased heat dissipation (e.g., which may require remedial cooling), larger components (e.g., for greater power ratings), reduced battery life (e.g., which may additionally require greater energy storage), and/or increased need for line power for active cooling.

Some electronic systems may include an amplifier (e.g., which may include at least one transistor) that may be arranged to actively control a source current in response to an input signal voltage. Some examples of amplifiers may be arranged as comparators. For a given source current (e.g., for powering the comparator), the comparator typically responds quickly to small voltage changes of the first and second input signals. Also, due to the time during which the common node settles to an appropriate (e.g., ideal) value, the comparator typically responds more slowly to larger voltage variations that may be present in the first and second input signals. Increasing the source current output of the current source used to power the comparator may increase the speed and/or accuracy of the comparator. However, increasing the source current of the comparator also increases the power consumption of the comparator. Increasing the power consumption of the comparator may make the comparator design unsuitable for at least some lower power systems.

Example comparators described herein may be arranged to compare a first input signal voltage with a second input signal voltage and generate an output signal (e.g., a single-ended or complementary output signal) in response to the comparison. The example comparator may selectively increase power during some input conditions that may otherwise degrade performance (e.g., increase latency and/or decrease output accuracy).

FIG. 1 is a schematic diagram of an example comparator 100 for low power response to input signal fluctuations. Comparator 100 includes a first stage 110, a replica input transistor pair 120, an Aux _ bias generator 130, a current switch 140, a second stage 150, and a third stage 160. In at least one implementation, the comparator 100 is arranged to compare a pair of differential input signals and selectively add current to a common node of a differential amplifier when an undercurrent condition of the common node is detected.

The first stage 110 is an amplifier having an input transistor pair 112 and a current mirror 115. The input transistor pair may comprise PMOS (P-type metal oxide semiconductor) transistors such as transistors Ql and Q2, with transistors Q1 and Q2 including a common node (e.g., common source node 114) coupled to at least a first current source I1. In other examples, transistors Q1 and Q2 are different types of transistors. The current mirror includes NMOS (N-type metal oxide semiconductor) transistors Q3 and Q4, and resistors R1 and R2 (e.g., for generating a Replica _ load _ CG signal used to bias the common gate of Q3 and Q4). The drains of Q3 and Q4 are coupled to the drains of Q1 and Q2, respectively. Resistors R1 and R2 (e.g., arranged as a voltage divider) are coupled in series between respective drains of Q3 and Q4 (e.g., where the drains are coupled as first and second inputs of a current mirror including Q3 and Q4). In other examples, transistors Q3 and Q4 are different types of transistors. A central node 113 (e.g., a voltage dividing node) between resistors R1 and R2 is coupled to bias respective control terminals of Q3 and Q4 (e.g., to commonly bias gates of Q3 and Q4).

The first stage 110 is a differential amplifier coupled to receive input signals differentially, such as a positive input signal (INP) and a negative input signal (INM). Signal INP and signal INM control the current flowing through Q1 and Q2, respectively. The voltage of the common source node 114 is generated in response to a current supplied by a first current source (e.g., current source I1) and in response to a current selectively controlled by transistors Q1 and Q2. Under some conditions (e.g., caused by voltage variations of the input signal), an undercurrent condition of the common source node 114 may occur, such that the voltage rise of the common node may be delayed and/or cause erroneous output of the comparator 100.

Replica input transistor pair 120 is a replica circuit of input transistor pair 112. For example, the replica input transistor pair 120 includes PMOS transistors Q5 and Q6, which may be the same size or otherwise scaled to determine (e.g., detect, mimic, simulate, and/or simulate) the performance of the input transistor pair 112 (e.g., at least one operating characteristic of Q1 and/or Q2). The source nodes of Q5 and Q6 are coupled to the common source node 114, and the gates of Q4 and Q6 are coupled to signals INP and INM, respectively. In this arrangement, the replica input transistor pair 120 can be responsive to the same (or similar) contemporaneous input conditions experienced by the input transistor pair 112. For example, the replica input transistor pair may detect a voltage drop at the common node, where the detected voltage drop is generated in response to a rise in the input signal (e.g., signal INP or INM).

The output of the Replica input transistor pair 120 (e.g., the commonly coupled drains of Q5 and Q6) is a Replica signal (e.g., a Replica _ load) that is used to indicate (e.g., emulate) the contemporaneous response of the input transistor pair 112. The replica signal may be coupled along a feedback path to generate a feedback signal (e.g., Aux bias) for controlling the selective addition of the current described herein to the common source node 114 via the current switch 140. For example, during a current starvation condition, the output current (e.g., tail current) of the replica input transistor pair 120 decreases, which indicates a current starvation condition. In response to a decrease in the tail current of the replica input transistor pair 120, the Aux _ bias feedback signal may be asserted such that the current flowing through the drain of Q7 contributes supplemental charge to the common source node 114.

Aux _ bias generator 130 is coupled to receive the output of replica input transistor pair 120. The Aux _ bias generator 130 includes a current source I2, an NMOS transistor Q8, and an NMOS transistor Q9. Transistor Q8 is biased by a normalized cascode (ncas) control signal and Q9 is biased by a normalized bias (nbias) control signal. The respective control signal voltage is selected such that Aux _ bias generator 130 asserts the Aux _ bias signal in response to a decrease in current of the Replica _ load signal (and de-asserts the Aux _ bias signal when the Replica _ load signal indicates that the undercurrent condition of common source node 114 has decreased).

When the signal Replica load indicates an insufficient current condition of the common source node 114, less current is added to the current flowing through the drain of Q9 (with the current otherwise flowing through Q9 being coupled from I2 via Q8). In response to less current being added to the current flowing through Q9, the voltage at the source of Q8 (e.g., of node Aux _ bias) drops, causing PMOS transistor Q7 to be turned on.

The current switch 140 includes Q7 and a resistor R3. The resistor R3 is a current source for coupling a limited current to be selectively coupled into the common source node 114 through Q7. Node Aux _ bias is coupled to a control terminal (e.g., gate) of Q7. Transistor Q7 is arranged to selectively apply current to the common source node 114 in response to the Aux _ bias voltage. In at least one example, current source I1 is a first current source, current source R3 (e.g., which is coupled to the VDD power rail) is a second current source, and the first and second current sources are coupled in parallel between the power rail and the common node.

The second stage 150 is a second stage amplifier including PMOS transistors Q10 and Q11 and NMOS transistors Q12 and Q13. The second stage amplifier is coupled to convert a differential input received from the first stage amplifier to a single ended output of the second stage amplifier. Transistor Q10 is the master transistor and transistor Q11 is the slave transistor. The master and slave transistors are arranged as a current mirror for generating a second stage output signal in response to a first stage output signal (e.g., a first stage differential output signal). For example, the current mirror (Q10 and Q11) transistors are biased in response to the first stage output negative signal (1st _ stage _ out _ minus signal), while the second stage output signal (2nd _ stage _ output signal) is generated in response to the 1st _ stage _ out _ plus signal and in response to the current supplied by Q11. The second stage 150 may be arranged as a differential input to a single ended output converter. In another example (not shown), the second stage 150 may be arranged to have a differential output, such that the comparator 100 may be arranged to have a differential output.

Third stage 160 is an amplifier (e.g., a buffer and/or an output stage) arranged to quantize the second stage output (e.g., analog signal 2nd _ stage _ output) and output a signal (e.g., a digital signal) indicative of the comparison result of the differential input signal pair. For example, the third stage may include an odd number of inverters for buffering and inverting the second stage output to generate an output signal as the comparator output (Comp _ Out).

In some examples, the low power responsive comparator includes an input transistor pair (e.g., input transistor pair 112) arranged to receive first and second input signals (e.g., voltages that may vary over time). The input transistor pair may include a first transistor (e.g., Q1) and a second transistor (e.g., Q2). A first current terminal (e.g., source or drain) of the first transistor is coupled to a first current terminal of the second transistor and a common node (e.g., common source node 114). A control terminal (e.g., gate) of the first transistor is coupled to a first input signal, and a control terminal of the second transistor is coupled to a second input signal.

A first current source (e.g., a normally-on current source I1) includes a current output coupled to a common node such that, for example, the first current source provides a first current coupled through the common node to respective current terminals of the first and second transistors. (the term "source" need not refer to the source terminal of a PMOS or NMOS transistor and may refer to a positive or negative current supply depending on the context.)

The transistors of the input transistor pair may individually control the respective currents in response to an input signal coupled to the control terminals of the transistors of the input transistor pair. In an example, each transistor of an input transistor pair may be arranged to independently control (e.g., by varying the current carried between the source and drain terminals in response to a control signal) a portion of the source current supplied from a common node of the input transistor pair.

In an example, respective sources of the input transistor pair are coupled to a common node, and respective drains of the input transistor pair are coupled to respective drain nodes. Thus, voltage variations of the respective first and second input voltages may control respective magnitudes of first and second currents, where the first and second currents respectively flow from the source to the drain (or, for example, from the drain to the source) of the respective transistors of the input transistor pair.

An example low power responsive comparator (e.g., comparator 100) described herein may include replica circuitry (e.g., replica input transistor pair 120 circuitry) for indicating (e.g., copying or emulating) the response of the input transistor pair to changes in the first and second input signals. The replica circuit can include a replica input transistor pair coupled to receive current from a common node supplying current to the input transistor pair. Duplicate input transistor pairs need not be instantiated (e.g., physically fabricated) using the same precise design features of each transistor of the input transistor pair; for example, the transistors of the replica input pair may be scaled such that the replica circuit may emulate the scaled response of the input transistor pair.

An example replica input transistor pair can include third and fourth transistors. A first current terminal of the third transistor is coupled to a first current terminal of the fourth transistor and a common node. A second current terminal of the third transistor is coupled to a second current terminal of the fourth transistor and the feedback signal node. A control terminal of the third transistor is coupled to the first input signal and a control terminal of the fourth transistor is coupled to the second input signal.

As described herein, a replica input transistor pair may emulate an input transistor pair. For example, the Replica input transistor pair may generate a Replica signal (e.g., at the Replica _ load node of FIG. 1) indicating (e.g., emulating) the contemporaneous response of the input transistor pair. The replica signal may be arranged to generate a feedback signal (e.g., the Aux _ bias signal of fig. 1) generated by the input transistor pair (e.g., generated at the common source node 114) for indicating a current starvation condition of the common node.

The replica input transistor pair can detect (e.g., by emulation of the input transistor pair) an undercurrent response of the input transistor pair because, for example, the replica input transistor pair is coupled to (or a buffered input derived from) a similar input coupled to control a first transistor pair (e.g., an input transistor pair).

The undercurrent response is the response of the input transistor pair (e.g., input transistor pair 112) to the current supplied by the first current source and to the first and second input signals. For example, there may be (e.g., cause or generate) an undercurrent condition in a node between two transistors, where a first transistor supplies current to the node, and the capacitance of the node (and the current conducted away from the node by a second transistor) blocks the voltage change of the node.

To determine the undercurrent response, the second current terminals of the third and fourth transistors are coupled to the feedback signal node to generate a combined current. The combined current is an indication of determined performance (e.g., a replay _ load signal) and is coupled to a feedback signal node to generate a feedback signal (e.g., an Aux _ bias signal) for controlling a current switch (e.g., current switch 140).

The current switch includes a first current terminal coupled to the power rail, a second current terminal coupled to the common source node, and a control terminal coupled to the feedback signal node. The current switch is arranged to selectively couple current into the common node in response to an indication of determined performance. A bias generator (e.g., Aux _ bias generator 130) may generate a feedback signal (e.g., a bias signal) in response to the enabled indication. The feedback signal controls (e.g., activates and/or regulates) a current switch (e.g., a boost current source such as current switch 140). For example, the bias generator is arranged to assert a bias signal to activate the current switch in response to a decrease in the indicated current received from the feedback signal node.

Thus, there is a feedback loop such that, for example, a current switch regulates (e.g., selectively provides in response to a feedback signal node) the coupling of the second current (e.g., the amplified current) to the common node. The feedback signal may include a signal generated in an associated feedback path, such as a control signal for selectively controlling a current switch.

The current switch may be coupled to generate (e.g., amplify and/or inject) a controlled boost current to dynamically amplify the source current used to power the input transistor pair. The source current for powering the input transistor pair may be selectively applied by controlling the addition of a boost current (e.g., as regulated by a current switch) to the common source node of the input transistor pair. Selectively amplifying the source current used to power the input transistor pair may save power that would otherwise be depleted by providing, for example, a fixed magnitude source current (e.g., of the first current source) to avoid a current starved response of the common source node of the input transistor pair.

The amplified source current is coupled to first and second current terminals of the input transistor pair. In an example configuration, a second current terminal (e.g., drain or source) of the first transistor may be coupled to a first input of the second stage of the comparator and a second current terminal of the second transistor may be coupled to a second input of the second stage of the comparator. In an example configuration, the output signal of the second stage (e.g., an analog output signal) may be quantized (e.g., converted to a digital value) and coupled as the output signal of the comparator (e.g., as a digital output). As described herein, selective amplification of the common node source current may help reduce latency and output errors while maintaining low power consumption of the low power responsive comparator described herein.

Selective amplification of the common node source current used to power the input transistor pair may reduce quiescent current otherwise consumed by the input transistor pair and reduce latency (e.g., as described herein with respect to fig. 1, 3, 5, and 7). Furthermore, selective amplification of the source current may increase amplifier accuracy and eliminate some kinds of parasitic comparator errors (e.g., as described herein with respect to fig. 6).

The undercurrent response of the common source node of the comparator 100 may be shown by disabling the turn-on of the current switch 140 in the simulation. For example, when the current switch 140 is disabled in the simulation, the delay caused by the insufficient current common source node is shown (e.g., as described herein with respect to fig. 2, 4, and 6), and the output error caused by the insufficient current common source node is shown (e.g., as described herein with respect to fig. 6). The simulation is performed using a simulation program such as SPICE (simulation program with integrated circuit emphasis) to mathematically generate a response of the modeling circuit to input signal fluctuations.

FIG. 2 is a waveform diagram of an example simulation of a disabled low power response of an example comparator to a large input signal transition. Example simulation 200 includes waveforms for showing example operations of portions of comparator 100 described above with reference to fig. 1. Example waveforms include waveform INM210 (e.g., the "input negative" signal coupled to the gate of Q2 of fig. 1), waveform INP 220 (e.g., the "input positive" signal of Q1), waveform Comp _ Out 230 (e.g., the "comparator output" signal of third stage 160), waveform Source240 (e.g., of Node Common _ Source _ Node coupled to respective sources of transistors Q1, Q2, Q5, and Q6 and to the drain of Q7), and waveform Aux _ bias 250 (e.g., the gate coupled to Q7). The low power enhanced response of the example comparator to large input signal transitions may be disabled in response to the analog parameters (e.g., the feedback signal for generating the low power response may be disabled in the simulation 200 by coupling the Aux _ bias node to 3.9 volts via an ideal switch).

In simulation 200, which is used to illustrate the undercurrent response of comparator 100 to large input signal transitions, waveform INM210 is initially asserted at ground potential (e.g., 0 volts) and waveform INP 220 is initially asserted at about 2.90 volts. Because the magnitude of waveform INP 220 is greater than the magnitude of waveform INM210 (e.g., in a steady-state condition), waveform Comp _ Out 230 is initially a logic one (e.g., a logic high level, represented herein as a voltage greater than 1.42 volts, for example).

Waveform Source240 indicates that the voltage of the common Source node 114 is initially driven to approximately 1.2 volts in response to current supplied by a first current Source (e.g., current Source I1), and in response to current selectively controlled by transistors Q1 and Q2. For example, waveform Source240 is driven to approximately 1.2 volts in response to waveform INM210 being at ground potential (e.g., it strongly biases Q2 to make it conduct), in response to waveform INP 220 being at approximately 2.90 volts (e.g., it moderately biases Q1 to make it conduct), and in response to the commonly controlled current mirrors of Q3 and Q4 (e.g., they are commonly biased via the resistor network of R1 and R2).

The waveform Aux _ bias 250 is initially driven to a value of about 3.90 volts in response to the current source I2. The low power enhanced response of the example comparator to large input signal transitions may be disabled in response to the analog parameters (e.g., the feedback signal for generating the low power response may be disabled in the simulation 200 by coupling the Aux _ bias node to 3.9 volts via an ideal switch).

During operation of the comparator 100, the feedback signal of the replica input transistor pair 120 circuit may be a voltage generated in response to a "tail" current of the replica input transistor pair 120 circuit. In simulation 200, the feedback signal is decoupled from waveform Aux _ bias 250 (e.g., as a function of the input parameters of simulation 200) (when transistor Q8 is in an off state). The feedback signal is disabled (e.g., by turning off Q8 in response to the simulation 200 input parameters) so that, for example, the response of the comparator 100 with disabled low power enhancement can be seen. Without enabling the low power selected current boost described in the example, the simulation 200 of the comparator 100 shows a long delay (e.g., approximately 230 nanoseconds) for the voltage of the common Source node 114 (e.g., the waveform Source240) to rise to a steady state level.

The waveform Aux _ bias 250 is coupled to a control terminal (e.g., gate) of the transistor Q7. The transistor Q7 is arranged as a programmable (e.g., programmable in response to a gate voltage) current source for selectively applying current to the common source node 114. In simulation 200, transistor Q7 is biased (in response to the simulation 200 input) so as not to selectively apply current to the common source node 114 (e.g., apply current in response to a feedback signal generated by the replica input transistor pair 120 circuitry). Because the waveform Aux _ bias 250 is about 3.90 volts, the PMOS transistor Q7 is in an off state so that no boost current is injected into the common source node 114 (e.g., of Q1 and Q2) by the current source Q7.

At 10 microseconds into simulation 200, waveform INM210 is driven (e.g., as an input parameter to simulation 200) to experience a large voltage transition 212 from ground potential to a voltage of about 2.92 volts (e.g., which is close to-but greater than-the contemporaneous voltage of waveform INP 220). The transition 212 of the waveform INM210 causes transients 222 and 252 (e.g., via parasitic coupling and/or "ground bounce").

In response to transition 212, the gate voltage of transistor Ql is raised to about 2.92 volts. Thus, the gate voltage of Q1 (after transition 212) is higher than the contemporaneous gate voltage of Q2. The current source I1 is designed to supply current at a low maximum value (e.g., by design to save power). The low level of the maximum current may result in an undercurrent response that contributes to the delay (e.g., delay) in the voltage rise (during transition 242) of the common source node 114. The waveform Source240 during transition 242 rises (e.g., slowly) in response to the limited current supplied by current Source I1, the common Source node 114 capacitance, and the current drawn by the current mirror including transistors Q3 and Q4.

The parasitic conditions of the structure forming the common source node 114 (e.g., of Ql and Q2) prevent the voltage of the common source node 114 from rising (e.g., momentarily rising). Thus, the slew rate of transition 242 is limited and the rising of waveform Source240 to about 3.6 volts is achieved with a delay of about 200 nanoseconds. (in the simulations described below with respect to FIG. 3, the low power enhanced response may reduce the delay in the voltage rise of the common source node 114 by 140 nanoseconds for similar characteristics of the waveform INM210 and the waveform INP 220).

In simulation 200, waveform Comp _ Out 230 switches (e.g., switches to low) in response to transition 212 of waveform INM210 to a voltage greater than the contemporaneous voltage of waveform INP 220. In response to transition 212, waveform Comp _ Out 230 switches from a logic one to a logic zero (where the logic zero is represented as a ground voltage and the logic one is represented as a level of approximately 1.42 volts). The waveform Comp _ Out 230 switches to a logic zero during transition 232, which reaches a logic zero level at time 202 (e.g., approximately 10.33 microseconds).

At time 202, the simulation 200 approaches a steady state response. Waveform INM210 is about 2.92 volts and waveform INP 220 is about 2.90 volts. After transition 242, waveform Source240 is maintained at a voltage of approximately 3.6 volts. Because the feedback control of the replica input transistor pair 120 circuit is disabled, the waveform Aux _ bias 250 is maintained at a voltage of approximately 3.90 volts.

The delay of comparator 100 shown in simulation 200 may be measured from the beginning of transition 212 of waveform INM210 to the end of transition 232 of waveform Comp _ Out 230. When so measured, the delay of comparator 100 in simulation 200 is about 330 nanoseconds, where simulation 200 includes disabling feedback control of replica input transistor pair 120 circuitry. In the simulation described below with respect to fig. 3, where feedback control of the replica input transistor pair 120 circuit is not disabled as a simulation parameter, the delay of the comparator 100 in the simulation 200 is reduced to approximately 124 nanoseconds.

FIG. 3 is a waveform diagram of an example simulation of a low power enhanced response of an example comparator to a large input signal transition. The example simulation 300 includes waveforms for showing example operations of portions of the comparator 100 described above with reference to fig. 1. Example waveforms include: waveform INM310, waveform INP320, waveform Comp _ Out 330, waveform Source 340, and waveform Aux _ bias 350. The low power enhanced response of the example comparator to large input signal transitions is enabled in simulation 300.

In simulation 300, which is used to illustrate the current boost response of comparator 100 to large input signal transitions, waveform INM310 is initially asserted at ground potential (e.g., 0 volts) and waveform INP320 is initially asserted at about 2.90 volts. Because the magnitude of waveform INP320 is greater than the magnitude of waveform INM310 (e.g., in a steady state condition), waveform Comp _ Out 330 is initially a logic one (e.g., 1.42 volts).

The waveform Source 340(Common _ Source _ Node) indicates that the voltage of the Common Source Node 114 is initially driven to approximately 1.2 volts in response to the current supplied by the first current Source (e.g., current Source I1), and in response to the current selectively controlled by transistors Q1 and Q2. For example, in response to waveform INM310 being at ground potential (e.g., it strongly biases Q2 to make it conduct), in response to waveform INP320 being at about 2.90 volts (e.g., it moderately biases Q1 to make it conduct), and in response to the commonly controlled current mirror of Q3 and Q4, waveform Source 340 is driven to about 1.2 volts.

At 10 microseconds into simulation 300, waveform INM310 is driven to undergo a large voltage transition 312 from ground potential to a voltage of approximately 2.92 volts. Transition 312 of waveform INM310 causes transient 322.

In response to transition 312, the gate voltage of transistor Ql is raised to approximately 2.92 volts. Thus, the gate voltage of Q1 (after transition 312) is higher than the contemporaneous gate voltage of Q2. The low level of the current maximum of the current source I1 may result in an undercurrent response, which contributes to the delay in the voltage rise (during transition 342) of the common source node 114. The waveform Source 340 during transition 342 rises (e.g., slowly) in response to the limited current supplied by current Source I1, the common Source node 114 capacitance, and the current drawn by the current mirror including transistors Q3 and Q4.

The replica input transistor pair 120 (e.g., coupled to the inputs of the input transistor pair 112) detects an undercurrent condition of the common source node 114. In response to the undercurrent condition, the tail current of the replica input transistor pair 120 is reduced. In response to a decrease in the tail current of the replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage at the source of Q8 (waveform Aux _ bias350) drops (e.g., as transition 352). For example, transition 352 begins approximately 40 nanoseconds after the onset of the undercurrent condition.

As the waveform Aux _ bias350 falls, the PMOS transistor (e.g., switch) Q7 increases conductivity and adds current (via current switch 140) to the common source node 114. Adding current to the common Source node 114 via the Q7 of the current switch 140 reduces the current starvation condition at the common Source node 114 and speeds up the rise of the waveform Source 340 during the transition 342.

As the waveform Source 340 rises to a steady-state level (e.g., 3.6 volts) at about the end of the transition 342, the undercurrent condition of the common Source node 114 is alleviated. The replica input transistor pair 120 detects a decrease in the current starved state of the common source node 114 and increases the tail current of the replica input transistor pair 120. In response to an increase in the tail current of replica input transistor pair 120, more current is added to the current flowing through the drain of Q9. In response to more current being added to the current flowing through Q9, the voltage of the source of Q8 (e.g., waveform Aux _ bias350) rises (e.g., as transition 354). For example, transition 354 begins in response to waveform Source 340 rising to a steady-state level (e.g., which occurs approximately 98 nanoseconds after the beginning of the undercurrent condition in simulation 300).

As the waveform Aux _ bias350 rises during the transition 354, the PMOS transistor (e.g., switch) Q7 decreases conductivity and gradually adds less current (e.g., supplied from the current switch 140) to the common source node 114. The waveform Aux _ bias350 rises to a steady-state level (e.g., 3.6 volts) after the comparator 100 responds (e.g., responds correctly) to the relative change in the first input signal that occurred at 10 microseconds into the simulation 300.

In simulation 300, waveform Comp _ Out 330 switches in response to transition 312 of waveform INM310 to a voltage greater than the contemporaneous voltage of waveform INP 320. In response to transition 312, waveform Comp _ Out 330 switches from a logic one to a logic zero. Waveform Comp _ Out 330 switches to a logic zero during transition 332, which reaches a logic zero level at time 302 (e.g., approximately 10.124 microseconds).

After time 302, the simulation 300 approaches a steady state response. Waveform INM310 is about 2.92 volts and waveform INP320 is about 2.90 volts. Waveform Source 340 reaches and maintains a steady state voltage of approximately 3.60 volts after transition 342.

The delay of comparator 100 shown in simulation 300 can be measured from the beginning of transition 312 of waveform INM310 to the end of transition 332 of waveform Comp _ Out 330. When so measured, the delay of the comparator 100 in the simulation 300 is reduced to approximately 124 nanoseconds by the described current boost added by the current switch 140. The delay of simulation 300 is 176 nanoseconds faster than the delay of 330 nanoseconds for simulation 200, where the feedback control of the replica input transistor to 120 circuitry is disabled (e.g., in response to simulation 200 parameter input).

FIG. 4 is a waveform diagram of an example simulation of a disabled low power enhancement response of an example comparator to a small input signal transition. Example simulation 400 includes waveforms for showing example operations of portions of comparator 100 described above with reference to fig. 1. Example waveforms include waveform INM410, waveform INP 420, waveform Comp _ Out 430, waveform Source440, and waveform Aux _ bias 450. The low power enhanced response of the example comparator to small input signal transitions may be disabled in response to the analog parameters (e.g., the feedback signal for generating the low power response may be disabled in the analog 400 by coupling the Aux _ bias node to 3.9 volts via an ideal switch.

In simulation 400, which illustrates the undercurrent response of comparator 100 to small input signal transitions, waveform INM410 is initially asserted (e.g., prior to time 402) at a potential of 2.88 volts and waveform INP 420 is initially asserted at about 2.90 volts. Because the magnitude of waveform INP 420 is greater than the contemporaneous magnitude of waveform INM410 (e.g., in a steady state condition), waveform Comp _ Out 430 is initially a logic one (e.g., 1.42V).

The waveform Source440 indicates that the voltage of the Common Source Node 114 is initially driven to approximately 3.55 volts in response to the current supplied by the first current Source (e.g., current Source I1), and in response to the current selectively controlled by transistors Q1 and Q2. For example, in response to waveform INM410 being at 2.88 volts, in response to waveform INP 420 being at about 2.90 volts, and in response to the commonly controlled current mirror of Q3 and Q4 (e.g., which are commonly biased via the resistor network of R1 and R2), waveform Source440 is driven to about 3.55 volts.

In response to current source I2, waveform Aux _ bias 450 is driven to a value of approximately 3.90 volts. The low power enhanced response of the example comparator to small input signal transitions may be disabled in response to the analog parameters (e.g., the feedback signal for generating the low power response may be disabled in the analog 400 by coupling the Aux _ bias node to 3.9 volts via an ideal switch).

During operation of the comparator 100, the feedback signal of the replica input transistor pair 120 circuit may be a voltage generated in response to the tail current of the replica input transistor pair 120 circuit. In simulation 400, the feedback signal is decoupled from the modulated waveform Aux _ bias 450 (e.g., as a function of input parameters of simulation 400). The feedback signal is disabled (e.g., by turning off Q8 in response to the simulation 400 input parameters) so that, for example, the response of comparator 100 with disabled low power enhancement can be seen. Without enabling the low power selected current boost enhancement described in the example, the simulation 400 of the comparator 100 shows a delay (e.g., approximately 40 nanoseconds) for the voltage of the common Source node 114 (e.g., the waveform Source 440) to rise to a steady state level.

The waveform Aux _ bias 450 is coupled to a control terminal (e.g., gate) of the transistor Q7. The transistor Q7 is arranged as a programmable (e.g., programmable in response to a gate voltage) current source for selectively applying current to the common source node 114. In the simulation 400, the transistor Q7 is disabled (in response to the simulation 400 input) from selectively applying current to the common source node 114 (e.g., applying current in response to a feedback signal generated by the replica input transistor pair 120 circuit). Because the waveform Aux _ bias 450 is about 3.90 volts, the PMOS transistor Q7 is in an off state so that no boost current is injected into the common source node 114 (e.g., of Q1 and Q2) by the current source Q7.

At 10 microseconds into the simulation 400, the waveform INM410 is driven (e.g., as an input parameter to the simulation 400) to undergo a small voltage transition 412 from a voltage of 2.88 volts to a voltage of approximately 2.92 volts. Transition 412 of waveform INM410 causes transients 422 and 452.

In response to the transition 412, the gate voltage of the transistor Q2 is raised to approximately 2.92 volts. Thus, the gate voltage of Q2 (after transition 412) is higher than the contemporaneous gate voltage of Q1. The current source I1 is designed to supply current at a low maximum value (e.g., to save power). The low level of the maximum current may result in an undercurrent response, which contributes to the delay in the voltage rise (during transition 442) of the common source node 114. The waveform Source440 during transition 442 rises (e.g., slowly) in response to the limited current supplied by current Source I1, the common Source node 114 capacitance, and the current drawn by the current mirror including transistors Q3 and Q4.

The parasitic conditions of the structure forming the common source node 114 (e.g., of Ql and Q2) prevent the voltage of the common source node 114 from rising (e.g., momentarily rising). Thus, the slew rate of transition 442 is limited and the rising of waveform Source440 to about 3.6 volts is achieved with a delay of about 40 nanoseconds.

In simulation 400, waveform Comp _ Out 430 switches in response to transition 412 of waveform INM410 to a voltage greater than the contemporaneous voltage of waveform INP 420. In response to transition 412, waveform Comp _ Out 430 switches from a logic one to a logic zero. Waveform Comp _ Out 430 switches to a logic zero during transition 432, which reaches a logic zero level approximately 1 nanosecond before time 404 (e.g., where time 404 is 10.056 microseconds).

At time 404, the simulation 400 approaches a steady state response. Waveform INM410 is about 2.92 volts and waveform INP 420 is about 2.90 volts. After transition 442, waveform Source440 is maintained at a voltage of approximately 3.57 volts. Because the feedback control of the replica input transistor pair 120 circuit is disabled, the waveform Aux _ bias 450 is maintained at a voltage of about 3.90 volts.

The delay of comparator 100 shown in simulation 400 may be measured from the beginning of transition 412 of waveform INM410 to the end of transition 432 of waveform Comp _ Out 430. When so measured, the delay of the comparator 100 in the simulation 400 is about 55 nanoseconds, with the simulation 400 including disabling feedback control of the replica input transistor pair 120 circuit. In the simulation described below with respect to fig. 5 (where feedback control of the replica input transistor pair 120 circuit is not disabled as a simulation parameter), the delay of comparator 100 in simulation 500 is similar to the delay of comparator 100 in simulation 400.

FIG. 5 is a waveform diagram of an example simulation of a low power enhanced response of an example comparator to a small input signal transition. Example simulation 500 includes waveforms for showing example operations of portions of comparator 100 described above with reference to fig. 1. Example waveforms include: waveform INM510, waveform INP 520, waveform Comp _ Out 530, waveform Source 540, and waveform Aux _ bias 550. The low power enhanced response of the example comparator to small input signal transitions is enabled in simulation 500. In the initial condition, the waveform Aux _ bias is a logic one, such that transistor Q7 is turned off, and such that Q7 does not (initially) inject a boost current into the common source node 114.

In simulation 500, which is used to illustrate the current boost response of comparator 100 to small input signal transitions, waveform INM510 is initially asserted (e.g., prior to time 502) at a potential of 2.88 volts and waveform INP 520 is initially asserted at about 2.90 volts. Because the magnitude of waveform INP 520 is greater than the magnitude of waveform INM510 (e.g., in a steady state condition), waveform Comp _ Out 530 is initially a logic one (e.g., 1.42 volts).

Waveform Source 540 indicates that the voltage of the Common Source Node 114 is initially driven (e.g., prior to time 502) to approximately 3.55 volts in response to the current supplied by the first current Source (e.g., current Source I1), and in response to the current selectively controlled by transistors Q1 and Q2. For example, waveform Source 540 is driven to approximately 3.55 volts in response to waveform INM510 being at 2.88 volts, in response to waveform INP 520 being at approximately 2.90 volts, and in response to the commonly controlled current mirror of Q3 and Q4.

At 10 microseconds into simulation 500 (e.g., at time 502), waveform INM510 is driven to undergo a small voltage transition 512 from a voltage of 2.88 volts to a voltage of approximately 2.92 volts. Transition 512 of waveform INM510 causes a transient 522.

In response to the transition 512, the gate voltage of transistor Q2 is raised to approximately 2.92 volts. Thus, the gate voltage of Q2 (after transition 512) is higher than the contemporaneous gate voltage of Q1. The low level of the current maximum of current source I1 may result in an undercurrent response, which contributes to the delay in the voltage rise (during transition 542) of common source node 114. The waveform Source 540 during transition 542 rises in response to the limited current supplied by current Source I1, the common Source node 114 capacitance, and the current drawn by the current mirror including transistors Q3 and Q4.

The replica input transistor pair 120 (e.g., coupled to the inputs of the input transistor pair 112) detects an undercurrent condition of the common source node 114. In response to the undercurrent condition, the tail current of the replica input transistor pair 120 is reduced. In response to a decrease in the tail current of the replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage at the source of Q8 (waveform Aux _ bias550) drops (e.g., as transition 552). For example, transition 552 begins approximately 10 nanoseconds after the start of the undercurrent condition.

As the waveform Aux _ bias550 falls, the PMOS transistor (e.g., switch) Q7 increases conductivity and adds current (from current switch 140) to the common source node 114. In simulation 500, the resulting undercurrent condition is light (e.g., due to small voltage variations of waveform INM510, and the added current from current switch Q7 to common Source node 114 is not readily able to significantly accelerate (on the scale shown in FIG. 5) the rise of waveform Source 540 during transition 542. As described below, transition 552 is not readily able to significantly turn on transistor Q7 to add supplemental current to common Source node 114.

In simulation 500, waveform Comp _ Out 530 switches in response to transition 512 of waveform INM510 to a voltage greater than the contemporaneous voltage of waveform INP 520. In response to transition 512, waveform Comp _ Out 530 switches from a logic one to a logic zero. The waveform Comp _ Out 530 switches to a logic zero during transition 532, which reaches a logic zero level at time 504 (e.g., approximately 10.055 microseconds).

At time 504, waveform INM510 of simulation 500 is about 2.92 volts, waveform INP 520 is about 2.90 volts, and waveform Source 540 reaches and maintains a steady state voltage of about 3.6 volts after transition 542.

The delay of comparator 100 shown in simulation 500 may be measured from the beginning of transition 512 of waveform INM510 to the end of transition 532 of waveform Comp _ Out 530. As shown in fig. 5, the delay of comparator 100 in simulation 500 may be compared to the delay of comparator 100 in simulation 400 (described above).

FIG. 6 is a waveform diagram of another example simulation of a disabled low power enhancement response of an example comparator to a large input signal transition. The example simulation 600 includes waveforms for showing example operations of portions of the comparator 100 described above with reference to fig. 1. Example waveforms include waveform INM 610, waveform INP620, waveform Comp _ Out630, waveform Source640, waveform Aux _ bias650, waveform 1st _ stage _ Out _ plus 660, waveform 1st _ stage _ Out _ minus 670, and waveform 2nd _ stage _ output 680. Transistor Q8 is turned off by the simulation 600 parameters to disable the feedback signal (e.g., via waveform Aux _ bias 650) for controlling the current boost of Q7.

Simulation 600 shows the undercurrent response of the common source node 114 of the comparator 100 to a change in the first input signal to a first value substantially close to a second value of the second input signal. For example, when the difference between the first input signal value and the second input signal value is a value within the input offset of an amplifier receiving the first and second input signals, the first input signal value is substantially close to the second input signal value.

In simulation 600, waveform INM 610 is initially asserted (e.g., before the 10 microsecond mark of simulation 600) at ground potential (e.g., 0 volts), while waveform INP620 is initially asserted at about 2.90 volts. Because the initial magnitude of waveform INP620 is greater than the contemporaneous magnitude of waveform INM 610 (e.g., at an initial steady-state condition), waveform Comp _ Out630 is initially a logic one (e.g., 1.42V). The waveform Comp _ Out630 is generated in response to the difference between the waveform 1st _ stage _ Out _ minus 670 and the waveform 1st _ stage _ Out _ plus 660, where the difference is indicated by the waveform 2nd _ stage _ output 680 described below.

The waveform Source640 indicates that the voltage of the Common Source Node 114 is initially driven to a low voltage (e.g., 1.2 volts) in response to current supplied by a first current Source (e.g., current Source I1), and in response to current selectively controlled by transistors Q1 and Q2. For example, in response to the waveform INM 610 being grounded, the waveform Source640 is driven to a low voltage (e.g., 1.2 volts) in response to the waveform INP620 being at about 2.90 volts and in response to the common controlled current mirror of Q3 and Q4 (e.g., which are commonly biased via the resistor network of R1 and R2).

In response to current source I2, waveform Aux _ bias650 is driven to a value of approximately 3.90 volts. The low power enhanced response of the example comparator to large input signal transitions may be disabled in response to the analog parameters (e.g., the feedback signal for generating the low power response may be disabled in the analog 600 by coupling the Aux _ bias node to 3.9 volts via an ideal switch).

During operation of the comparator 100, the feedback signal of the replica input transistor pair 120 circuit may be a voltage generated in response to the tail current of the replica input transistor pair 120 circuit. In simulation 600, the feedback signal is decoupled from waveform Aux _ bias650 (e.g., in response to simulation 600 input parameters). The feedback signal is disabled (e.g., in response to the simulation 600 input parameters) so that, for example, the response of the comparator 100 with disabled low power enhancement can be seen. For example, a defect of "robust" operation (e.g., sensitivity to producing erroneous output) may be demonstrated by an example spurious output pulse of waveform Comp _ Out630 (e.g., where the spurious pulse includes transitions 632 and 634).

The waveform Aux _ bias650 is coupled to a control terminal (e.g., gate) of the transistor Q7. The transistor Q7 is arranged as a programmable (e.g., programmable in response to a gate voltage) current source for selectively applying current to the common source node 114. In the simulation 600, the transistor Q7 is disabled (in response to the simulation 600 input) from selectively applying current to the common source node 114 (e.g., applying current in response to a feedback signal generated by the replica input transistor pair 120 circuit). Because the waveform Aux _ bias650 is about 3.90 volts throughout the simulation 600, the PMOS transistor Q7 is in an off state so that no boost current is injected by the current source Q7 into the common source node 114 (e.g., of Q1 and Q2).

Waveform 1st _ stage _ out _ plus 660 and waveform 1st _ stage _ out _ minus 670 are generated in response to a first input signal and a second input signal, respectively. For example, the waveform 1st _ stage _ out _ plus 660 is initially about 169 millivolts (in response to the waveform INM 610), and the waveform 1st _ stage _ out _ minus 670 is about 550 millivolts (in response to the waveform INP 620).

The second stage 150 generates a waveform 2nd _ stage _ output 680 in response to the difference between the waveform 1st _ stage _ out _ plus 660 and the waveform 1st _ stage _ out _ minus 670 (where the waveform 1st _ stage _ out _ plus 660 and the waveform 1st _ stage _ out _ minus 670 are first stage 110 output signals). The difference between the initial voltage values of the waveform 1st _ stage _ out _ plus 660 and the waveform 1st _ stage _ out _ minus 670 is greater than the input offset of the second stage 150 input transistors Q12 and Q13 (e.g., this results in a reduced probability of output errors). When the difference between the initial voltage values of waveform 1st _ stage _ out _ plus 660 and waveform 1st _ stage _ out _ minus 670 is not greater than the input offset of the second stage 150, the second stage is susceptible to outputting an erroneous output (as described below).

In response to the difference in the input signals, waveform 2nd _ stage _ output 680 is initially a voltage (e.g., ground or near ground potential) that indicates that the magnitude of waveform 1st _ stage _ out _ plus 660 is less than waveform 1st _ stage _ out _ minus 670. The waveform 2nd _ stage _ output 680 value (e.g., initially at ground potential) is received by the third stage 160 and quantized by the input gate of the third stage 160 (e.g., initially as an input logic zero). The third stage 160 buffers and inverts the input logic zero and outputs the buffered inverted value as the waveform Comp _ Out630 (e.g., which is initially a logic one).

At 10 microseconds into the simulation 600, the waveform INM 610 is driven (e.g., as a simulation 600 input parameter) to undergo a large voltage transition 612 from ground potential to a voltage of approximately 2.88 volts. The voltage at which waveform INM 610 rises to approximately 2.88 volts is a level that is still less than the magnitude of waveform INP620 (e.g., 2.90 volts), so waveform Comp _ Out630 is not expected to switch (e.g., change output logic state) under ideal conditions (e.g., no logic errors). Transition 612 of waveform INM 610 causes transients 622, 652, 662, 672, and 682.

During transition 612, the gate voltage of transistor Q2 rises to approximately 2.88 volts. After transition 612, the gate voltage of Q2 remains lower than the contemporaneous gate voltage of Q1 (e.g., such that waveform Comp _ Out630 cannot properly switch). The current Source I1 is designed to supply current to Common _ Source _ Node (e.g., waveform Source 640) at a low maximum current (e.g., by design to conserve power). The low level of the maximum current results in an undercurrent response (e.g., in response to transition 612), which contributes to the delay in the voltage rise of transition 642.

The current starvation induced delay of the common source node 114 of the first stage 110 (e.g., which occurs during the transition 642) also contributes to the stable delay of the waveforms 1st _ stage _ out _ plus 660 and 1st _ stage _ out _ minus 670. For example, after transients 662 and 672, the voltages of waveforms 1st _ stage _ out _ plus 660 and 1st _ stage _ out _ minus 670 converge to a difference that is less than the input offset of the second stage 150 amplifier (which may result in an erroneous output of the second stage 150).

The convergence of waveforms 1st _ stage _ out _ plus 660 and 1st _ stage _ out _ minus 670 to a low voltage (e.g., near ground) helps ensure that NMOS transistors Q12 and Q13 are biased more negatively so that transistors Q12 and Q13 do not conduct strongly. When transistors Q12 and Q13 do not conduct strongly during the undercurrent condition (e.g., during transition 642), waveform 2nd _ stage _ output 680 rises (e.g., gradually rises in response to the drain current generated by the current mirror formed by transistors Q10 and Q11).

As waveform 2nd _ stage _ output 680 rises in simulation 600, the second stage 150 output (logically erroneously) reaches a voltage that can be quantized to a logical one by third stage 160 (e.g., 900 millivolts). Third stage 160 inverts the received logic one value, which causes third stage 160 to switch low at transition 632. The transition of the third stage 160 output to switching is erroneous because the input signals (e.g., waveform INM 610 and waveform INP 620) having the largest magnitudes of the first and second input signals do not change. Such errors may result in incorrect processing of the data such that incorrect processing may result in corrupted output data or other processing errors. When the comparator is used in a feedback loop to control an external process (e.g., external to the comparator 100), for example, the external process may interrupt the stability and accuracy of the feedback control signal, including signals within the safety critical system.

Waveform Source640 reaches a steady state value (e.g., a near steady state value) at the end of transition 642. At the end of transition 642 (e.g., at time 602), the undercurrent condition is alleviated, causing waveform 1st _ stage _ out _ plus 660 and waveform 1st _ stage _ out _ minus 670 to rise. As the waveform 1st _ stage _ out _ plus 660 and the waveform 1st _ stage _ out _ minus 670 rise, at least one of the transistors Q12 and Q13 is more strongly biased (e.g., to increase conductivity). As at least one of transistors Q12 and Q13 is more strongly biased, the output of second stage 150 (e.g., waveform 2nd _ stage _ output 680) drops to a level that can be quantized to a logic zero by third stage 160. The third stage 160 inverts the received logic zero value, which causes the third stage 160 to switch high (e.g., back to the logically correct value) at transition 634. Transition 634 of the third stage 160 output restores the correct output value of comparator 100 (e.g., after the undercurrent condition during transition 642 is alleviated).

At time 604, the simulation 600 approaches a steady state response. Waveform INM 610 is about 2.88 volts and waveform INP620 is about 2.90 volts. After transition 642, waveform Source640 is maintained at a voltage of approximately 3.44 volts. The waveform Aux _ bias650 is maintained at a voltage of about 3.90 volts because the feedback control of the replica input transistor pair 120 circuit is disabled. Waveform 1st _ stage _ out _ plus 660 is about 332 mv, waveform 1st _ stage _ out _ minus 670 is about 394 mv, and waveform 2nd _ stage _ output 680 is about 217 mv.

The delay of comparator 100 during transition 642 may result in erroneous performance (e.g., a logically incorrect output value) during an undercurrent condition encountered, for example, when at least one input signal undergoes a large transition (rather than transitioning to a value indicative of a logically valid transition of comparator 100). Simulation 600 includes disabling feedback control of the replica input transistor pair 120 circuit so that logically incorrect behavior of the comparator under undercurrent conditions can be demonstrated. In simulation 700 (where feedback control of the replica input transistor pair 120 circuit is not disabled as an analog parameter), comparator 100 selectively couples current from a current switch (e.g., current switch 140) into common source node 114 (e.g., to more quickly alleviate a current starvation condition that may otherwise result in the generation of an erroneous output signal).

FIG. 7 is a waveform diagram of another example simulation of an enabled low power enhancement response of an example comparator to a large input signal transition. The example simulation 700 includes waveforms for showing example operations of portions of the comparator 100 described above with reference to fig. 1. Example waveforms include waveform INM 710, waveform INP 720, waveform Comp _ Out730, waveform Source740, waveform Aux _ bias750, waveform 1st _ stage _ Out _ plus760, waveform 1st _ stage _ Out _ minus 770, and waveform 2nd _ stage _ output 780. The low power enhanced response of the example comparator to large input signal transitions is enabled in the simulation 700.

Simulation 700 shows the current starved response of comparator 100 to a voltage transition of a first input signal to a first input signal value within a difference given by the input offset of the amplifier receiving the first and second input signals.

In simulation 700, waveform INM 710 is initially asserted (e.g., before the 10 microsecond mark of simulation 700) at ground potential, while waveform INP 720 is initially asserted at about 2.90 volts. Because the initial magnitude of waveform INP 720 is greater than the contemporaneous magnitude of waveform INM 710 (e.g., in an initial steady-state condition), waveform Comp _ Out730 is initially a logic one (e.g., 1.42V). The waveform Comp _ Out730 is generated in response to the difference between the waveform 1st _ stage _ Out _ minus 770 and the waveform 2nd _ stage _ output780 described below.

The waveform Source740 indicates that the voltage of the Common Source Node 114 is initially driven to a low voltage (e.g., 1.2 volts) in response to the current supplied by the first current Source (e.g., current Source I1), and in response to the current selectively controlled by transistors Q1 and Q2. For example, in response to waveform INM 710 being grounded, waveform Source740 is driven to a low voltage (e.g., 1.2 volts) in response to waveform INP 720 being at about 2.90 volts and in response to the commonly controlled current mirror of Q3 and Q4.

In response to current source I2, waveform Aux _ bias750 is driven to a value of approximately 3.90 volts. The waveform Aux _ bias is not affected by the Replica _ load feedback signal of the Replica input transistor pair 120 circuit because the Replica input transistor pair 120 circuit (in the initial condition) does not detect the undercurrent condition of the common source node 114. Transistor Q8 is biased on in response to signal NCAS ("normalized cascode," shown in fig. 1). When transistor Q8 is in the on state, the feedback path of the feedback signal of the Replica input transistor pair 120 circuit (e.g., including signal Replica _ load, the first and second current terminals of transistor Q8, and signal Aux _ bias) is coupled as a feedback circuit (e.g., for coupling the feedback signal to the common source node 114).

During operation of the comparator 100, the feedback signal of the replica input transistor pair 120 circuit may be a voltage generated in response to the tail current of the replica input transistor pair 120 circuit. In the simulation 700, the feedback signal is coupled to the gate of the transistor Q7 (and to the common source node 114 via the drain of Q7) so that, for example, the response of the replica input transistor pair 120 can be seen. For example, "robust" operation (e.g., insensitivity to producing erroneous outputs from input signals having voltage inputs less than the input offset of the amplifier) can be demonstrated by the absence of spurious output pulses of waveform Comp _ Out730 (see Comp _ Out 630).

The waveform Aux _ bias750 is coupled to a control terminal (e.g., gate) of the transistor Q7. In the simulation 700, the transistor Q7 is enabled (in response to the simulation 700 input) to selectively apply current to the common source node 114 (e.g., in response to a feedback signal generated by the replica input transistor pair 120 circuitry). Because the waveform Aux _ bias750 is initially about 3.90 volts in the simulation 700, the PMOS transistor Q7 is in an off state so that no boost current is injected by the current source Q7 into the common source node 114 (e.g., of Q1 and Q2).

The waveform 1st _ stage _ out _ plus760 and the waveform 1st _ stage _ out _ minus 770 are generated in response to a first input signal and a second input signal, respectively. For example, waveform 1st _ stage _ out _ plus760 is initially about 169 millivolts (in response to waveform INM 710) and waveform 1st _ stage _ out _ minus 770 is about 550 millivolts (in response to waveform INP 720).

In response to the difference in the input signals, waveform 2nd _ stage _ output780 initially indicates that the magnitude of waveform 1st _ stage _ out _ plus760 is less than waveform 1st _ stage _ out _ minus 770. The waveform 2nd _ stage _ output780 value (e.g., initially at ground potential) is received by the third stage 160 and quantized by the input gates of the third stage 160 (e.g., initially as an input logic zero). The third stage 160 buffers and inverts the input logic zero and outputs the buffered inverted value as the waveform Comp _ Out730 (e.g., which is initially a logic one).

At 10 microseconds into the simulation 700, the waveform INM 710 is driven (e.g., as a simulation 700 input parameter) to undergo a large voltage transition 712 from ground potential to a voltage of approximately 2.88 volts. The voltage at which waveform INM 710 rises to about 2.88 volts is a level that is still less than the magnitude of waveform INP 720, so waveform Comp _ Out730 does not switch under ideal conditions (e.g., no errors). The transition 712 of the waveform INM 710 causes transients 722, 762, 772 and 782.

During transition 712, the gate voltage of transistor Ql rises to approximately 2.88 volts. After transition 712, the gate voltage of Q1 remains lower than the contemporaneous gate voltage of Q2 (e.g., such that waveform Comp _ Out730 cannot properly switch). The current source I1 is designed to supply current at a low maximum value (e.g., by design to save power) so that an undercurrent response of the first stage 110 results.

The current starvation induced delay of the common source node 114 of the first stage 110 (e.g., which occurs during the transition 742) also contributes to the stable delay of the waveforms 1st _ stage _ out _ plus760 and 1st _ stage _ out _ minus 770. For example, after transients 762 and 772, the voltages of waveforms 1st _ stage _ out _ plus760 and 1st _ stage _ out _ minus 770 converge to a difference that is less than the input offset of the second stage 150 amplifier (which could otherwise result in an erroneous output of the second stage 150).

The convergence of waveforms 1st _ stage _ out _ plus760 and 1st _ stage _ out _ minus 770 to a low voltage (e.g., near ground) helps ensure that NMOS transistors Q12 and Q13 are biased more negatively so that transistors Q12 and Q13 do not conduct strongly. When transistors Q12 and Q13 do not conduct strongly during the undercurrent condition (e.g., during transition 742), waveform 2nd _ stage _ output780 rises (e.g., gradually rises in response to the drain current generated by the current mirror formed by transistors Q10 and Q11).

As the second stage 150 output (e.g., waveform 2nd _ stage _ output780) rises in the simulation 700, the second stage 150 output is prevented from reaching a voltage that can be quantized by the third stage 160 to a logical one. As described below, the second stage 150 output is prevented from reaching a voltage that would otherwise be quantized to a logic one by the third stage 160. The rise to a logic one threshold of the second stage 150 output is prevented by the current injection selectively coupled through the current switch 140, where the current injection mitigates the undercurrent condition of the common source node 114.

The replica input transistor pair 120 (e.g., coupled to the inputs of the input transistor pair 112) detects an undercurrent condition of the common source node 114. In response to the undercurrent condition, the tail current of the replica input transistor pair 120 is reduced. In response to a decrease in the tail current of the replica input transistor pair 120, less current is added to the current flowing through the drain of Q9. In response to less current being added to the current flowing through Q9, the voltage at the source of Q8 (waveform Aux _ bias750) drops (e.g., as transition 752). For example, transition 752 begins approximately 40 nanoseconds after the start of the undercurrent condition.

As the waveform Aux _ bias750 falls, the PMOS transistor (e.g., switch) Q7 increases conductivity and adds current (selectively supplied via current switch 140) to the common source node 114. Adding current to the common Source node 114 via the current switch Q7 reduces the undercurrent condition at the common Source node 114 and speeds up the rise of the waveform Source740 during the transition 742.

As the waveform Source740 rises to a steady-state level (e.g., 3.6 volts) at about the end of the transition 742, the undercurrent condition of the common Source node 114 is alleviated. The replica input transistor pair 120 detects a decrease in the current starved state of the common source node 114 and the tail current of the replica input transistor pair 120 increases. In response to an increase in the tail current of replica input transistor pair 120, more current is added to the current flowing through the drain of Q9. In response to more current being added to the current flowing through Q9, the voltage of the source of Q8 (e.g., waveform Aux _ bias750) rises (e.g., as transition 754). For example, transition 754 begins in response to waveform Source740 rising to a steady-state level (e.g., which occurs approximately 98 nanoseconds after the beginning of an undercurrent condition in simulation 700).

As the waveform Aux _ bias750 rises during the transition 754, the PMOS transistor (e.g., switch) Q7 decreases conductivity and gradually adds less current (from the current switch 140) to the common source node 114. The waveform Aux _ bias750 rises to a steady-state level (e.g., 3.6 volts) after the comparator 100 responds (e.g., responds correctly) to the relative change in the first input signal that occurred at 10 microseconds into the simulation 700.

At time 704, the simulation 700 approaches a steady state response. Waveform INM 710 is about 2.88 volts and waveform INP 720 is about 2.90 volts. After transition 742, waveform Source740 is maintained at a voltage of approximately 3.44 volts. Because the current switch Q7 is off, the waveform Aux _ bias750 is maintained at a voltage of about 3.90 volts. Waveform 1st _ stage _ out _ plus760 is about 331 millivolts, waveform 1st _ stage _ out _ minus 770 is about 392 millivolts, and waveform 2nd _ stage _ output780 is about 217 millivolts.

In the simulation 700 of the comparator 100, feedback control of the replica input transistor pair 120 circuit detects an undercurrent condition at the common source node 114. In response to an indication of an undercurrent condition generated by the replica input transistor pair 120 circuitry, the current switch 140 selectively couples current from the current switch 140 into the common source node 114, which accelerates the reduction of the undercurrent condition of the common source node 114. Speeding up the reduction of the current starved condition of the common source node 114 prevents the waveforms 1st _ stage _ out _ plus760 and 1st _ stage _ out _ minus 770 from converging to a difference less than the input offset of the second stage 150 amplifier. Inhibiting the convergence of waveforms 1st _ stage _ out _ plus760 and 1st _ stage _ out _ minus 770 to a difference less than the input offset of the second stage 150 amplifier increases the robustness of the comparator against generating erroneous output signals.

Fig. 8 is a schematic diagram of another example Aux _ bias generator for the low power enhancement response of an example comparator. An example Aux _ bias generator 830 of circuit 800 includes transistors Q80, Q81, Q82, and Q83, and an inverter 832. For example, Aux _ bias generator 830 is similar to Aux _ bias generator 130 described above.

In at least one implementation, PMOS transistors Q80 and Q81 are arranged as a current mirror, with current flowing through Q80 controlling current flowing through Q81. The current flowing through Q80 is controlled by the bias signal nbias such that NMOS transistor Q81 is biased to conduct (e.g., turn on the channel for carrying) a first current "a" (e.g., xA) of magnitude "x". The Replica _ load _ CG signal (e.g., the gate control signals of Q3 and Q4 generated by the first stage 110) is coupled to bias the NMOS transistor Q83 in response to the Replica input transistor pair 120 circuit to detect a current starvation condition.

When the Replica _ load _ CG signal indicates that there is no undercurrent condition, transistor Q83 is biased to conduct a current (1.5xA) that is 50% greater than the current supplied by transistor Q81, for example. Because the biased current capacity of Q83 is greater than the biased current capacity of Q81, the voltage developed between the respective drains of Q81 and Q83 is quantized by inverter 832 to logic zero. In response, inverter 832 outputs a logic one such that PMOS transistor Q7 is turned off and current switch 140 does not inject additional current into common source node 114.

When the Replica _ load _ CG signal indicates that a current starvation condition exists, the transistor Q83 is biased to not conduct (and/or conduct a small amount of current, such as to cause the inverter 832 to switch). When transistor Q83 is biased to be non-conducting, the voltage developed between the respective drains of Q81 and Q83 is quantized by inverter 832 to a logical one. In response, inverter 832 outputs a logic zero such that PMOS transistor Q7 is turned off and current switch 140 is coupled to inject additional current into common source node 114 (e.g., so the undercurrent condition of common source node 114 is alleviated).

For example, the Replica _ load _ CG signal may indicate that a current starvation condition exists by decreasing the voltage level of the Replica _ load _ CG signal (e.g., such that NMOS transistor Q83 is arranged to be less conductive and/or turned off). When the voltage of the Replica load signal decreases to a voltage level selected to indicate that a current starvation condition exists, Aux _ bias generator 830 is coupled to assert a bias signal to activate current switch 140 (e.g., in response to a decrease in the indicated voltage received from the repica _ load _ CG signal node). Thus, the current of the replica load signal may be reduced in response to the voltage drop of the common source node.

FIG. 9 is a flow diagram of an example method of response of an example low power comparator to input signal fluctuations. The process 910 of the example method 900 includes generating, by the first stage, a first stage output signal in response to an input signal. The input signal is coupled to control a first current coupled from a first current source through a common node to generate a first stage output signal.

Process 920 includes generating a replica load signal by a replica input transistor pair in response to an input signal and in response to a current received from a common node. In an example, the replica load signal is generated in response to detecting an undercurrent response of a pair of input transistors arranged to generate the first stage output signal. In another example, the replica load signal is generated in response to a simulation of the input transistor pair.

Process 930 includes selectively coupling a second current from a second current source to the common node in response to the replica load signal.

Various examples of comparators (and example operations thereof) with lower power consumption and reduced latency are described herein with respect to the figures. The figure of merit for lower power consumption and reduced latency may be the product of the consumed power and the reduced latency (e.g., power delay). In the various simulations described hereinabove, a three-fold improvement in comparator delay for the same power has been observed. In cases where the input signal is within a narrow margin, the synergy of the increase in robustness with reduced power and latency (e.g., as described above with respect to simulation 700) may extend the figure of merit by more than a factor of three.

Modifications are possible in the described examples, and other examples are possible within the scope of the claims.