阅读说明：本技术 上电掉电复位电路 (Power-on and power-off reset circuit ) 是由 王野 谢程益 于 2020-07-03 设计创作，主要内容包括：本发明涉及集成电路技术领域,提供了一种上电掉电复位电路,其包括：掉电处理模块,连接于供电端与地之间,根据供电端提供的输入电压生成第一控制信号；上电处理模块,连接于供电端与地之间,具有接入第一控制信号的第一输入端和接入第二控制信号的第二输入端,以及用于提供电压调节信号的第一输出端；功率管,连接于前述第一输出端和地之间,根据电压调节信号生成复位信号。由此可以确保在上电和掉电时,位于该上电掉电复位电路输出端的功率管均能正常工作,提高电路的可靠性和稳定性。(The invention relates to the technical field of integrated circuits, and provides a power-on and power-off reset circuit, which comprises: the power failure processing module is connected between the power supply end and the ground and generates a first control signal according to the input voltage provided by the power supply end; the power-on processing module is connected between the power supply end and the ground, and is provided with a first input end connected with a first control signal, a second input end connected with a second control signal, and a first output end used for providing a voltage regulation signal; and a power tube connected between the first output end and the ground and generating a reset signal according to the voltage regulation signal. Therefore, the power tube positioned at the output end of the power-on and power-off reset circuit can work normally when power is on or off, and the reliability and stability of the circuit are improved.)

1. A power-on-power-down reset circuit, comprising:

the power failure processing module is connected between a power supply end and the ground and generates a first control signal according to input voltage provided by the power supply end;

the power-on processing module is connected between the power supply end and the ground, and is provided with a first input end connected with the first control signal, a second input end connected with the second control signal, and a first output end used for providing a voltage regulating signal;

and the power tube is connected between the first output end and the ground and generates a reset signal according to the voltage regulating signal.

2. The power-on-power-down reset circuit of claim 1, wherein the power-down processing module comprises:

the first transistor and the first capacitor are connected between the power supply end and the ground in series, the first end of the first transistor is connected with the power supply end, the second end of the first transistor is connected with the first capacitor, and the second end of the first transistor is connected with the control end of the first transistor;

a second transistor, a first resistor, and a third transistor connected in series between a second terminal of the first transistor and ground, the second transistor and a control terminal of the third transistor being connected to the power supply terminal in common,

the connection node of the first resistor and the third transistor is used for providing the first control signal.

3. The power-on-power-down reset circuit of claim 2, wherein the substrate end of the first transistor is electrically connected to the substrate end of the second transistor, the substrate end of the first transistor is connected to the second end of the first transistor, and the substrate end of the second transistor is connected to the first end of the second transistor.

4. The power-on-power-down reset circuit of claim 1, wherein the power-on processing module comprises:

a fourth transistor, a fifth transistor and a sixth transistor connected in series between the power supply terminal and the ground, wherein a control terminal of the fifth transistor is used as the second input terminal for accessing the second control signal;

a seventh transistor and a third capacitor connected in series between the power supply terminal and ground, a first terminal of the seventh transistor being connected to the power supply terminal, a control terminal of the seventh transistor being connected to a connection node of the fourth transistor and the fifth transistor, the connection node of the seventh transistor and the third capacitor being configured to provide a third control signal;

the second capacitor is connected between the first end and the control end of the seventh transistor;

the control end of the eighth transistor is connected with a connection node of the seventh transistor and the third capacitor and is connected to the third control signal, and the control end of the ninth transistor is electrically connected with the control end of the fifth transistor and is connected to the second control signal.

5. The power-on-power-down reset circuit of claim 4, wherein the power-on processing module further comprises:

and the tenth transistor is connected to two ends of the third capacitor in parallel, a first end of the tenth transistor is connected with a connection node of the seventh transistor and the third capacitor, a second end of the tenth transistor is grounded, and a control end is used as the first input end to be connected into the first control signal.

6. The power-on-power-down reset circuit of claim 5, wherein the power-on processing module further comprises:

a fourth capacitor and a third resistor connected in series between the power supply terminal and the ninth transistor.

7. The power-on-power-down reset circuit according to claim 1, wherein a first end of the power transistor is used as an output end of the power-on-power-down reset circuit to provide the reset signal, a second end of the power transistor is grounded, and a control end of the power transistor is connected to the first output end and is connected to the voltage regulation signal.

8. The power-on-power-down reset circuit of claim 7, wherein the power transistor is a bipolar junction transistor.

9. The power-on-power-down reset circuit of claim 4, wherein the first transistor, the second transistor, the fourth transistor, the seventh transistor, and the eighth transistor are all P-type metal oxide semiconductor field effect transistors.

10. The power-on-power-down reset circuit of claim 5, wherein the third transistor, the fifth transistor, the ninth transistor and the tenth transistor are all N-type metal oxide semiconductor field effect transistors.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a power-on and power-off reset circuit.

Background

The power-on and power-off reset circuit is basically built in the current chip. Most of Reset chips are effective in low level, and in the Power-on process, when the Power supply voltage is less than the Power on Reset (VPOR), the output Power tube is not turned on, so that the output is in an unstable state, and error indication may be generated to affect the whole chip system.

Although the traditional power-on and power-off reset circuit has many types, in the setting of most GPIO (general purpose input/output ports) of single-chip microcomputers, two different output modes are provided for selection, one is open drain (open drain) output, and the other is push-pull (push pull) output.

Fig. 1 is a schematic diagram of a power-on/power-off reset circuit in the prior art, and as shown in fig. 1, the power-on/power-off reset circuit is a push-pull output, which can output high/low levels, and an output terminal is generally connected to a digital device. The power-on and power-off reset circuit comprises a PMOS tube T11 and an NMOS tube T12 which are sequentially connected In series between a power supply end VDD and the ground, the grids of the PMOS tube T11 and the NMOS tube T12 are connected together to be connected with an input signal In, the connection node of the drain of the PMOS tube T11 and the drain of the NMOS tube T12 provides an output signal Out, when the grid inputs 0, the high-side PMOS tube T11 is conducted, the low-side NMOS tube T12 is switched off In a high-resistance mode, and 1 is output; when the gate inputs 1, the high-side PMOS transistor T11 is turned off with high impedance, the low-side NMOS transistor T12 is turned on, and 0 is output (this circuit does not require an external pull-up circuit, and the rising edge change is steep).

Fig. 2 is a schematic diagram of another power-on/power-off reset circuit in the prior art, and as shown in fig. 2, the power-on/power-off reset circuit is an open-drain output, and a collector of a transistor connected with a pull-up resistor is used as an output terminal, so that the power-on/power-off reset circuit is suitable for current-type driving and has strong current absorption capability. The power-on and power-off reset circuit comprises a pull-up resistor R21 and an NMOS tube T22 which are sequentially connected In series between a power supply end VDD and the ground, wherein the grid of the NMOS tube T22 is connected with an input signal In, the connection node of the pull-up resistor R21 and the drain of the NMOS tube T22 is used for providing an output signal Out, and when the grid inputs 0, the NMOS tube T22 is not conducted, the drain is In high-resistance disconnection, and 1 is output. When the gate inputs 1, the drain and the source of the NMOS transistor T22 are turned on, and 0 is output (an external pull-up circuit is required, and the rising edge changes relatively slowly).

In the power-on process of the chip with any one of the two output forms, when the input signal In connected to the gate of the output MOS transistor does not reach the turn-on voltage (e.g., 700mV), the output signal out is In an unstable state, which may give an error indication signal to a subsequent circuit.

Although the MOS transistor with low on-state voltage (low Vth, lvt) is used as the output transistor to reduce the aforementioned turn-on voltage and power-on-reset Voltage (VPOR) to some extent, an additional layer is added in the chip manufacturing process to increase the cost, and meanwhile, the MOS transistor with low on-state voltage at high temperature has a risk of leakage and is poor in reliability.

Disclosure of Invention

In order to solve the technical problems, the invention provides a power-on and power-off reset circuit which can ensure that a power tube at an output end can work normally when power is on and off, and improve the reliability and stability of the circuit.

The invention provides a power-on and power-off reset circuit, which comprises:

the power failure processing module is connected between the power supply end and the ground and generates a first control signal according to the input voltage provided by the power supply end;

the power-on processing module is connected between the power supply end and the ground, and is provided with a first input end connected with the first control signal, a second input end connected with the second control signal, and a first output end used for providing a voltage regulating signal;

and a power tube connected between the first output end and the ground and generating a reset signal according to the voltage regulation signal.

Preferably, the power down processing module includes:

the first transistor and the first capacitor are connected between the power supply end and the ground in series, the first end of the first transistor is connected with the power supply end, the second end of the first transistor is connected with the first capacitor, and the second end of the first transistor is connected with the control end of the first transistor;

a second transistor, a first resistor and a third transistor connected in series between the second terminal of the first transistor and ground, the control terminals of the second and third transistors being commonly connected to the power supply terminal,

the connection node of the first resistor and the third transistor is used for providing the first control signal.

Preferably, the substrate end of the first transistor is electrically connected to the substrate end of the second transistor, the substrate end of the first transistor is connected to the second end of the first transistor, the substrate end of the second transistor is connected to the first end of the second transistor, and the first end of the second transistor is connected to the second end of the first transistor.

Preferably, the power-on processing module includes:

a fourth transistor, a fifth transistor and a sixth transistor connected in series between the power supply terminal and the ground, wherein a control terminal of the fifth transistor is used as the second input terminal for accessing the second control signal;

a seventh transistor and a third capacitor connected in series between the power supply terminal and the ground, wherein a first terminal of the seventh transistor is connected to the power supply terminal, a control terminal of the seventh transistor is connected to a connection node of the fourth transistor and the fifth transistor, and the connection node of the seventh transistor and the third capacitor is used for providing a third control signal;

the second capacitor is connected between the first end and the control end of the seventh transistor;

and the control end of the eighth transistor is connected with the connection node of the seventh transistor and the third capacitor and is connected with the third control signal, and the control end of the ninth transistor is electrically connected with the control end of the fifth transistor and is connected with the second control signal.

Preferably, the power-on processing module further includes:

and a tenth transistor connected in parallel to two ends of the third capacitor, wherein a first end of the tenth transistor is connected to a connection node between the seventh transistor and the third capacitor, a second end of the tenth transistor is grounded, and a control end is used as the first input end to access the first control signal.

Preferably, the power-on processing module further includes:

and the fourth capacitor and the third resistor are connected in series between the power supply terminal and the ninth transistor.

Preferably, a first end of the power transistor is used as an output end of the power-on/power-off reset circuit to provide the reset signal, a second end of the power transistor is grounded, and a control end of the power transistor is connected to the first output end and is connected to the voltage regulation signal.

Preferably, the power transistor is a bipolar junction transistor.

Preferably, the first transistor, the second transistor, the fourth transistor, the seventh transistor, and the eighth transistor are all P-type metal oxide semiconductor field effect transistors.

Preferably, the third transistor, the fifth transistor, the ninth transistor, and the tenth transistor are all N-type metal oxide semiconductor field effect transistors.

The invention has the beneficial effects that: the embodiment of the invention provides a power-on and power-off reset circuit, which comprises: the power-down processing module is connected between the power supply end and the ground and can generate a first control signal according to the input voltage provided by the power supply end; the power-on processing module is connected between the power supply end and the ground, generates a voltage regulating signal according to the first control signal and the second control signal provided by the power-down processing module and provides the voltage regulating signal to the control end of the power tube connected with the power-on processing module, and the power tube controls the on-off state of the power tube according to the voltage regulating signal and releases a reset signal to enable a connected chip or a chip where a circuit is located to work normally. Therefore, the power tube serving as the output end in the power-on and power-off reset circuit can work normally when power is on or off, the risk of electric leakage at high temperature when an MOS tube is used as the power tube in the prior art is avoided, and the reliability and stability of the circuit are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a prior art power-on-power-down reset circuit;

FIG. 2 shows a schematic diagram of another prior art power-on-power-down reset circuit;

fig. 3 illustrates a schematic structural diagram of a power-on/power-off reset circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating one embodiment of a power-on-power-down reset circuit of FIG. 3;

fig. 5 shows an operation timing diagram of signals in the power-on power-down reset circuit in fig. 4.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The present invention will be described in detail below with reference to the accompanying drawings.

Fig. 3 is a schematic structural diagram of a power-on and power-down reset circuit according to an embodiment of the present invention, and fig. 4 is a circuit structural diagram of an implementation manner of the power-on and power-down reset circuit in fig. 3.

Referring to fig. 3 and 4, a power-on/power-down reset circuit 100 provided by the present invention includes: the power-down processing module 110, the power-up processing module 120 and the power tube M2, wherein the power-down processing module 110 is connected between a power supply terminal and ground, and generates a first control signal VA according to an input voltage VDD provided by the power supply terminal; the power-on processing module 120 is connected between the power supply terminal and the ground, and has a first input terminal connected to the first control signal VA, a second input terminal connected to the second control signal VG, and a first output terminal providing the voltage regulation signal VB; the power transistor M2 is connected between the first output terminal and ground, and generates the reset signal Vo according to the voltage regulation signal VB.

Further, a first end of the power transistor M2 is used as an output end of the power-on/power-off reset circuit 100 for providing the reset signal Vo, a second end is grounded, and a control end is connected to the first output end and is connected to the voltage regulation signal VB.

Further, the power transistor M2 is a bipolar junction transistor (also called bipolar junction transistor, BJT). It will be appreciated that in this embodiment, the power transistor M2(BJT) is connected in common with the emitter, which has the advantage that small variations in the voltages applied to the base and emitter terminals can cause significant variations in the current between the emitter and collector. Here, when the base of the power transistor M2(BJT) is used as the input terminal, connected to the first output terminal, and connected to the voltage regulation signal VB, and the collector is used as the output terminal to provide the reset signal Vo, and the equivalent principle analysis is performed by using thevenin's theorem, the power transistor M2(BJT) can be regarded as a voltage-controlled current source, or as a current-controlled voltage source.

In addition, the collector-emitter current and the base current of the bipolar transistor have approximately linear characteristics in the range of the forward amplification region (or simply, the amplification region). Looking into the left side of the power transistor M2(BJT) port network, the input impedance at the base decreases to the base resistance, thus reducing the load capability requirement of the previous stage circuit, and by this property, the input current (or voltage) can be amplified.

In this embodiment, the power down processing module 110 includes: transistor T1, capacitor C1, transistor T2, resistor R1 and transistor T3.

Specifically, a transistor T1 and a capacitor C1 are connected in series between a power supply terminal and ground, a first terminal of the transistor T1 is connected to the power supply terminal, a second terminal is connected to the capacitor C1, and the second terminal is connected to the control terminal of the transistor T1 itself; the transistor T2, the resistor R1 and the transistor T3 are sequentially connected in series between the second end of the transistor T1 and the ground, and the control end of the transistor T2 and the control end of the transistor T3 are connected to the power supply end in common; the connection node of the resistor R1 and the transistor T3 is used for providing the first control signal VA.

Further, the substrate terminal (bulk) of the transistor T1 is electrically connected to the substrate terminal (bulk) of the transistor T2, while the substrate terminal (bulk) of the transistor T1 is connected to the second terminal thereof, the substrate terminal (bulk) of the transistor T2 is connected to the first terminal thereof, and the first terminal of the transistor T2 is connected to the second terminal of the transistor T1.

In this embodiment, the power-on processing module 120 includes: a transistor T4, a transistor T5, a transistor M1, a capacitor C2, a transistor T6, a capacitor C3, a resistor R2, a transistor T7, and a transistor T8.

Specifically, the transistor T4, the transistor T5, and the transistor M1 are sequentially connected in series between the power supply terminal and the ground, and the control terminal of the transistor T5 is used as the second input terminal for receiving the second control signal VG; the transistor T6 and the capacitor C3 are connected in series between the power supply terminal and the ground, and the connection node of the transistor T6 and the capacitor C3 is used for providing the third control signal VC; the capacitor C2 is connected between the first terminal and the control terminal of the transistor T6, the first terminal of the transistor T6 is connected to the power supply terminal, and the control terminal of the transistor T6 is connected to the connection node of the transistor T4 and the transistor T5; the resistor R2, the transistor T7 and the transistor T8 are connected in series between the power supply terminal and the ground, the control terminal of the transistor T7 is connected to the connection node between the transistor T6 and the capacitor C3, the third control signal VC is connected thereto, and the control terminal of the transistor T8 is electrically connected to the control terminal of the transistor T5, and the second control signal VG is connected thereto.

Further, the transistor M1 is a Bipolar Junction Transistor (BJT).

Further, the power-on processing module 120 further includes a transistor T9, the transistor T9 is connected in parallel to two ends of the capacitor C3, a first end of the transistor T9 is connected to a connection node between the transistor T6 and the capacitor C3, a second end of the transistor T9 is grounded, and a control end of the transistor T9 serves as a first input end of the power-on processing module 120 to receive the first control signal VA.

Further, the power-on processing module 120 further includes: a capacitor C4 and a resistor R3, the capacitor C4 and the resistor R3 being connected in series between the supply terminal and the transistor T8.

Further, the Transistor T1, the Transistor T2, the Transistor T4, the Transistor T6, and the Transistor T7 are all P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

Further, the Transistor T3, the Transistor T5, the Transistor T9, and the Transistor T8 are all N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

In the embodiment of the invention, the Power tube M2(BJT) and the NMOS tube T8 are arranged in parallel, and the Power tube M2(BJT) has lower starting voltage, so that the Power tube can be started earlier in the Power-on process, the output unstable state area is reduced, the Power-on-Reset Voltage (VPOR) is reduced, and the base voltage of the Power tube M2(BJT) is processed, so that the Power tube M2(BJT) can normally work in Power-on and Power-off processes.

Fig. 5 shows an operation timing diagram of signals in the power-on power-down reset circuit in fig. 4.

Specifically, referring to fig. 4 and 5, the power-on/power-off reset circuit of the above embodiment operates as follows:

in the time period from T1 to T2, when the input voltage VDD is powered on, the second control signal VG (e.g., a pulse signal provided by the reference source generation circuit) is in a low level state, the first control signal VA is in a low level state, at this time, in the power-on processing module 120, the transistor T5, the transistor T9, and the transistor T8 are all in an off state, and since the capacitor C2 is connected between the control terminal (gate) and the power supply terminal of the transistor T6, the gate potential of the transistor T6 does not reach the on voltage during power-on, the transistor T6 is in an off state, and at this time, no current charges the capacitor C3, the voltage of the third control signal VC at this node, that is, the gate voltage potential of the transistor T7 is close to the ground potential, and the transistor T7 is in an on state. The transistor T6 is in the off state, the base of the power transistor M2(BJT) is charged high, the power transistor M2(BJT) is turned on, and the collector-to-emitter pull-down current makes the output reset signal Vo at the ground potential when it is turned on.

By processing (e.g., connecting to a low potential) the bulk terminal (bulk) of the transistor T7, the bulk terminal (bulk) voltage is lower than the source terminal (first terminal) voltage thereof, so that the turn-on voltage Vth becomes smaller, and thus the transistor T7 can be turned on earlier.

However, the on voltage Vth of the transistor T7 makes the transistor T7 be turned on and in an unstable state, so that the resistor R3 and the capacitor C4 connected in series between the control terminal (base) of the power transistor M2(BJT) and the input voltage VDD are connected to the base of the power transistor M2(BJT), so that the power transistor M2(BJT) is turned on more fully, and the response speed of the output reset signal Vo reaching a low level state is faster.

In the time period from t2 to t3, after the input voltage is powered up, the entire circuit is in a steady state.

In a time period from T3 to T4, when the whole circuit is built up, the second control signal VG is turned to a high level state, the transistor T5 and the transistor T8 are turned on, and the transistor M1(BJT) is turned on, at this time, the current flowing through the transistor M1(BJT) is greater than the current flowing through the transistor T4, so that the level of the gate of the transistor T6 is limited to a low level, the transistor T6 is turned on, the potential of the gate of the transistor T7 is pulled up to the input voltage VDD by charging the capacitor C3, then the transistor T7 is turned to an off state, and as the second control signal VG is turned to a high level state, the transistor T8 is turned on, the base of the power transistor M2(BJT) is turned to a low level state, the power transistor M2(BJT) is turned off, and the high level reset signal Vo is output.

When the input voltage VDD is powered down in a time period from t4 to t5, the second control signal VG is in a high level state, and the input voltage VDD is greater than or equal to the turn-on voltage of the NMOS transistor, the turn-off state of the power transistor M2(BJT) is not changed.

In the time period from t5 to t6, the second control signal VG is changed to a low level state, and the first control signal VA obtains a small spike voltage with rapid change through charging and discharging of the capacitor C1 during the power-down process of the input voltage VDD. When the input voltage VDD drops to ground, the power down processing module 110 will drain the charge stored in the capacitor C3 to a clean state, so as to ensure that the gate potential of the transistor T7 is at a low level state when the next power-on occurs, and the power transistor M2(BJT) is turned on quickly, and releases the reset signal, so that the connected chip or the chip where the circuit is located operates normally.

The substrate end (bulk) of the transistor T1 is connected to the second end (drain end) thereof, the substrate end (bulk) of the transistor T2 has the same potential as the substrate end (bulk) of the transistor T1, the transistor T3 is turned on during normal operation, the transistor T2 is turned off because the gate voltage of the transistor T2 is higher than the source voltage, and the transistor T6 does not function when the second control signal VG is in a low level state. When the input voltage VDD is powered down, the potential of the substrate terminal (bulk) of the transistor T2 and the potential of the substrate terminal (bulk) of the transistor T1 are held by the capacitor C1, and the falling speed thereof is slower than the input voltage VDD, so that the transistor T2 is turned on, charges the node to which the first control signal VA is supplied, and pulls up the voltage of the first control signal VA for a short time. The transistor T9 is turned on to discharge the charge stored in the capacitor C3 with a large current, so that after the power is turned off, the gate voltage of the transistor T7 returns to a zero level state, and the power-up processing module 120 can operate normally when the power-up processing module is powered up next time.

In summary, the power-on/power-down reset circuit provided in the embodiment of the present invention includes: the power-down processing module is connected between the power supply end and the ground and can generate a first control signal according to the input voltage provided by the power supply end; the power-on processing module is connected between the power supply end and the ground, generates a voltage regulating signal according to the first control signal and the second control signal provided by the power-down processing module and provides the voltage regulating signal to the control end of the power tube connected with the power-on processing module, and the power tube controls the on-off state of the power tube according to the voltage regulating signal and generates a reset signal. Therefore, when power is on or off, the power tube serving as the output end in the power-on and power-off reset circuit can release the reset signal, so that the connected chip or the chip where the circuit is located can work normally, the leakage risk of the MOS tube serving as the power tube at high temperature in the prior art is avoided, and the reliability and stability of the circuit are improved.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.

Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.