阅读说明：本技术 复位电路 (Reset circuit ) 是由 雷宇超 吕洁洁 陈光胜 于 2021-11-17 设计创作，主要内容包括：一种复位电路,包括：偏置电流产生单元、电压检测单元、电压生成单元、比较单元以及输出单元,其中：偏置电流产生单元,其输出端与电压生成单元、电压检测单元以及比较单元耦接,适于根据预设的电源电压生成偏置电流并输出；电压检测单元,其输出端与电压生成单元耦接,适于在检测到电源电压变化时,控制电压生成单元的第一输出端的输出电压发生相应变化；电压生成单元,其第一输出端与比较单元的第一输入端耦接,其第二输出端与比较单元的第二输入端耦接；电压生成单元的第二输出端适于输出参考电压；比较单元,其输出端与输出单元的输入端耦接；输出单元,其输出端输出复位信号。上述方案能够实现电路系统的快速复位。(A reset circuit, comprising: bias current produces unit, voltage detection unit, voltage generation unit, comparing element and output unit, wherein: the output end of the bias current generating unit is coupled with the voltage generating unit, the voltage detecting unit and the comparing unit and is suitable for generating and outputting bias current according to preset power supply voltage; the output end of the voltage detection unit is coupled with the voltage generation unit and is suitable for controlling the output voltage of the first output end of the voltage generation unit to correspondingly change when the change of the power supply voltage is detected; a first output end of the voltage generating unit is coupled with a first input end of the comparing unit, and a second output end of the voltage generating unit is coupled with a second input end of the comparing unit; the second output end of the voltage generating unit is suitable for outputting a reference voltage; the output end of the comparison unit is coupled with the input end of the output unit; and the output end of the output unit outputs a reset signal. The scheme can realize the quick reset of the circuit system.)

1. A reset circuit, comprising: bias current produces unit, voltage detection unit, voltage generation unit, comparing element and output unit, wherein:

the output end of the bias current generating unit is coupled with the voltage generating unit, the voltage detecting unit and the comparing unit, and is suitable for generating and outputting bias current according to preset power supply voltage;

the output end of the voltage detection unit is coupled with the voltage generation unit and is suitable for controlling the output voltage of the first output end of the voltage generation unit to correspondingly change when the change of the power supply voltage is detected;

a first output end of the voltage generating unit is coupled with a first input end of the comparing unit, and a second output end of the voltage generating unit is coupled with a second input end of the comparing unit; the second output end of the voltage generating unit is suitable for outputting a reference voltage;

the output end of the comparison unit is coupled with the input end of the output unit;

and the output end of the output unit outputs a reset signal.

2. The reset circuit according to claim 1, wherein the bias current generating unit includes:

first PMOS pipe, second PMOS pipe, first NMOS pipe and second NMOS pipe, wherein:

the grid electrode of the first PMOS tube is grounded, the drain electrode of the first PMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube is connected with the power supply voltage;

the grid electrode of the second PMOS tube is coupled with the first output end of the bias current generating unit, and the drain electrode of the second PMOS tube is coupled with the first output end of the bias current generating unit and the drain electrode of the second NMOS tube;

the grid electrode of the first NMOS tube is coupled with the second output end of the bias current generating unit and the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded;

and the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.

3. The reset circuit according to claim 1, wherein the voltage detection unit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, third PMOS pipe and first electric capacity, wherein:

the grid electrode and the drain electrode of the third NMOS tube are connected with the power supply voltage, and the source electrode of the third NMOS tube is connected with the upper polar plate of the first capacitor;

the grid electrode of the fourth NMOS tube is coupled with the input end of the voltage detection unit, the drain electrode of the fourth NMOS tube is coupled with the drain electrode of the third PMOS tube, and the source electrode of the fourth NMOS tube is grounded;

the grid electrode of the fifth NMOS tube is coupled with the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube is coupled with the output end of the voltage detection unit, and the source electrode of the fifth NMOS tube is grounded;

the grid electrode of the third PMOS tube is connected with the power supply voltage, and the source electrode of the third PMOS tube is coupled with the source electrode of the third NMOS tube;

the lower plate of the first capacitor is grounded.

4. The reset circuit of claim 3, wherein a substrate of the third PMOS transistor is coupled to a source of the third NMOS transistor.

5. The reset circuit of claim 1, wherein the voltage generation unit comprises: reset signal trigger module and reference voltage generation module, wherein:

the first input end of the reset signal triggering module is coupled with the first input end of the voltage generating unit, the second input end of the reset signal triggering module is coupled with the second input end of the voltage generating unit, and the output end of the reset signal triggering module is coupled with the first output end of the voltage generating unit;

the input end of the reference voltage generation module is coupled with the first input end of the voltage generation unit, and the output end of the reference voltage generation module is coupled with the second output end of the voltage generation unit.

6. The reset circuit of claim 5, wherein the reset signal triggers a module comprising: fourth PMOS pipe, fifth PMOS pipe and second electric capacity, wherein:

the grid electrode of the fourth PMOS tube is coupled with the first input end of the reset signal triggering module, the drain electrode of the fourth PMOS tube is coupled with the source electrode of the fifth PMOS tube, and the source electrode of the fourth PMOS tube is connected with the power supply voltage;

the grid electrode of the fifth PMOS tube is coupled with the drain electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is coupled with the output end of the reset signal triggering module and the second input end of the reset signal triggering module;

and the upper polar plate of the second capacitor is coupled with the second input end of the reset signal triggering module, and the lower polar plate of the second capacitor is grounded.

7. The reset circuit of claim 5, wherein the reference voltage generation circuit comprises: sixth PMOS pipe, sixth NMOS pipe and seventh NMOS pipe, wherein:

the grid electrode of the sixth PMOS tube is coupled with the input end of the reference voltage generating circuit, the drain electrode of the sixth PMOS tube is coupled with the second output end of the reference voltage generating circuit, and the source electrode of the sixth PMOS tube is connected with the power supply voltage;

the grid electrode of the sixth NMOS tube is coupled with the drain electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is also coupled with the drain electrode of the sixth PMOS tube, and the source electrode of the sixth NMOS tube is coupled with the drain electrode of the seventh NMOS tube;

the gate of the seventh NMOS transistor is coupled to the drain thereof, and the source thereof is grounded.

8. The reset circuit of claim 1, wherein the comparison unit comprises: a comparison module and an amplification module, wherein:

the first input end of the comparison module is coupled with the first input end of the comparison unit, the second input end of the comparison module is coupled with the second input end of the comparison unit, the output end of the comparison module is coupled with the input end of the amplification module, and the control end of the comparison module is coupled with the second output end of the current bias unit;

and the output end of the amplifying module is coupled with the output end of the comparing unit.

9. The reset circuit of claim 8, wherein the comparison module comprises: seventh PMOS pipe, eighth NMOS pipe, ninth NMOS pipe and tenth NMOS pipe, wherein:

a seventh PMOS transistor having a gate coupled to a drain thereof, a source connected to the power voltage, and a drain coupled to a drain of the eighth NMOS transistor;

the grid electrode of the eighth PMOS tube is coupled with the grid electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is coupled with the drain electrode of the ninth NMOS tube and the output end of the comparison module;

the gate of the eighth NMOS transistor is coupled to the first input terminal of the comparison module, and the source of the eighth NMOS transistor is coupled to the drain of the tenth NMOS transistor;

the grid electrode of the ninth NMOS tube is coupled with the second input end of the comparison module, and the source electrode of the ninth NMOS tube is coupled with the drain electrode of the tenth NMOS tube;

the gate of the tenth NMOS transistor is coupled to the control terminal of the comparison module, and the source thereof is grounded.

10. The reset circuit of claim 8, wherein the amplification module comprises: a ninth PMOS transistor, wherein:

the ninth PMOS transistor has a gate coupled to the input terminal of the amplifying module, a drain coupled to the output terminal of the amplifying module, and a source connected to the power voltage.

11. The reset circuit of claim 10, wherein the comparison unit further comprises: and the grid electrode of the eleventh NMOS tube is coupled with the control end of the comparison module, the drain electrode of the eleventh NMOS tube is coupled with the drain electrode of the ninth PMOS tube, and the source electrode of the eleventh NMOS tube is grounded.

12. The reset circuit of claim 1, wherein the output unit comprises: an inverter, an input of which is coupled to the input of the output unit, and an output of which is coupled to the output of the inverter.

13. The reset circuit of claim 12, wherein the inverter comprises: a tenth PMOS transistor and a twelfth NMOS transistor, wherein:

a gate of the tenth PMOS transistor is coupled to the input terminal of the inverter, a drain of the tenth PMOS transistor is coupled to the output terminal of the inverter, and a source of the tenth PMOS transistor is connected to the power voltage;

the grid electrode of the twelfth NMOS tube is coupled with the grid electrode of the tenth PMOS tube, the drain electrode of the twelfth NMOS tube is coupled with the drain electrode of the tenth PMOS tube, and the source electrode of the twelfth NMOS tube is grounded.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a reset circuit.

Background

The reset circuit is a module circuit necessary for modern integrated circuit chips, and is a circuit for restoring the circuit to an initial state. The reset circuits are of various types, can independently operate and directly influence the initial state, and are mainly power-on reset and power-off reset. The power-on reset and the power-off reset can ensure that the chip can be reliably reset in a complex electromagnetic environment, and play a key role in the whole circuit system.

The traditional reset circuit generally covers one or two of quick power-on reset, slow power-on reset, quick power-off reset and slow power-off reset, is difficult to consider various power-on and power-off application scenes, and cannot solve the problem of reset reliability after incomplete power-off and power-on. The power-on reset refers to reset generated in the normal process from no power supply to power supply; the power failure reset refers to reset generated in the processes of power supply voltage drop, voltage oscillation and the like.

Disclosure of Invention

The embodiment of the invention solves the technical problem that the reset can not be effectively generated under various power-on and power-off application scenes, and particularly relates to the problem of reset reliability after power-off is not complete and then power-on.

To solve the above technical problem, an embodiment of the present invention provides a reset circuit, including: bias current produces unit, voltage detection unit, voltage generation unit, comparing element and output unit, wherein: the output end of the bias current generating unit is coupled with the voltage generating unit, the voltage detecting unit and the comparing unit, and is suitable for generating and outputting bias current according to preset power supply voltage; the output end of the voltage detection unit is coupled with the voltage generation unit and is suitable for controlling the output voltage of the first output end of the voltage generation unit to correspondingly change when the change of the power supply voltage is detected; a first output end of the voltage generating unit is coupled with a first input end of the comparing unit, and a second output end of the voltage generating unit is coupled with a second input end of the comparing unit; the second output end of the voltage generating unit is suitable for outputting a reference voltage; the output end of the comparison unit is coupled with the input end of the output unit; and the output end of the output unit outputs a reset signal.

Optionally, the bias current generating unit includes: first PMOS pipe, second PMOS pipe, first NMOS pipe and second NMOS pipe, wherein: the grid electrode of the first PMOS tube is grounded, the drain electrode of the first PMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube is connected with the power supply voltage; the grid electrode of the second PMOS tube is coupled with the first output end of the bias current generating unit, and the drain electrode of the second PMOS tube is coupled with the first output end of the bias current generating unit and the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is coupled with the second output end of the bias current generating unit and the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; and the grid electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded.

Optionally, the voltage detection unit includes: third NMOS pipe, fourth NMOS pipe, fifth NMOS pipe, third PMOS pipe and first electric capacity, wherein: the grid electrode and the drain electrode of the third NMOS tube are connected with the power supply voltage, and the source electrode of the third NMOS tube is connected with the upper polar plate of the first capacitor; the grid electrode of the fourth NMOS tube is coupled with the input end of the voltage detection unit, the drain electrode of the fourth NMOS tube is coupled with the drain electrode of the third PMOS tube, and the source electrode of the fourth NMOS tube is grounded; the grid electrode of the fifth NMOS tube is coupled with the drain electrode of the third PMOS tube, the drain electrode of the fifth NMOS tube is coupled with the output end of the voltage detection unit, and the source electrode of the fifth NMOS tube is grounded; the grid electrode of the third PMOS tube is connected with the power supply voltage, and the source electrode of the third PMOS tube is coupled with the source electrode of the third NMOS tube; the lower plate of the first capacitor is grounded.

Optionally, the substrate of the third PMOS transistor is coupled to the source of the third NMOS transistor.

Optionally, the voltage generating unit includes: reset signal trigger module and reference voltage generation module, wherein: the first input end of the reset signal triggering module is coupled with the first input end of the voltage generating unit, the second input end of the reset signal triggering module is coupled with the second input end of the voltage generating unit, and the output end of the reset signal triggering module is coupled with the first output end of the voltage generating unit; the input end of the reference voltage generation module is coupled with the first input end of the voltage generation unit, and the output end of the reference voltage generation module is coupled with the second output end of the voltage generation unit.

Optionally, the reset signal triggering module includes: fourth PMOS pipe, fifth PMOS pipe and second electric capacity, wherein: the grid electrode of the fourth PMOS tube is coupled with the first input end of the reset signal triggering module, the drain electrode of the fourth PMOS tube is coupled with the source electrode of the fifth PMOS tube, and the source electrode of the fourth PMOS tube is connected with the power supply voltage; the grid electrode of the fifth PMOS tube is coupled with the drain electrode of the fifth PMOS tube, and the drain electrode of the fifth PMOS tube is coupled with the output end of the reset signal triggering module and the second input end of the reset signal triggering module; and the upper polar plate of the second capacitor is coupled with the second input end of the reset signal triggering module, and the lower polar plate of the second capacitor is grounded.

Optionally, the reference voltage generating circuit includes: sixth PMOS pipe, sixth NMOS pipe and seventh NMOS pipe, wherein: the grid electrode of the sixth PMOS tube is coupled with the input end of the reference voltage generating circuit, the drain electrode of the sixth PMOS tube is coupled with the second output end of the reference voltage generating circuit, and the source electrode of the sixth PMOS tube is connected with the power supply voltage; the grid electrode of the sixth NMOS tube is coupled with the drain electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube is also coupled with the drain electrode of the sixth PMOS tube, and the source electrode of the sixth NMOS tube is coupled with the drain electrode of the seventh NMOS tube; the gate of the seventh NMOS transistor is coupled to the drain thereof, and the source thereof is grounded.

Optionally, the comparing unit includes: a comparison module and an amplification module, wherein: the first input end of the comparison module is coupled with the first input end of the comparison unit, the second input end of the comparison module is coupled with the second input end of the comparison unit, the output end of the comparison module is coupled with the input end of the amplification module, and the control end of the comparison module is coupled with the second output end of the current bias unit; and the output end of the amplifying module is coupled with the output end of the comparing unit.

Optionally, the comparing module includes: seventh PMOS pipe, eighth NMOS pipe, ninth NMOS pipe and tenth NMOS pipe, wherein: a seventh PMOS transistor having a gate coupled to a drain thereof, a source connected to the power voltage, and a drain coupled to a drain of the eighth NMOS transistor; the grid electrode of the eighth PMOS tube is coupled with the grid electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is coupled with the drain electrode of the ninth NMOS tube and the output end of the comparison module; the gate of the eighth NMOS transistor is coupled to the first input terminal of the comparison module, and the source of the eighth NMOS transistor is coupled to the drain of the tenth NMOS transistor; the grid electrode of the ninth NMOS tube is coupled with the second input end of the comparison module, and the source electrode of the ninth NMOS tube is coupled with the drain electrode of the tenth NMOS tube; the gate of the tenth NMOS transistor is coupled to the control terminal of the comparison module, and the source thereof is grounded.

Optionally, the amplifying module includes: a ninth PMOS transistor, wherein: the ninth PMOS transistor has a gate coupled to the input terminal of the amplifying module, a drain coupled to the output terminal of the amplifying module, and a source connected to the power voltage.

Optionally, the comparing unit further includes: and the grid electrode of the eleventh NMOS tube is coupled with the control end of the comparison module, the drain electrode of the eleventh NMOS tube is coupled with the drain electrode of the ninth PMOS tube, and the source electrode of the eleventh NMOS tube is grounded.

Optionally, the output unit includes: an inverter, an input of which is coupled to the input of the output unit, and an output of which is coupled to the output of the inverter.

Optionally, the inverter includes: a tenth PMOS transistor and a twelfth NMOS transistor, wherein: a gate of the tenth PMOS transistor is coupled to the input terminal of the inverter, a drain of the tenth PMOS transistor is coupled to the output terminal of the inverter, and a source of the tenth PMOS transistor is connected to the power voltage; the grid electrode of the twelfth NMOS tube is coupled with the grid electrode of the tenth PMOS tube, the drain electrode of the twelfth NMOS tube is coupled with the drain electrode of the tenth PMOS tube, and the source electrode of the twelfth NMOS tube is grounded.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the voltage detection unit detects the change of the power supply voltage and adjusts the output voltage of the first output end of the voltage generation unit. Since the two output terminals of the voltage generating unit are respectively connected to the two input terminals of the comparing unit, the comparing unit substantially compares the output voltages of the two output terminals of the voltage generating unit. When the output voltage of the first output end of the voltage generating unit changes, the comparison result output by the comparison unit correspondingly changes, and accordingly a reset signal is generated according to the change of the power supply voltage. The reset circuit can rapidly respond to the change of the power supply voltage, and can realize rapid and effective reset no matter aiming at rapid power-on reset or slow power-on reset, rapid power-off reset and slow power-off reset.

Further, by arranging the second capacitor, delay reset can be realized. The second capacitor is charged by the second bias current, and the time when the voltage of the upper plate of the second capacitor reaches the output voltage of the second output end of the voltage generation unit from 0 can be regarded as the delay reset time. By controlling the magnitude of the second bias current and the magnitude of the second capacitor, the delay reset time can be correspondingly adjusted.

Drawings

Fig. 1 is a schematic structural diagram of a reset circuit in an embodiment of the present invention.

Detailed Description

As described above, the conventional reset circuit cannot cover various power-on and power-off application scenarios in practical application, and cannot quickly and effectively implement reset.

In the embodiment of the invention, the voltage detection unit detects the change of the power supply voltage, and adjusts the output voltage of the first output end of the voltage generation unit. Since the two output terminals of the voltage generating unit are respectively connected to the two input terminals of the comparing unit, the comparing unit substantially compares the output voltages of the two output terminals of the voltage generating unit. When the output voltage of the first output end of the voltage generating unit changes, the comparison result output by the comparison unit correspondingly changes, and accordingly a reset signal is generated according to the change of the power supply voltage. The reset circuit can rapidly respond to the change of the power supply voltage, and can realize rapid and effective reset no matter aiming at rapid power-on reset or slow power-on reset, rapid power-off reset and slow power-off reset.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The reset circuit provided by the embodiment of the invention is described in detail below with reference to fig. 1.

In a specific implementation, the reset circuit may include: bias current generating unit 11, voltage detecting unit 12, voltage generating unit 13, comparing unit 14, and output unit 15.

In the embodiment of the present invention, the output terminal of the bias current generating unit 11 is coupled to the voltage generating unit 13, the voltage detecting unit 12 and the comparing unit 14, and can generate a corresponding bias current according to the change of the power supply voltage VCC, so as to provide the bias current for the voltage detecting unit 12, the comparing unit 14, and the like. The magnitude of the bias current is related to the supply voltage VCC. When the supply voltage VCC changes, the bias current changes accordingly.

An output of the voltage detection unit 12 may be coupled to the voltage generation unit 13. When the voltage detecting unit 12 detects that the power supply voltage VCC changes, the output voltage of the first output terminal of the voltage generating unit 13 can be controlled to change accordingly.

A first output terminal of the voltage generating unit 13 is coupled to a first input terminal of the comparing unit 14, and a second output terminal of the voltage generating unit 13 is coupled to a second input terminal of the comparing unit 14; the second output terminal of the voltage generating unit 13 may output a reference voltage of a fixed value.

A first input terminal of the comparing unit 14 is coupled to a first output terminal of the voltage generating unit 13, a second input terminal of the comparing unit 14 is coupled to a second output terminal of the voltage generating unit 13, and an output terminal of the comparing unit 14 is coupled to an input terminal of the output unit 15; the comparing unit 14 may compare the output voltage of the first output terminal of the voltage generating unit 13 with the output voltage of the second output terminal of the voltage generating unit 13 to obtain a comparison result.

The output unit 15 performs an inversion process on the comparison result received from the comparison unit 14, and the output end of the output unit 15 outputs the finally obtained reset signal.

The voltage detection unit 12 detects a change in the power supply voltage VCC, and adjusts the output voltage of the first output terminal of the voltage generation unit 13. Since the two output terminals of the voltage generating unit 13 are respectively connected to the two input terminals of the comparing unit 14, the comparing unit 14 substantially compares the output voltages of the two output terminals of the voltage generating unit 13. When the output voltage of the first output terminal of the voltage generating unit 13 changes, the comparison result output by the comparing unit 14 changes accordingly, so that the reset signal is generated accordingly according to the change of the power supply voltage VCC. The reset circuit can rapidly respond to the change of the power supply voltage VCC, and effective reset is realized.

The specific structure of the reset circuit provided in the above-described embodiments of the present invention will be described in detail below.

In an embodiment of the present invention, the bias current generating unit 11 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2, wherein:

the gate of the first PMOS transistor MP1 may be grounded GND, the drain of the first PMOS transistor MP1 may be coupled to the drain of the first NMOS transistor MN1, and the source of the first PMOS transistor MP1 may be connected to the power voltage VCC;

a gate of the second PMOS transistor MP2 may be coupled to the first output terminal of the bias current generating unit 11, and a drain of the second PMOS transistor MP2 may be coupled to the gate of the second PMOS transistor MP2, the first output terminal of the bias current generating unit 11, and the drain of the second NMOS transistor MN 2; the drain voltage of the second PMOS transistor MP2 is VB 2;

the gate of the first NMOS transistor MN1 may be coupled to the second output terminal of the bias current generating unit 11, and the gate of the first NMOS transistor MN1 is coupled to the drain of the first NMOS transistor MN 1; the source of the first NMOS transistor MN1 may be grounded GND; the drain voltage of the first NMOS tube is VB 1;

the gate of the second NMOS transistor MN2 may be coupled to the gate of the first NMOS transistor MN1 and the second output terminal of the bias current generating unit 11, and the source of the second NMOS transistor MN2 may be coupled to the ground GND.

The first PMOS transistor MP1 may be a PMOS transistor with a large aspect ratio. For example, the aspect ratio of the first PMOS transistor MP1 is 1: 1000. the first PMOS transistor MP1 can be equivalent to a large resistor.

It should be noted that only one first PMOS transistor MP1 is exemplarily shown in fig. 1. In a specific application, the first PMOS transistor MP1 may also be composed of a plurality of PMOS transistors connected in series. The aspect ratio of the first PMOS transistor MP1 may have other values, and is not limited to the above example.

The gate of the first NMOS transistor MN1 is connected to the drain of the first NMOS transistor MN1, forming a diode connection. The equivalent large resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 form a current source of NMOS ultra-low current, and a second bias current is output through the second output terminal of the bias current generating unit 11.

The gate of the second PMOS transistor MP2 is coupled to the drain of the second PMOS transistor MP2 to form a diode connection. The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2 and the gate of the second PMOS transistor MP2, and is folded by the second NMOS transistor MN2 and the second PMOS transistor MP2 to form a PMOS ultra-low current source, and the first bias current is output through the first output terminal of the bias current generating unit 11.

In the embodiment of the present invention, the first bias current and the second bias current are not substantially different. After the second PMOS transistor MP2 establishes a current mirror with the corresponding PMOS transistor in the voltage generating unit 13, the generated first bias current supplies power to the corresponding PMOS transistor; the second NMOS transistor MN2 generates a second bias current to power the corresponding NMOS transistor after establishing a current mirror with the corresponding NMOS transistor in the voltage detection unit 12 and the corresponding NMOS transistor in the comparison unit 14.

In the embodiment of the invention, in order to meet the requirement of low power consumption, the bias current output by the bias current generating circuit can be as low as a nanoampere (nA) level.

In specific implementation, the power-down detection circuit may detect whether the power supply voltage VCC is quickly powered down, that is, whether the power supply voltage VCC is quickly lowered.

In an embodiment of the present invention, the power down detection circuit may include: a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a third PMOS transistor MP3, and a first capacitor C1, wherein:

the grid electrode of the third NMOS tube MN3 is connected with a power supply voltage VCC, the drain electrode of the third NMOS tube MN3 is connected with the power supply voltage VCC, and the source electrode of the third NMOS tube MN3 is connected with the upper polar plate of the first capacitor C1;

the lower plate of the first capacitor C1 is grounded GND;

the gate of the fourth NMOS transistor MN4 is coupled to the input terminal of the voltage detection unit 12, the drain of the fourth NMOS transistor MN4 is coupled to the drain of the third PMOS transistor MP3 and the drain of the fifth NMOS transistor MN5, and the source of the fourth NMOS transistor MN4 is grounded to GND; the fourth NMOS transistor MN4 and the second output terminal of the bias current generating unit 11 form a current mirror, that is, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 form a current mirror, that is, the fourth NMOS transistor MN4 is powered by the second bias current;

the drain of the fifth NMOS transistor MN5 is coupled to the output terminal of the voltage detecting unit 12, and the source of the fifth NMOS transistor MN5 is grounded to GND;

the gate of the third PMOS transistor MP3 is connected to the power voltage VCC, the drain of the third PMOS transistor MP3 is coupled to the drain of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5, and the source of the third PMOS transistor MP3 is coupled to the source of the third NMOS transistor MN 3.

In the embodiment of the present invention, the voltage at the source input of the third NMOS transistor MN3 is denoted as VX 1. Since the gate of the fourth NMOS transistor MN4 is coupled to the input terminal of the voltage detecting unit 12, that is, the gate of the fourth NMOS transistor MN4 is coupled to the second output terminal of the bias current generating unit 11, the fourth NMOS transistor MN4 provides the third PMOS transistor MP3 with the second bias current, and marks the drain voltage of the third PMOS transistor MP3 as VX 2.

The gate voltage of the fifth NMOS transistor MN5 is VX2, the source of the fifth NMOS transistor MN5 is grounded to GND, and the voltage output by the drain of the fifth NMOS transistor MN5 is labeled VX 3. When the power supply voltage VCC is rapidly powered down, the voltage of the first capacitor C1 cannot be suddenly changed, so that the source voltage VX1 of the third NMOS transistor MN3 is kept unchanged; the gate voltage of the third PMOS transistor MP3 decreases, such that the third PMOS transistor MP3 is turned on, the drain voltage of the third PMOS transistor MP3 increases from 0V, and when the voltage increases to the turn-on threshold voltage of the fifth NMOS transistor MN5, the fifth NMOS transistor MN5 is turned on.

In a specific implementation, the voltage generating unit 13 may include a reset signal triggering module and a reference voltage generating module, wherein:

a first input terminal of the reset signal triggering module is coupled to a first input terminal of the voltage generating unit 13, that is, the first input terminal of the reset signal triggering module is coupled to a first output terminal of the bias current generating unit 11; a second input terminal of the reset signal triggering module is coupled to a second input terminal of the voltage generating unit 13, that is, the second input terminal of the reset signal triggering module is coupled to an output terminal of the voltage detecting unit 12; the output terminal of the reset signal triggering module is coupled to the first output terminal of the voltage generating unit 13, that is, the output terminal of the reset signal triggering module is coupled to the first input terminal of the comparing unit 14;

the input terminal of the reference voltage generating module is coupled to the first input terminal of the voltage generating unit 13, that is, the input terminal of the reference voltage generating module is coupled to the first output terminal of the bias current generating unit 11; an output terminal of the reference voltage generating module is coupled to a second output terminal of the voltage generating unit 13, that is, an output terminal of the reference voltage generating module is coupled to a second input terminal of the comparing unit 14. The reference voltage generation module may generate a fixed value of the reference voltage.

In an embodiment of the present invention, the reset signal triggering module may include: a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a second capacitor C2, wherein:

a source of the fourth PMOS transistor MP4 is coupled to the power voltage VCC, a gate of the fourth PMOS transistor MP4 is coupled to the first input terminal of the voltage generating unit 13, and a drain of the fourth PMOS transistor MP4 is coupled to a source of the fifth PMOS transistor MP 5;

a gate of the fifth PMOS transistor MP5 is coupled to the drain of the fifth PMOS transistor MP5, and a drain of the fifth PMOS transistor MP5 is coupled to the first output terminal of the voltage generating unit 13, the second input terminal of the voltage generating unit 13, and the upper plate of the second capacitor C2;

the lower plate of the second capacitor C2 is grounded GND; the upper plate voltage of the second capacitor C2 is identified as VX 3.

The gate of the fifth PMOS transistor MP5 is coupled to the drain of the fifth PMOS transistor MP5, forming a diode structure and connected to the upper plate of the second capacitor C2. The fourth PMOS transistor MP4 and the first output terminal of the bias current generating unit 11 form a current mirror, and the first bias current flows through the fifth PMOS transistor MP5 to the upper plate of the second capacitor C2. The voltage at the upper plate of the second capacitor C2 is labeled VX 3. When the fifth NMOS transistor MN5 is turned on, the charges stored in the second capacitor C2 are discharged, and the voltage VX3 of the upper plate of the second capacitor C2 rapidly decreases to 0V.

In a specific implementation, the delayed reset can be realized by setting the second capacitor C2. The time when the voltage of the upper plate of the second capacitor C2 reaches the output voltage of the second output terminal of the voltage generation unit 13 from 0V by charging the second capacitor C2 with the second bias current can be regarded as the delay reset time. By controlling the magnitude of the second bias current and the magnitude of the second capacitor C2, the delayed reset time can be adjusted accordingly.

In an embodiment of the present invention, the reference voltage generating module may include: a sixth PMOS transistor MP6, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7, wherein:

the gate of the sixth PMOS transistor MP6 is coupled to the input terminal of the reference voltage generating module, the drain of the sixth PMOS transistor MP6 is coupled to the second output terminal of the voltage generating unit 13 and the drain of the sixth NMOS transistor MN6, and the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VCC; the sixth PMOS transistor MP6 and the first output terminal of the bias current generating unit 11 form a current mirror, that is, the second PMOS transistor MP2 and the sixth PMOS transistor MP6 form a current mirror, that is, the sixth PMOS transistor MP6 is powered by the first bias current;

the gate of the sixth NMOS transistor MN6 is coupled to the drain of the sixth NMOS transistor MN6, and the source of the sixth NMOS transistor MN6 is coupled to the drain of the seventh NMOS transistor MN 7;

the gate of the seventh NMOS transistor MN7 is coupled to the drain of the seventh NMOS transistor MN7, and the source of the seventh NMOS transistor MN7 is grounded to GND.

In the embodiment of the invention, the gate of the sixth NMOS transistor MN6 is coupled to the drain of the sixth NMOS transistor MN6, forming a diode structure. The gate of the seventh NMOS transistor MN7 is coupled to the drain of the seventh NMOS transistor MN7, forming a diode structure. Therefore, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 may be equivalent to two diodes connected in series. The drain voltage of the sixth PMOS transistor MP6 is denoted by VX4, i.e., the reference voltage generated by the reference voltage generating module is VX 4.

In a specific implementation, the comparator may include a comparison module and an amplification module, wherein:

the first input terminal of the comparing module is coupled to the first input terminal of the comparing unit 14, and the first input terminal of the comparing module can be regarded as the first input terminal of the comparing unit 14; a second input terminal of the comparing module is coupled to a second input terminal of the comparing module, and the second input terminal of the comparing module can be regarded as a second input terminal of the comparing unit 14; the output end of the comparison module is coupled with the input end of the amplification module, the control end of the comparison module is coupled with the control end of the comparison unit 14, and the control end of the comparison unit 14 is coupled with the second output end of the current bias power supply;

the output of the amplifying block may be coupled to the output of the comparing unit 14, i.e. the output of the amplifying block is regarded as the output of the comparing unit 14.

In an embodiment of the present invention, the comparing module may include: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10, wherein:

a source electrode of the seventh PMOS transistor MP7 is connected to the power supply voltage VCC, a gate electrode of the seventh PMOS transistor MP7 is coupled to a gate electrode of the eighth PMOS transistor MP8 and a drain electrode of the seventh PMOS transistor MP7, and a drain electrode of the seventh PMOS transistor MP7 is coupled to a drain electrode of the eighth NMOS transistor MN 8;

the source electrode of the eighth PMOS tube MP8 is connected with a power supply voltage VCC, the grid electrode of the eighth PMOS tube MP8 is coupled with the grid electrode of the seventh PMOS tube MP7, and the drain electrode of the eighth PMOS tube MP8 is coupled with the output end of the comparator and the drain electrode of the ninth NMOS tube MN 9; the drain voltage of the eighth PMOS transistor MP8 is denoted VX 5;

the gate of the eighth NMOS transistor MN8 is coupled to the first input terminal of the comparator, and the source of the eighth NMOS transistor MN8 is coupled to the drain of the tenth NMOS transistor MN 10;

the gate of the ninth NMOS transistor MN9 is coupled to the second input terminal of the comparator, and the source of the ninth NMOS transistor MN9 is coupled to the drain of the tenth NMOS transistor MN 10;

the source of the tenth NMOS transistor MN10 is grounded GND; the tenth NMOS transistor MN10 and the second output terminal of the bias current generating unit 11 form a current mirror, i.e., the second NMOS transistor MN2 and the tenth NMOS transistor MN10 form a current mirror, i.e., the tenth NMOS transistor MN10 is powered by the second bias current.

In the embodiment of the invention, the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 form a differential pair, and the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form an active current mirror.

In the embodiment of the present invention, the amplifying module may include a ninth PMOS transistor MP 9. The gate of the ninth PMOS transistor MP9 may be coupled to the input terminal of the amplifying module, that is, the gate of the ninth PMOS transistor MP9 is regarded as the input terminal of the amplifying module; the drain of the ninth PMOS transistor MP9 is coupled to the output terminal of the amplifying module, the drain of the ninth PMOS transistor MP9 can be regarded as the output terminal of the amplifying module, and the source of the ninth PMOS transistor MP9 is connected to the power supply voltage VCC.

The drain voltage of the ninth PMOS transistor MP9 is denoted as VX 6.

In the embodiment of the present invention, the comparing unit 14 may further include an eleventh NMOS transistor MN 11. The gate of the eleventh NMOS transistor MN11 is coupled to the control terminal of the comparison module, the drain of the eleventh NMOS transistor MN11 is coupled to the drain of the ninth PMOS transistor MP9, and the source of the eleventh NMOS transistor MN11 is grounded to GND. The eleventh NMOS transistor MN11 and the second output terminal of the bias current generating unit 11 form a current mirror, that is, the second NMOS transistor MN2 and the eleventh NMOS transistor MN11 form a current mirror, that is, the eleventh NMOS transistor MN11 is powered by the first bias current.

In a specific implementation, the output unit 15 may include an inverter, an input terminal of the inverter is an input terminal of the output unit 15, and an output terminal of the inverter is an output terminal of the output unit 15. The output of the comparison unit 14 is inverted by an inverter.

Since the digital circuit usually adopts low level reset, the output of the previous stage module (i.e. the comparison unit 14) is represented by high level reset, and the final output is represented by low level reset by adding an inverter, thereby ensuring the consistency of the whole reset circuit.

In the embodiment of the present invention, the inverter may include a tenth PMOS transistor MP10 and a twelfth NMOS transistor MN12, wherein:

the gate of the tenth PMOS transistor MP10 is coupled to the input terminal of the inverter, the drain of the tenth PMOS transistor MP10 is coupled to the output terminal of the inverter, and the source of the tenth PMOS transistor MP10 is connected to the power supply voltage VCC;

the gate of the twelfth NMOS transistor MN12 is coupled to the gate of the tenth PMOS transistor MP10, the drain of the twelfth NMOS transistor MN12 is coupled to the drain of the tenth PMOS transistor MP10, and the source of the twelfth NMOS transistor MN12 is grounded to GND.

That is, the gates of the tenth PMOS transistor MP10 and the twelfth NMOS transistor MN12 are both coupled to the input terminal of the inverter, and the drains of the tenth PMOS transistor MP10 and the twelfth NMOS transistor MN12 are both coupled to the output terminal of the inverter.

In the embodiment of the present invention, except that the substrate of the third PMOS transistor MP3 is coupled to the source of the third NMOS transistor MN3, the substrates of the remaining PMOS transistors (the first to fourth PMOS transistors MP1 to MP2 and the fourth to tenth PMOS transistors MP4 to MP10) are all connected to the power supply, and the substrates of the remaining NMOS transistors (the first to fourth NMOS transistors MN1 to MN2 and the fourth to twelfth NMOS transistors MN4 to MN12) are all grounded.

The following is a description of a specific operation principle of the reset circuit provided in the above-described embodiment of the present invention.

Comparing unit 14 compares VX3 with VX4, and when VX3 > VX4, VX5 is high, VX6 is low, and the output RESET signal RESET is high. When VX3 < VX4, VX5 is low, VX6 is high, and the output RESET signal RESET is low. When the RESET signal RESET is at a low level, the representation is in a RESET state; when the RESET signal RESET is at a high level, the representation completes the RESET.

A fast power-up scenario for supply voltage VCC:

the time for the power supply voltage VCC to complete power-up is in the order of microseconds (μ s). With the power-on of the power supply voltage VCC, the bias current generating circuit starts working synchronously and outputs a first bias current and a second bias current. The reference voltage generating module in the voltage generating unit 13 generates a stable reference voltage VX4, and at the same time, the second bias current charges the second capacitor C2, so that the voltage VX3 of the upper plate of the second capacitor C2 rises slowly from 0V. After a certain time of charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, the RESET signal RESET is at high level, and the quick power-on RESET is completed.

Aiming at the scene that the power supply voltage VCC is quickly electrified after being quickly and incompletely powered down:

the rapid incomplete power-down of the power supply voltage VCC means that: the power supply voltage VCC drops by a voltage difference of about 1V and does not drop to a 0V potential. The rapid and complete power-down of the power supply voltage VCC means that: the supply voltage VCC is quickly powered down to 0V potential. For a reset circuit, when reset can be achieved at incomplete power down, then reset can also be achieved at complete power down. Therefore, the scene that the power supply voltage VCC is rapidly and incompletely powered down is considered in the embodiment of the invention.

In the fast incomplete power-down stage, after the power supply voltage VCC is fast powered down, VX1 remains unchanged, and the third PMOS transistor MP3 is turned on, so that VX2 rapidly jumps to be approximately equal to VX 1. Then, the fifth NMOS transistor MN5 turns on, quickly releasing the charges stored in the second capacitor C2, so that VX3 quickly decreases to 0V, and the RESET signal RESET quickly switches to a low level.

In the fast power-up phase, the third PMOS transistor MP3 is turned off, and the fourth NMOS transistor MN4 is turned on, so as to rapidly drop VX2 to 0V. VX4 is kept unchanged, and the second capacitor C2 is charged through the second bias current, so that the voltage VX3 of the upper plate of the second capacitor C2 slowly rises from 0V. After a certain time of charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, the RESET signal RESET is at high level, and the quick power-on RESET is completed.

Aiming at the scene of slow power-on after fast incomplete power-off:

in the embodiment of the present invention, the slow power-up after the fast incomplete power-down may refer to: after a rapid incomplete power down, the supply voltage VCC remains stable and after a period of time is powered up again at a rate of milliseconds (ms).

In the fast incomplete power-down stage, after the power supply voltage VCC is fast powered down, VX1 remains unchanged, and the third PMOS transistor MP3 is turned on, so that VX2 rapidly jumps to be approximately equal to VX 1. Then, the fifth NMOS transistor MN5 turns on, quickly releasing the charges stored in the second capacitor C2, so that VX3 quickly decreases to 0V, and the RESET signal RESET quickly switches to a low level.

In the slow power-up stage, when the power voltage VCC rises to a certain value, the third PMOS transistor MP3 is turned off, and the fourth NMOS transistor MN4 is turned on, so as to rapidly drop VX2 to 0V. VX4 is kept unchanged, and the second capacitor C2 is charged through the second bias current, so that the voltage VX3 of the upper plate of the second capacitor C2 slowly rises from 0V. After a certain time of charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, the RESET signal RESET is at high level, and the slow power-on RESET is completed.

Aiming at the scene of slow power-up after slow power-down:

in the slow power-down stage, when the power voltage VCC decreases to a certain value, the third PMOS transistor MP3 is turned on, and the upper plate voltage VX3 of the second capacitor C2 maintains 0V.

In the slow power-up stage, when the power voltage VCC rises to a certain value, the third PMOS transistor MP3 is turned off, and the fourth NMOS transistor MN4 is turned on, so as to rapidly drop VX2 to 0V. VX4 is kept unchanged, and the second capacitor C2 is charged through the second bias current, so that the voltage VX3 of the upper plate of the second capacitor C2 slowly rises from 0V. After a certain time of charging process, the voltage VX3 of the upper plate of the second capacitor C2 exceeds the reference voltage VX4, the RESET signal RESET is at high level, and the slow power-on RESET is completed.

In summary, the reset circuit provided by the embodiment of the invention can cover all scenes of fast power-on reset, slow power-on reset, fast power-off reset, slow power-off reset and incomplete power-off re-power-on.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.