阅读说明：本技术 一种用于qkd系统的soc构架芯片 (SOC (system on chip) framework chip for QKD (quantum key distribution) system ) 是由 杨灿美 彭文溢 程磊 李飒祎 于 2019-11-28 设计创作，主要内容包括：本发明公开了一种用于QKD系统的SOC构架芯片,包括：第一互联总线；与第一互联总线连接的QKD模块,用于通过与第一互联总线连接的第一类外设接口与一个光量子通信设备连接,以与所连接的光量子通信设备进行数据交互；第二互联总线,通过第一总线桥与所述第一互联总线连接,且通过第二类外设接口与光量子通信设备连接,以获取光量子通信设备的工作参数；CPU子系统,与所述第一互联总线连接,且连接有中断控制器。本发明技术方案提供了一种用于QKD系统的SOC构架芯片,芯片中各个部件一体集成,芯片体积小,无需采用分离的电子元器件搭建用于QKD系统的数据处理与控制子系统,使用方便。(The invention discloses an SOC framework chip for a QKD system, which comprises: a first interconnect bus; the QKD module is connected with the first interconnection bus and is used for being connected with a light quantum communication device through a first type of peripheral interface connected with the first interconnection bus so as to perform data interaction with the connected light quantum communication device; the second interconnection bus is connected with the first interconnection bus through a first bus bridge and is connected with the light quantum communication equipment through a second type peripheral interface so as to obtain working parameters of the light quantum communication equipment; and the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller. The technical scheme of the invention provides the SOC framework chip for the QKD system, all parts in the chip are integrated into a whole, the chip is small in size, a data processing and control subsystem for the QKD system is not required to be built by adopting separated electronic components, and the use is convenient.)

1. An SOC architecture chip for a QKD system having two optical quantum communication devices in quantum communication, the SOC architecture chip comprising:

a first interconnect bus;

the first type of peripheral interface is connected with the first interconnection bus and is used for connecting the light quantum communication equipment;

the QKD module is connected with the first interconnection bus and used for carrying out data interaction with the optical quantum communication equipment connected with the chip to complete a preset QKD algorithm;

the second interconnection bus is connected with the first interconnection bus through a first bus bridge and is connected with the light quantum communication equipment through a second type peripheral interface so as to acquire working parameters of the light quantum communication equipment;

and the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller and used for executing at least one function of system start and stop, hardware parameter configuration, peripheral drivers, application end command analysis issuing, data scheduling and process management.

2. The SOC architecture chip of claim 1, further comprising:

and the application port is connected with the first interconnection bus and used for outputting a quantum key.

3. The SOC architecture chip of claim 1, wherein the two optical quantum communication devices are an optical signal transmission device and an optical signal detection device, respectively;

the first type of peripheral interface comprises: and the first peripheral interface is used for connecting a photon detector of the optical signal detection equipment to complete the configuration of the coding parameters of the off-chip device and the reading of the detection result.

4. The SOC architecture chip of claim 1, wherein the two optical quantum communication devices are an optical signal transmission device and an optical signal detection device, respectively;

the first type of peripheral interface comprises: and the second external interface is connected with a light-emitting code and control module in the chip, the second external interface is used for connecting a light source subsystem of the optical signal sending equipment, and the light-emitting code and control module is used for providing a light source driving signal for the light source subsystem through the second external interface.

5. The SOC architecture chip of claim 4 wherein the SOC architecture chip has an on-chip true random number generator;

the first type of peripheral interface further comprises: and the third peripheral interface is connected with the on-chip true random number generator through a gate and the luminous coding and control module.

6. The SOC architecture chip of claim 4, further comprising: the third type peripheral interface is separately connected with a second bus bridge through a third interconnection bus, and the second bus bridge is connected with the first interconnection bus;

the third type of peripheral interface is used for connecting an external DDR3 chip, so that the SOC framework chip is connected with external data and a programmer to form a working system.

7. The SOC architecture chip of claim 6 wherein the illumination code and control module interfaces with the third type of peripherals solely through one of the third interconnect buses; and the QKD module is separately connected with the third type of peripheral interfaces through the third interconnection bus.

8. The SOC architecture chip of claim 1, further comprising: and the fourth type peripheral interface is respectively connected with the QKD module and the first interconnection bus and is used for connecting an Ethernet PHY chip to form an Ethernet.

9. The SOC architecture chip of claim 1, further comprising: and the fifth type peripheral interface is connected with the first interconnection bus and is used for connecting a chip external program flash memory.

10. The SOC architecture chip of any of claims 1-9 wherein a memory is connected to at least the CPU subsystem and the QKD module, respectively.

Technical Field

The invention relates to the technical field of Quantum Key Distribution (QKD), in particular to a System On Chip (SOC) architecture chip for a QKD system.

Background

The current QKD (Quantum Key Distribution) system basically adopts the traditional photoelectric technology and the ethernet to complete the processes of sending, detecting, data interaction between the sending and receiving parties, data processing and the like based on the BB84 protocol, so as to refine the secure Quantum Key. The QKD system is composed of an optical signal transmitting device and an optical signal detecting device, an optical quantum channel is formed by connecting optical fibers in the middle, and an information interaction network is needed between the optical signal transmitting device and the optical signal detecting device. QKD systems include optical, electrical signal conditioning in signal form, functional splitting of light sources, detection and data processing, and information interaction.

According to the functional distinction, the QKD system forms a system structure state of modularizing three parts, namely a light source subsystem, a receiving subsystem and data processing and control, as shown in fig. 1, fig. 1 is a schematic structural diagram of the QKD system and is provided with an optical signal transmitting device 11 and an optical signal detecting device 12. The optical signal transmitting device 11 has an optical source subsystem 112 and a data processing and controlling subsystem 111, and the data processing and controlling subsystem 111 controls the optical source subsystem 112 to transmit the encoded optical signal to the optical signal detecting device 12. The optical signal detection device 12 has a receiving subsystem 121 and a data processing and control subsystem 122, and the data processing and control subsystem 122 controls the receiving subsystem 121 to decode and detect the optical signal to refine the secure quantum key.

Since QKD is an emerging information technology area, there is currently no application specific integrated circuit chip (ASIC) for QKD systems.

Disclosure of Invention

In view of the above, the present application provides an SOC architecture chip for QKD system, which has the following scheme:

an SOC architecture chip for a QKD system having two optical quantum communication devices in quantum communication, the SOC architecture chip comprising:

a first interconnect bus;

the first type of peripheral interface is connected with the first interconnection bus and is used for connecting the light quantum communication equipment;

the QKD module is connected with the first interconnection bus and used for carrying out data interaction with the optical quantum communication equipment connected with the chip to complete a preset QKD algorithm;

the second interconnection bus is connected with the first interconnection bus through a first bus bridge and is connected with the light quantum communication equipment through a second type peripheral interface so as to acquire working parameters of the light quantum communication equipment;

and the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller and used for executing at least one function of system start and stop, hardware parameter configuration, peripheral drivers, application end command analysis issuing, data scheduling and process management.

Preferably, the SOC architecture chip further includes:

and the application port is connected with the first interconnection bus and used for outputting a quantum key.

Preferably, in the SOC architecture chip, the two optical quantum communication devices are an optical signal transmitting device and an optical signal detecting device, respectively;

the first type of peripheral interface comprises: and the first peripheral interface is used for connecting a photon detector of the optical signal detection equipment to complete the configuration of the coding parameters of the off-chip device and the reading of the detection result.

Preferably, in the SOC architecture chip, the two optical quantum communication devices are an optical signal transmitting device and an optical signal detecting device, respectively;

the first type of peripheral interface comprises: and the second external interface is connected with a light-emitting code and control module in the chip, the second external interface is used for connecting a light source subsystem of the optical signal sending equipment, and the light-emitting code and control module is used for providing a light source driving signal for the light source subsystem through the second external interface.

Preferably, in the SOC architecture chip, the SOC architecture chip includes an on-chip true random number generator;

the first type of peripheral interface further comprises: and the third peripheral interface is connected with the on-chip true random number generator through a gate and the luminous coding and control module.

Preferably, the SOC architecture chip further includes: the third type peripheral interface is separately connected with a second bus bridge through a third interconnection bus, and the second bus bridge is connected with the first interconnection bus;

the third type of peripheral interface is used for connecting an external DDR3 chip, so that the SOC framework chip is connected with external data and a programmer to form a working system.

Preferably, in the SOC architecture chip, the light-emitting coding and control module is separately connected to the third type of peripheral interface through one third interconnection bus; and the QKD module is separately connected with the third type of peripheral interfaces through the third interconnection bus.

Preferably, the SOC architecture chip further includes: and the fourth type peripheral interface is respectively connected with the QKD module and the first interconnection bus and is used for connecting an Ethernet PHY chip to form an Ethernet.

Preferably, the SOC architecture chip further includes: and the fifth type peripheral interface is connected with the first interconnection bus and is used for connecting a chip external program flash memory.

Preferably, in the SOC architecture chip, at least one memory is connected to each of the CPU subsystem and the QKD module.

As can be seen from the above description, the SOC architecture chip for QKD system provided by the embodiment of the present invention includes: a first interconnect bus; the QKD module is connected with the first interconnection bus and is used for being connected with one optical quantum communication device through a first type of peripheral interface connected with the first interconnection bus so as to perform data interaction with the connected optical quantum communication device and complete a preset QKD algorithm; the second interconnection bus is connected with the first interconnection bus through a first bus bridge and is connected with the light quantum communication equipment through a second type peripheral interface so as to acquire working parameters of the light quantum communication equipment; and the CPU subsystem is connected with the first interconnection bus and is connected with an interrupt controller and used for executing at least one function of system start and stop, hardware parameter configuration, peripheral drivers, application end command analysis issuing, data scheduling and process management. The technical scheme of the invention provides the SOC framework chip for the QKD system, all parts in the chip are integrated into a whole, the chip is small in size, a data processing and control subsystem for the QKD system is not required to be built by adopting separated electronic components, and the use is convenient.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic diagram of a QKD system;

FIG. 2 is a SOC architecture chip for a QKD system according to an embodiment of the present invention;

FIG. 3 is a block diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention;

FIG. 4 is a block diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention;

FIG. 5 is a block diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention;

fig. 6 is a block diagram of another SOC architecture chip for a QKD system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The traditional photoelectric technology has no integrated circuit chip specially used for a QKD system, except a small amount of optical devices and a small amount of customized products, in the existing QKD system, a large amount of commercial and civil general chips are built in the aspects of a light source subsystem and a receiving subsystem, and one or more electronic components such as an FPGA (field programmable gate array), a memory, a general processor, a network processor and the like are adopted for realizing data processing and control, so that the integrated circuit chip has at least the following major defects:

firstly, the equipment has large volume, high cost and larger power consumption.

Secondly, the key device is easy to be attacked by network and side channel, if the existing devices are basically commercial Ethernet as an interactive channel, and a commercial protocol TCP/IP protocol is adopted at the network port, an attacker is very easy to attack the device; moreover, a data processing and control subsystem is constructed by adopting a plurality of PCB boards for connection, so that more data interfaces can be exposed, and the convenience of attack of more side channels is provided for an attacker.

Thirdly, performance bottlenecks are easily achieved in QKD key generation rate (rate) performance, and a significant feature of QKD systems is that the final secure key generation rate is not high, but requires high data processing throughput, e.g., for a 100Km fiber QKD system, the final rate of rate is about 100kbps even when the optical quantum transmitting device transmits photons at GHz operating frequency, whereas in data processing, the system must be able to handle 10Gbps data throughput. In the prior art, the FPGA is adopted to complete algorithm data processing, all data processing is completed by a hardware module, all data processing follows a single flat structure, and subsequent data processing can be started only after the preorder data processing is completed, so that the overhead of temporary data storage is increased, and the throughput rate of the whole data processing cannot be improved.

Fourth, the same device constructed in the prior art cannot be adapted to different QKD application scenarios and coding rate requirements.

In order to solve the above problems, embodiments of the present invention provide an SOC chip design scheme for a QKD system, which can complete data processing based on BB84 protocol, and implement critical control and state parameter monitoring of a light source and a detector in the QKD system.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 2, fig. 2 is an SOC architecture chip for a QKD system according to an embodiment of the present invention, where the QKD system includes two optical quantum communication devices for performing quantum communication, one of the two optical quantum communication devices is used as an optical signal transmission device, and the other is used as an optical signal detection device, and optical signal transmission device structures and optical signal detection device structures in the two optical quantum communication devices may be in the existing QKD system mode, which is not specifically limited in this embodiment of the present invention.

The illustrated SOC architecture chip 10 includes: a first interconnection bus 11; a first type peripheral interface D1 connected to the first interconnect bus 11; the QKD module 12 is connected with the first interconnection bus, and the QKD module 12 is used for performing data interaction with the optical quantum communication equipment connected with the chip to complete a preset QKD algorithm; the second interconnection bus 13 is connected with the first interconnection bus 11 through a first bus bridge 14, and the second interconnection bus 13 is connected with the optical quantum communication device through a second type peripheral interface D2 to obtain working parameters of the optical quantum communication device; the CPU subsystem 15 is connected to the first interconnection bus 11 and connected to an interrupt controller 16, and the CPU subsystem 15 is configured to execute at least one of system start/stop, hardware parameter configuration, peripheral driver, application command parsing and issuing, data scheduling, and process management.

The first interconnect bus 11 may be an AHB bus. The second interconnect bus 13 may be an APB bus. The first bus bridge 14 may be an AHB-2-APB bridge. The QKD module 12 may execute all QKD algorithms related to the communication protocol based on the existing QKD communication protocol, such as the BB84 protocol, to implement QKD communication, where a specific algorithm is a standard algorithm under the corresponding communication protocol, and may be implemented based on the existing software and hardware schemes, and this is not specifically limited in the embodiments of the present invention.

The working parameters of the optical quantum communication equipment comprise light intensity parameters of a light source in the optical signal sending equipment, temperature parameters of a detector in the optical signal detecting equipment and the like. The second type peripheral interface D2 may be configured to be connected to the plurality of low speed peripheral interfaces 17 through the multiplexer Pin MUX and to be connected to the second interconnect bus 13 through the low speed peripheral interfaces 17. The low-speed peripheral interface 17 includes two i2c interfaces, two uart interfaces, two spi interfaces, two RTC interfaces, one Timer interface, and two gpio interfaces. The number and type of the low-speed peripheral interfaces 17 may be set based on chip communication requirements, and are not particularly limited. Each low-speed peripheral interface 17 is connected to the second interconnection bus 13 on the chip, and external signals can be configured by software through the multiplexer Pin MUX in different combinations to be connected to 64 output pins in total.

Optionally, in the SOC architecture chip according to the embodiment of the present invention, at least the CPU subsystem 15 and the QKD module 12 are respectively connected to a memory, and the memory may be an SRAM (static random access memory). The specific memory amount and layout can be set based on the chip usage requirement, and are not limited to the manner described in the embodiment of the present invention.

Referring to fig. 3, fig. 3 is another SOC architecture chip for QKD system according to an embodiment of the present invention, where the manner shown in fig. 3 is based on the manner shown in fig. 2, and further includes: an application port 18 connected to the first interconnect bus 11, the application port 18 being configured to output a quantum key. The application port 18 is a GMAC compliant port.

As mentioned above, the two optical quantum communication devices in the QKD system are the optical signal transmission device and the optical signal detection device, respectively, and in this case, the SOC architecture chip may be as shown in fig. 4.

Referring to fig. 4, fig. 4 is a further SOC architecture chip for a QKD system according to an embodiment of the present invention, where the manner shown in fig. 4 may be based on the manner shown in fig. 2 or fig. 3, and the first type peripheral interface D1 includes: and the first peripheral interface D11 is used for connecting a photon detector of the optical signal detection device to complete the configuration of coding parameters of the off-chip device and the reading of detection results. The first peripheral interface D11 is connected to the first interconnect bus 11 through the on-chip TDC interface and the photon information decoding module.

In the manner shown in fig. 4, the SOC architecture chip is used solely for data processing and control of the optical signal detection device in the QKD system, and can be connected to the detector in the optical signal detection device only through the first peripheral interface D11, and can detect the operating parameters of the elements in the optical signal detection device through the second peripheral interface D2.

As mentioned above, the two optical quantum communication devices in the QKD system are an optical signal transmission device and an optical signal detection device, and in this case, the SOC architecture chip may also be as shown in fig. 5.

Referring to fig. 5, fig. 5 is a further SOC architecture chip for a QKD system according to an embodiment of the present invention, where the manner shown in fig. 5 may be based on the manner shown in fig. 2 or fig. 3, and the first type peripheral interface D1 includes: and the second external interface D12 is connected with the light emitting coding and control module 19 inside the chip, the second external interface D12 is used for connecting the light source subsystem of the optical signal transmitting device, and the light emitting coding and control module 19 is used for providing a light source driving signal to the light source subsystem through the second external interface D12.

Alternatively, as shown in fig. 5, the SOC architecture chip 10 has an on-chip True Random Number Generator (TRNG) 20; the first-type peripheral interface D1 further includes: and the third peripheral interface D13 is used for connecting a peripheral random number generator, and the third peripheral interface D13 and the on-chip true random number generator 20 are connected with the luminous coding and control module 19 through a gate 21. The illumination encoding and control module 19 performs random number control of the optical signaling device in the QKD system based on two random number generators.

In the manner shown in fig. 5, the SOC chip is used solely for data processing and control of the optical signal transmitting device in the QKD system, and can be connected to the light source subsystem in the optical signal transmitting device only through the second peripheral interface D12, and can detect the operating parameters of the elements in the optical signal transmitting device through the second type peripheral interface D2.

The SOC architecture chip 10 according to the above embodiments further includes: a third type peripheral interface D3, where the third type peripheral interface D3 is connected to the second bus bridge 21 through a third interconnecting bus alone, and the second bus bridge 21 is connected to the first interconnecting bus 11; the third interconnect bus is an AXI bus. The third type peripheral interface D3 is used to connect an external DDR3 chip, so that the SOC framework chip 10 is connected with external data and a programmer to form a working system.

As shown in fig. 5, the lighting coding and control module 19 is connected to the peripheral interface D3 of the third type through one of the third interconnection buses alone; the QKD module 12 is separately connected to the peripheral interfaces D3 of the third type via one of the third interconnecting buses.

In the SOC architecture chip according to each of the embodiments described above, the SOC architecture chip further includes: a fourth type peripheral interface D4 connected to the QKD module 12 and the first interconnection bus 11, respectively, where the fourth type peripheral interface D4 is used to connect an ethernet PHY chip to form an ethernet network. The fourth type peripheral interface D4 is the interface of TCP/IP protocol and GMAC protocol.

In the SOC architecture chip according to each of the embodiments described above, the SOC architecture chip further includes: and the fifth type peripheral interface D5 is connected with the first interconnection bus 11, and the fifth type peripheral interface D5 is used for connecting an off-chip program flash memory. The fifth type of peripheral interface D5 may be an eMMc interface.

Based on the above embodiments, the SOC architecture chip may also be as shown in fig. 6, and fig. 6 is still another SOC architecture chip for a QKD system according to an embodiment of the present invention, in this manner, the SOC architecture chip concurrently has a peripheral interface and a built-in functional module for connecting an optical signal transmitting device and an optical signal detecting device in the QKD system, and when the chip is in operation, one of the optical signal transmitting device and the optical signal detecting device may be selectively connected to perform data processing and control on the chip.

In the above embodiments, the SOC architecture chip may further include a DMA controller connected to the first interconnection bus 11.

In the embodiment of the present invention, each of the interconnection buses, the interfaces, and the bus bridges may select a type that satisfies a preset communication standard based on a requirement, and the types of each of the interconnection buses, the interfaces, and the bus bridges in the embodiment of the present invention are not limited to the manner described in the embodiment of the present invention.

The structure and the working principle of the SOC architecture chip shown in fig. 6 in the embodiment of the present invention are explained below, but the structure and the working principle of the SOC architecture chip that can only connect to one of the optical signal transmission and detection devices in the QKD system may refer to the following description, and will not be described again in detail later.

Most of the modules in the chip are connected to the network of the first interconnect bus 11, and different modules are set as the master and slave identities of the first interconnect bus 11 according to the data transmission priority and control requirements. The second interconnecting bus 13 is connected to the network of the first interconnecting bus 11 through the first bus bridge 14, and the third type peripheral interface D3 is connected to the network of the first interconnecting bus 11 through the second bus bridge 21. In addition, the light emitting coding and control module 19 is directly connected to the third type peripheral interface D3 as a channel for sending the original photon information to be stored in the external DDR, and is not interconnected through the first interconnection bus 11.

The SOC framework chip is connected with an external subsystem through the following four peripheral interfaces: outputting a light source driving signal to a light source subsystem through a second external interface D12 supporting a high-speed signal; secondly, the external TDC is connected through a first peripheral interface D11 to complete the configuration of the off-chip TDC and the reading of the measurement result; connecting an Ethernet PHY chip through a fourth type peripheral interface D4 to form Ethernet connection; and outputting the quantum key through the application port 18.

The SOC framework chip is required to be connected with external data and a programmer to form a self working system, wherein external DDR3 chip particles are connected through a third type of peripheral interface D3; an off-chip program Flash memory (Flash) is connected through a fifth type peripheral interface D5. In addition, the SOC framework chip is connected with corresponding ports of the light source and receiving subsystem through a low-speed peripheral interface 17 so as to realize monitoring of the light source or the detector; the third peripheral interface D13 for transmitting high-speed signals is connected to an external high-speed random number generator to read in random numbers.

The SOC chip integrates all functions of QKD algorithm data processing, light source and detector interfaces, interactive networks, in-chip and out-chip storage, interfaces and the like by adopting a brand-new data processing and control framework system, a CPU IP inner core is embedded in a chip, each data processing and control hardware module is connected to an internal bus, the flow direction of data is scheduled by adopting software, and the quantum key is finally refined by the cooperative work of the software and the hardware.

QKD module 12 is a generic term for the macro module that performs all the algorithm functions for quantum key distribution, and includes the optical signal transmission device macro module and/or the optical signal detection device macro module. The SRAM is a general term for all on-chip memories which complete the quantum key distribution function, and in one mode of the embodiment of the invention, the on-chip memory comprises 16 SRAM blocks with different sizes, and the SRAM blocks are configured near different QKD sub-function modules and used for data caching.

The CPU subsystem 15 in the chip includes a CPU, and completes system start/stop, hardware configuration and peripheral driver, application end command analysis and issuing, data scheduling, flow management, and the like through software execution. The process management of quantum key generation is realized by adopting a CPU and software, the control dimensionality of data processing is increased, the pipeline management of the data processing process can be realized, and the overall data processing throughput rate is improved. The system is configured by software, so that the same chip can be selected from the optical signal sending device and the optical signal detecting device, and various light emitting rates can be selected by software configuration.

The SOC framework chip provided by the embodiment of the invention can greatly reduce the volume of equipment, simplify the structure of a system, enhance the reliability of the system, improve the performance of the system, reduce side channel attack points in key equipment, reduce the cost and power consumption of the system, and is favorable for modularization of a QKD system and formation of an industrial standard.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.