阅读说明：本技术 单处理器系统的伺服器主机板 (Server mainboard of uniprocessor system ) 是由 刘叶 于 2021-03-15 设计创作，主要内容包括：本发明提供了一种单处理器系统的伺服器主机板,包含复数个PCIe端口、一复杂可程序逻辑装置、一中央处理器、一基板管理控制器以及一隔离电路。复杂可程序逻辑装置以复数个PCIe通道电性连接于PCIe端口。中央处理器用以透过复数个PCIe重置引脚发送至少一PCIe重置讯号至复杂可程序逻辑装置,使复杂可程序逻辑装置依据PCIe重置讯号重置PCIe信道。基板管理控制器用以控制复杂可程序逻辑装置的更新。隔离电路设置于复杂可程序逻辑装置与基板管理控制器之间,用以在复杂可程序逻辑装置进行更新作业时,防止复杂可程序逻辑装置误触发基板管理控制器的重置作业。(The invention provides a server mainboard of a single processor system, which comprises a plurality of PCIe ports, a complex programmable logic device, a central processing unit, a substrate management controller and an isolation circuit. The complex programmable logic device is electrically connected with the PCIe port through a plurality of PCIe channels. The central processing unit is used for sending at least one PCIe reset signal to the complex programmable logic device through the plurality of PCIe reset pins so that the complex programmable logic device resets a PCIe channel according to the PCIe reset signal. The baseboard management controller is used for controlling the updating of the complex programmable logic device. The isolation circuit is arranged between the complex programmable logic device and the substrate management controller and is used for preventing the complex programmable logic device from mistakenly triggering the reset operation of the substrate management controller when the complex programmable logic device carries out updating operation.)

1. A server motherboard for a single processor system, comprising:

a plurality of PCIe ports for mounting at least one PCIe device;

a complex programmable logic device electrically connected to the plurality of PCIe ports by a plurality of PCIe channels;

a central processing unit electrically connected to the complex programmable logic device through a plurality of PCIe reset pins for sending at least one PCIe reset signal to the complex programmable logic device through the plurality of PCIe reset pins, so that the complex programmable logic device resets at least one of the plurality of PCIe channels according to the PCIe reset signal;

a substrate management controller electrically connected to the complex programmable logic device for controlling the updating operation of the complex programmable logic device; and

the isolating circuit is arranged between the complex programmable logic device and the substrate management controller and is used for preventing the complex programmable logic device from falsely triggering the reset operation of the substrate management controller when the complex programmable logic device carries out updating operation.

2. The server motherboard of claim 1 wherein the complex programmable logic device further comprises a reset module electrically connected to the plurality of PCIe reset pins of the central processing unit to reset at least one of the plurality of PCIe lanes upon receiving the at least one PCIe reset signal.

3. The server motherboard of claim 2 wherein the bmc further comprises a PCIe lane reset status monitor module for detecting whether the reset module controls the plurality of PCIe lanes to be reset.

4. The server motherboard of claim 1 wherein said isolation circuit comprises:

a logic gate unit electrically connected to the BMC Reset pin of the complex programmable logic device;

the first MOS transistor is electrically connected with the logic gate unit; and

and the second MOS transistor is electrically connected with the first MOS transistor and the Reset pin of the substrate management controller.

5. The server motherboard of claim 1 wherein said central processing unit is an AMD processor.

Technical Field

The present invention relates to a server motherboard, and more particularly, to a server motherboard of a single processor system.

Background

Referring to FIG. 1, FIG. 1 is a block diagram of a dual processor system according to the prior art. As shown in FIG. 1, a dual-processor system PA100 includes two processors (CPUs) PA1a and PA1b, a Complex Programmable Logic Device (CPLD) PA2, a plurality of Buffer (Buffer) PA3 (only one is shown), and a plurality of PCIe ports PA4 (only one is shown).

As mentioned above, the early dual-processor PA100 is mostly based on the Intel dual-processor system, so the server motherboard is designed to reserve a channel between the two processors PA1a and PA1b, so that the channel connected to the complex programmable logic device PA2 is limited, and the complex programmable logic device PA2 also needs to be connected to multiple PCIe ports PA4 through the buffer PA 3.

In recent years, AMD has been favored by manufacturers because its performance is superior to that of processors in the server market, and because one processor can replace the dual processor of Intel, early server systems were designed mainly for the dual processor of Intel, and therefore, if AMD's processors were used in existing dual processor systems, they would not be able to effectively utilize their performance, and because the dual processor motherboard would need to have two processors, which would result in wasted performance, it would be necessary to develop a new uni-processor operating system to match AMD's processors in order to effectively utilize AMD's processors.

In addition, in the conventional dual-processor system PA100, the complex programmable logic device PA2 is also used to control the reset operation of the board management controller (not shown), however, when the firmware of the complex programmable logic device PA2 is updated, the reset operation of the board management controller is easily triggered by mistake, and the dual-processor system PA100 cannot operate normally.

Disclosure of Invention

In view of the prior art, most of the existing servers are based on the dual-processor operating system of Intel, however, when the processors proposed by AMD can replace the dual-processor of Intel, the processors of AMD cannot be effectively used because the existing server motherboard is mainly designed according to the dual-processor system of Intel, and the existing dual-processor system has the problem that the reset operation of the board management controller is easily triggered by mistake when the firmware is updated by the complicated programmable logic device; therefore, the main objective of the present invention is to provide a server motherboard of a single processor system, which can effectively cooperate with an operating system of a single processor.

The present invention provides a server motherboard of a single processor system, which includes a plurality of pcie (peripheral Component Interconnect express) ports, a Complex Programmable Logic Device (CPLD), a central processing unit (cpu), a Board Management Controller (BMC), and an isolation circuit.

The plurality of PCIe ports are used for installing at least one PCIe device. The complex programmable logic device is electrically connected to the plurality of PCIe ports by a plurality of PCIe channels (lanes). The central processing unit is electrically connected with the complex programmable logic device through a plurality of PCIe reset pins and is used for sending at least one PCIe reset signal to the complex programmable logic device through the plurality of PCIe reset pins so that the complex programmable logic device resets at least one of the plurality of PCIe channels according to the PCIe reset signal.

The substrate management controller is electrically connected to the complex programmable logic device and is used for controlling the updating operation of the complex programmable logic device. The isolation circuit is arranged between the complex programmable logic device and the substrate management controller and is used for preventing the complex programmable logic device from falsely triggering the reset operation of the substrate management controller when the complex programmable logic device carries out updating operation.

Optionally, the complex programmable logic device further comprises a reset module electrically connected to the plurality of PCIe reset pins of the central processing unit, so as to reset at least one of the plurality of PCIe lanes when receiving the at least one PCIe reset signal. Preferably, the bmc further includes a PCIe channel reset status monitoring module configured to detect whether the reset module controls the PCIe channel resets.

Optionally, the isolation circuit includes a logic gate unit, a first MOS transistor and a second MOS transistor. The logic gate unit is electrically connected with the BMC Reset pin of the complex programmable logic device. The first MOS transistor is electrically connected to the logic gate unit. The second MOS transistor is electrically connected with the first MOS transistor and a Reset pin of the substrate management controller.

Optionally, the central processor is an AMD processor.

As described above, in the present invention, the isolation circuit is disposed between the complex programmable logic device and the bmc, so that when the complex programmable logic device performs the update operation, the isolation circuit can prevent the complex programmable logic device from falsely triggering the reset operation of the bmc, and the server motherboard of the single processor system of the present invention can still normally operate when the complex programmable logic device performs the firmware update.

The present invention will be further described with reference to the following examples and accompanying drawings.

Drawings

FIG. 1 is a system architecture diagram of a prior art dual processor system;

FIG. 2 is a circuit diagram of a signal transmission circuit of a server motherboard of the single processor system according to the preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of a circuit system of a server motherboard of the single processor system according to the preferred embodiment of the present invention; and

FIG. 4 is a circuit diagram of an isolation circuit of a server motherboard of a single processor system according to a preferred embodiment of the present invention.

In the figure, the position of the upper end of the main shaft,

PA 100-Dual processor System;

PA1a, PA1 b-processor;

PA 2-Complex programmable logic device;

PA 3-buffer;

PA4-PCIe port;

100-server motherboard of single processor system;

1 a-a PCIe port;

1 b-a PCIe port;

1 c-a PCIe port;

2-complex programmable logic devices;

21-a reset module;

3-a central processing unit;

4-a baseboard management controller;

41-PCIe channel reset state monitoring module;

5-an isolation circuit;

51-logic gate unit;

52-first MOS transistor;

53-second MOS transistor;

6-buffer.

Detailed Description

Referring to fig. 2, fig. 2 is a circuit diagram of signal transmission of a server motherboard of a single processor system according to a preferred embodiment of the invention. As shown in fig. 2, a server motherboard 100 of a single processor system includes eight PCIe (peripheral Component Interconnect express) ports 1a (only one is labeled), six PCIe ports 1b (only one is labeled), a PCIe port 1c, a Complex Programmable Logic Device (CPLD) 2, a Central Processing Unit (CPU) 3, a Baseboard Management Controller (BMC) 4, an isolation circuit 5, and a Buffer (Buffer) 6.

The PCIe ports 1a, 1b and 1c are used for installing at least one PCIe device; in this embodiment, the PCIe ports 1a and 1b are PCIe slots (PCIe slots), and the PCIe port 1c is a network card port (OCP 3.0).

Referring to fig. 3, fig. 3 is a schematic circuit diagram of a server motherboard of a single processor system according to a preferred embodiment of the invention. As shown in fig. 2 and 3, the complex programmable logic device 2 is electrically connected to the PCIe ports 1a, 1b and 1c through a plurality of PCIe lanes (lanes), and the complex programmable logic device 2 further includes a reset module 21, and the reset module 21 resets at least one of the PCIe lanes when receiving at least one PCIe reset signal.

The central processing unit 3 is electrically connected to the reset module 21 of the complex programmable logic device 2 through eight PCIe reset pins (the PCIe reset pins are Plinkreset0-Plinkreset3 and the Glinkreset0-Glinkreset3 in the central processing unit 3 of fig. 3), and is configured to send at least one PCIe reset signal to the reset module 21 of the complex programmable logic device 2 through the PCIe reset pins, so that the complex programmable logic device 2 resets at least one of the PCIe channels connected to the PCIe ports 1a, 1b, and 1c according to the PCIe reset signal.

The baseboard management controller 4 is electrically connected to the complex programmable logic device 2, and is used for controlling the updating operation of the complex programmable logic device 2; the bmc 4 further includes a PCIe reset status monitoring module 41 for detecting whether the reset module 21 controls the PCIe channel reset. The isolation circuit 5 is disposed between the complex programmable logic device 2 and the bmc 4, and is used to prevent the complex programmable logic device 2 from falsely triggering the reset operation of the bmc 4 when the complex programmable logic device 2 performs the update operation.

Referring to fig. 4, fig. 4 is a circuit diagram of an isolation circuit of a server motherboard of a single processor system according to a preferred embodiment of the invention. As shown in fig. 2 to 4, the isolation circuit 5 includes a logic gate unit 51, a first MOS transistor 52 and a second MOS transistor 53, the logic gate unit 51 has a first input pin, a second input pin and an output pin, the first input pin is electrically connected to the BMC Reset pin of the complex programmable logic device 2, the second input pin is grounded and electrically connected to the BMC Ready pin of the substrate management controller 4, the output pin of the logic gate unit 51 is electrically connected to the first MOS transistor 52, and the second MOS transistor 53 is electrically connected to the first MOS transistor 52 and the Reset pin of the substrate management controller 4.

As mentioned above, before the BMC Ready pin of the BMC 4 is not loaded with the firmware, the BMC Ready pin of the BMC 4 is kept at the low voltage, and at this time, if the complex programmable logic device 2 sends the BMC Reset signal to the first input pin through the BMC Reset pin, the logic gate unit 51 performs the logic operation because the second input pin is grounded and the connected BMC Ready pin of the BMC 4 is at the low voltage, so that the output pin outputs an intermediate signal to the first MOS transistor 52, and then the output pin is controlled by the power voltage of the first MOS transistor 52 and the power voltage of the second MOS transistor 53 to generate a Reset signal to the Reset pin of the BMC 4. However, after the BMC 4 is loaded with firmware, the BMC Ready pin of the BMC 4 is controlled by the BMC 4 to be kept at a high voltage level, so that if the complex programmable logic device 2 erroneously sends the BMC reset signal to the first input pin due to update, the logic gate unit 51 is also kept at a high voltage level due to the BMC Ready pin connected to the second input pin, so that the logic operation of the logic gate unit 51 does not output an intermediate signal to the first MOS transistor 52, thereby preventing the complex programmable logic device 2 from erroneously triggering the reset operation of the BMC 4.

Referring to fig. 2, as shown in fig. 2, the buffer 6 is electrically connected to the bmc 4 and the PCIe port 1b for buffering data to be transmitted to the PCIe port 1b by the bmc 4, and the bmc 4 is used for controlling the reset operation of the buffer 6. The buffer 6 of the present embodiment is a buffer (clock buffer) for controlling timing.

In summary, since most of the existing servers are based on the dual-processor operating system of Intel and the existing server motherboard is designed according to the dual-processor system of Intel, even if the AMD releases the single processor that can replace the dual-processor of Intel, the processor of the AMD cannot effectively exert the proper performance because the existing server motherboard cannot effectively support the single processor, and the existing dual-processor system has a problem that the reset operation of the board management controller is easily triggered by mistake when the firmware is updated by the complicated programmable logic device. Compared with the prior art, the isolation circuit is arranged between the complex programmable logic device and the substrate management controller, so that when the complex programmable logic device performs updating operation, the complex programmable logic device can be prevented from mistakenly triggering the resetting operation of the substrate management controller through the isolation circuit, and the server mainboard of the single processor system can further normally operate when the complex programmable logic device performs firmware updating.

In view of the above, the present invention not only retains the reset function between the original complex programmable logic device, the baseboard management controller and the CPU, but also adds the reset control of the baseboard management controller to the buffers, so that the buffers for timing control can be started according to the time required by the user, and the reset can be performed by starting the reset when the buffers are invalid. In addition, because the invention also utilizes the complicated programmable logic device to directly control the reset of a plurality of PCIe channels (lanes), compared with the method that the existing complicated programmable logic device needs a plurality of IO buffers because of less input/output pins (I/O pins), the invention not only reduces the cost, but also can effectively save the space, and can also directly control the reset of the PCIe device arranged on the PCIe port through the complicated programmable logic device, thereby meeting the requirement of one-to-one mapping of PCIe reset and clock of the AMD central processing unit.

The above detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and is not intended to limit the scope of the present invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims.