阅读说明：本技术 多相开关变换器及其控制器和控制方法 (Multiphase switching converter, controller and control method thereof ) 是由 姜礼节 许彬慈 刘超 于 2021-01-29 设计创作，主要内容包括：本发明公开了多相开关变换器及其控制电路和控制方法。多相开关变换器包括多个开关电路,控制器包括：置位信号产生电路、分频电路、以及多个子控制电路,置位信号产生电路根据输出电压和总输出电流产生置位信号,分频电路根据置位信号在多个输出端产生多个分频信号,每个子控制电路基于相应的分频信号产生相应的开关控制信号,使得当总输出电流大于一电流参考信号时,相应的开关电路维持关断,直至总输出电流小于电流参考信号时,基于输出电压和电压参考信号控制相应的开关电路导通。(The invention discloses a multiphase switching converter, a control circuit and a control method thereof. The multiphase switching converter includes a plurality of switching circuits, and the controller includes: the setting circuit generates setting signals according to output voltage and total output current, the frequency dividing circuit generates a plurality of frequency dividing signals at a plurality of output ends according to the setting signals, and each sub-control circuit generates corresponding switch control signals based on the corresponding frequency dividing signals, so that when the total output current is greater than a current reference signal, the corresponding switch circuit is kept off, and when the total output current is less than the current reference signal, the corresponding switch circuit is controlled to be switched on based on the output voltage and the voltage reference signal.)

1. A controller for a multiphase switching converter including a plurality of switching circuits having outputs coupled together to provide an output voltage, the controller generating a plurality of switching control signals to control the plurality of switching circuits to conduct in sequence, the controller comprising:

a set signal generating circuit for generating a set signal according to the output voltage and the total output current;

the frequency dividing circuit is provided with an input end and a plurality of output ends, wherein the input end is coupled to the setting signal generating circuit to receive the setting signal, and the frequency dividing circuit sequentially generates a plurality of frequency dividing signals at the plurality of output ends according to the setting signal;

and each sub-control circuit is provided with an input end and an output end, wherein the input end is coupled to the corresponding output end of the frequency dividing circuit to receive the corresponding frequency dividing signal, and the output end generates a corresponding switch control signal based on the corresponding frequency dividing signal, so that when the total output current is greater than a current reference signal, the corresponding switch circuit is kept off until the total output current is less than the current reference signal, and the corresponding switch circuit is controlled to be switched on based on the output voltage and the voltage reference signal.

2. The controller of claim 1, further comprising:

a plurality of overcurrent detection circuits, each of which detects whether or not a corresponding switch circuit is overcurrent based on a current flowing through the corresponding switch circuit; wherein

Each sub-control circuit is further coupled to the corresponding over-current detection circuit and controls the corresponding switch circuit to be kept off when the corresponding switch circuit is detected to be over-current.

3. The controller of claim 2, wherein the plurality of sub-control circuits comprises:

the logic circuit is provided with a first input end, a second input end and an output end, wherein the first input end is coupled to the corresponding output end of the frequency dividing circuit to receive the frequency dividing signal, the second input end is coupled to the corresponding output end of the over-current detection circuit to receive the over-current signal, and the output end generates a sub-set signal according to the frequency dividing signal and the over-current signal; and

and the trigger circuit is provided with a set end, a reset end and an output end, wherein the set end is coupled to the logic circuit to receive the sub-set signal, the reset end receives a conduction time control signal for controlling the conduction time of the corresponding switch circuit, and the output end is coupled to the corresponding switch circuit to provide the switch control signal.

4. The controller of claim 1, wherein the set signal generating circuit further comprises:

a voltage control circuit for generating a voltage control signal based on a comparison of a voltage feedback signal representative of the output voltage and a voltage reference signal generated based on the desired voltage signal and the first slope compensation signal;

a total current control circuit for generating a current control signal based on a comparison of a current feedback signal representative of the total output current and a current reference signal, the current reference signal being generated based on an expected total current signal and a second slope compensation signal; and

and a logic circuit generating a set signal according to the voltage control signal and the current control signal, wherein the logic circuit generates the set signal according to the voltage control signal when the current control signal is in a first state, and generates the set signal according to the current control signal when the current control signal is in a second state.

5. The controller of claim 4, wherein the total current control circuit comprises:

the first operational circuit is provided with a first input end, a second input end and an output end, wherein the first input end receives the expected total current signal, the second input end receives the second slope compensation signal, and the output end outputs a current reference signal according to the sum of the expected total current signal and the second slope signal; and

a first comparator having a first input terminal receiving a current feedback signal representative of a total output current of the plurality of switching circuits, a second input terminal receiving a current reference signal, and an output terminal, the first comparator generating a current control signal at the output terminal based on the current feedback signal and the current reference signal.

6. The controller of claim 4, wherein:

when the controller controls the conduction of the corresponding switch circuit according to the output voltage, the first slope compensation signal maintains an initial value in the next first time period and then gradually increases with a first slope; and

when the controller controls the conduction of the corresponding switch circuit according to the total output current, the second slope compensation signal maintains the initial value in the next second time period and then gradually increases with a second slope.

7. The controller of claim 4, wherein the voltage control circuit comprises:

a second operational circuit having a first input terminal receiving the expected voltage signal, a second input terminal receiving the first slope compensation signal, and an output terminal outputting a voltage reference signal according to a sum of the expected voltage signal and the first slope compensation signal; and

a second comparator having a first input terminal receiving a voltage feedback signal representative of the output voltage, a second input terminal receiving a voltage reference signal, and an output terminal, the second comparator generating a voltage control signal at the output terminal based on the voltage feedback signal and the voltage reference signal.

8. A multiphase switching converter comprising:

a plurality of switching circuits having outputs coupled together to provide an output voltage; and

a controller as claimed in any one of claims 1 to 7.

9. A control method for a multiphase switching converter including a plurality of switching circuits having outputs coupled together to provide an output voltage, the control method comprising:

generating a voltage control signal based on the voltage reference signal and the output voltage;

generating a current control signal based on a current reference signal and a total output current of the plurality of switching circuits; and

generating a set signal based on the voltage control signal and the current control signal;

sequentially generating a plurality of switch control signals based on the setting signal so as to control a plurality of switch circuits to be sequentially conducted; and

controlling the turn-off time of the corresponding switching circuit according to a turn-on duration signal representing the turn-on duration of the corresponding switching circuit; wherein

When the total output current of the plurality of switch circuits is greater than the current reference signal, the current-phase switch circuit is kept turned off until the total output current of the plurality of switch circuits is less than the current reference signal, and the turn-on time of the current-phase switch circuit is controlled based on the output voltage and the voltage reference signal.

10. The control method according to claim 9, further comprising:

when the current phase switching circuit is detected to be over-current, the current phase switching circuit is kept off, and the next phase switching circuit is controlled.

11. The control method of claim 9, wherein the voltage reference signal is equal to a sum of the desired voltage signal and the first slope compensation signal minus the first offset signal, and the current reference signal is equal to a sum of the desired voltage signal and the second slope compensation signal minus the second offset signal.

Technical Field

The present invention relates to electronic circuits, and more particularly, to a multiphase switching converter, a controller thereof, and a control method thereof.

Background

In recent years, with the advent of high-performance processors, switching converters with smaller output voltage and larger output current are required, and the requirements on the thermal performance and dynamic response performance of the switching converters are also higher and higher. Multiphase switching converters are becoming more and more widely used with their superior performance. A multiphase switching converter includes a plurality of switching circuits having outputs coupled together to provide power to a load. However, it is necessary to design a multiphase switching converter that can provide overcurrent protection for each phase of the switching circuit and can also ensure stable operation of the multiphase switching converter.

Disclosure of Invention

The present invention is directed to solve the above problems in the prior art, and provides a multiphase switching converter, a controller and a control method thereof.

A controller for a multiphase switching converter according to an embodiment of the present invention, the multiphase switching converter including a plurality of switching circuits, outputs of the plurality of switching circuits being coupled together to provide an output voltage, the controller generating a plurality of switching control signals to control the plurality of switching circuits to be sequentially turned on, the controller comprising: a set signal generating circuit for generating a set signal according to the output voltage and the total output current; the frequency dividing circuit is provided with an input end and a plurality of output ends, wherein the input end is coupled to the setting signal generating circuit to receive the setting signal, and the frequency dividing circuit sequentially generates a plurality of frequency dividing signals at the plurality of output ends according to the setting signal; and each sub-control circuit is provided with an input end and an output end, wherein the input end is coupled to the corresponding output end of the frequency dividing circuit to receive the corresponding frequency dividing signal, and the output end generates a corresponding switch control signal based on the corresponding frequency dividing signal, so that when the total output current is greater than a current reference signal, the corresponding switch circuit is kept off until the total output current is less than the current reference signal, and the corresponding switch circuit is controlled to be switched on based on the output voltage and the voltage reference signal.

A multiphase switching converter in accordance with an embodiment of the present invention includes a plurality of switching circuits having outputs coupled together to provide an output voltage; and a controller as described above.

A control method for a multiphase switching converter including a plurality of switching circuits having outputs coupled together to provide an output voltage in accordance with an embodiment of the invention, the control method comprising: generating a voltage control signal based on the voltage reference signal and the output voltage; generating a current control signal based on a current reference signal and a total output current of the plurality of switching circuits; and generating a set signal based on the voltage control signal and the current control signal; sequentially generating a plurality of switch control signals based on the setting signal so as to control a plurality of switch circuits to be sequentially conducted; and controlling the turn-off time of the corresponding switching circuit according to a turn-on duration signal representing the turn-on duration of the corresponding switching circuit; when the total output current of the plurality of switch circuits is greater than the current reference signal, the current phase switch circuit is kept turned off until the total output current of the plurality of switch circuits is less than the current reference signal, and the turn-on time of the current phase switch circuit is controlled based on the output voltage and the voltage reference signal.

In the embodiment of the invention, the control of the total output current by the multi-phase switching converter increases the safety of the system, so that the multi-phase switching converter can automatically and smoothly switch between the regulation of the output voltage and the regulation of the total output current, and the imbalance of the current among the switching circuits caused by the continuous increase of the total output current is avoided.

Drawings

FIG. 1 shows a block circuit diagram of a multiphase switching converter 100 in accordance with an embodiment of the invention;

fig. 2 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to an embodiment of the present invention;

fig. 3 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention;

fig. 4 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention;

fig. 5 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention;

FIG. 6 illustrates a waveform diagram for the multiphase switching converter 100 of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 7 illustrates a waveform diagram for the multiphase switching converter 100 of FIG. 1 in accordance with another embodiment of the invention;

FIG. 8A illustrates a circuit schematic of the sub-control circuit 25-i of FIG. 1 according to an embodiment of the present invention;

FIG. 8B illustrates a circuit schematic of the sub-control circuit 25-i of FIG. 1 according to another embodiment of the present invention;

FIG. 9 illustrates a circuit schematic of the total current calculation circuit 26 of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 10 illustrates a state transition diagram 500 for the frequency divider circuit 22 of FIG. 1 in accordance with an embodiment of the present invention;

fig. 11 shows a block circuit diagram of a multiphase switching converter 100 according to another embodiment of the invention;

fig. 12 shows a flow chart 800 of the operation of a multiphase switching converter in accordance with an embodiment of the invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.

Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Embodiments of the present invention provide a multiphase switching converter including a plurality of switching circuits, each of which is sequentially turned on based on an output voltage of the multiphase switching converter and a total output current of the plurality of switching circuits in a normal operation state. When the total output current of the plurality of switch circuits is greater than the current reference signal, the multiphase switch converter controls the corresponding switch circuit to be temporarily non-conductive until the total output current of the plurality of switch circuits is less than the current reference signal, and the multiphase switch converter controls the corresponding switch circuit to be conductive based on the output voltage. And when the current phase switching circuit is detected to be overcurrent, the multiphase switching converter skips the current phase switching circuit and keeps the other phase switching circuits to work normally. In the embodiment of the present invention, the "current-phase switching circuit" or the "corresponding switching circuit" refers to a switching circuit that should be turned on in order. The embodiments are described below by taking as an example a multiphase switching converter using constant on-time control.

Fig. 1 shows a block circuit diagram of a multiphase switching converter 100 according to an embodiment of the invention. The multiphase switching converter 100 includes a controller 20 and a plurality of switching circuits 10-1,10-2, … … 10-n, where n is an integer greater than or equal to 2. The switching circuits 10-1,10-2 … … 10-n have input terminals receiving an input voltage Vin and output terminals coupled together to provide an output voltage Vo to power the load 102. The switching circuits 10-1,10-2, … … 10-n may employ any direct current/direct current (DC/DC) or alternating current/direct current (AC/DC) conversion topology, such as synchronous or asynchronous boost and buck converters, as well as forward and flyback converters, and the like. The output capacitor 105 is coupled between the output of the switching circuit 10-1,10-2, … … 10-n and ground reference.

The controller 20 generates a plurality of control signals PWM1, PWM2, … … PWMn to control the plurality of switching circuits 10-1,10-2, … … 10-n to be turned on sequentially. The controller 20 includes a set signal generating circuit 21, a frequency dividing circuit 22, and a plurality of sub-control circuits 25-1, 25-2, … … 25-n. The SET signal generating circuit 21 is coupled to the output terminals of the plurality of switching circuits 10-1,10-2, … … 10-n, and generates the SET signal SET based on the output voltage Vo and the total output current Io, for example, based on a comparison result of the voltage reference signal Vref and the voltage feedback signal Vfb representing the output voltage Vo, and based on a comparison result of the current reference signal Iref and the current feedback signal Imon representing the total output current Io. The frequency dividing circuit 22 has an input terminal and a plurality of output terminals, wherein the input terminal of the frequency dividing circuit 22 is coupled to the SET signal generating circuit 21 to receive the SET signal SET, and the frequency dividing circuit 22 generates a plurality of frequency-divided signals FD1, FD2, … … FDn at the plurality of output terminals thereof according to the SET signal SET. The sub-control circuit 25-i (i ═ 1,2, … … n) is coupled to the corresponding output terminal of the frequency dividing circuit 22 to receive the frequency dividing signal FDi, and generates a corresponding switching control signal PWMi at its output terminal based on the frequency dividing signal FDi, so that when the total output current Io or the current feedback signal Imon is greater than the current reference signal Iref, the corresponding switching circuit remains off until the total output current Io or the current feedback signal Imon is less than the current reference signal Iref, the corresponding switching circuit is controlled to be on based on the output voltage Vo and the voltage reference signal Vref, for example, when the output voltage Vo or the voltage feedback signal Vfb is less than the voltage reference signal Vref, the current phase switching circuit is controlled to be on.

In one embodiment, controller 20 further includes a plurality of over-current detection circuits 24-1,24-2, … … 24-n. Each of the over-current detection circuits 24-i (i ═ 1,2, … … n) has an input terminal and an output terminal, the input terminal of the over-current detection circuit 24-i is coupled to the corresponding switch circuit 10-i, and the over-current detection circuit 24-i detects whether the corresponding switch circuit 10-i is over-current based on the current flowing through the corresponding switch circuit 10-i, and generates an over-current signal OCi at its output terminal. For example, based on a current sampling signal CSi (i ═ 1,2, … … n) representative of the current flowing through the corresponding switch circuit 10-i, it is detected whether the corresponding switch circuit 10-i is overcurrent, and an overcurrent signal OCi is generated. In one embodiment, when detecting that the current-phase switching circuit is over-current, the multiphase switching converter 100 skips the current-phase switching circuit, for example, controls the current-phase switching circuit to remain off, and keeps the remaining-phase switching circuits operating normally. In one embodiment, sub-control circuits 25-i (i ═ 1,2, … … n) are further coupled to the outputs of respective over-current detection circuits 24-i to receive over-current signal OCi, and sub-control circuits 25-i generate respective switch control signals PWMi based on frequency divided signal FDi and over-current signal OCi.

In one embodiment, the controller 20 further includes a total current calculating circuit 26 having a plurality of inputs and an output, the plurality of inputs of the total current calculating circuit 26 being coupled to the plurality of switching circuits 10-1,10-2, … … 10-n respectively to receive the plurality of current sampling signals CS1, CS2, … … CSn, the output of the total current calculating circuit 26 providing a current feedback signal Imon representing the total output current of the plurality of switching circuits 10-1,10-2, … … 10-n according to the plurality of current sampling signals CS1, CS2, … … CSn. Wherein the current sampling signals CS1, CS2, … … CSn respectively represent the current flowing through the corresponding switch circuit.

In one embodiment, the multiphase switching converter 100 further includes a voltage detection circuit 101. The voltage detection circuit 101 samples the output voltage Vo and generates a voltage feedback signal Vfb according to the output voltage Vo.

According to the embodiment of the invention, the control of the total output current by the multi-phase switching converter increases the safety of the CPU load, so that the multi-phase switching converter can automatically and smoothly switch between the regulation of the output voltage and the regulation of the total output current, and the imbalance of the current among the switching circuits caused by the continuous increase of the total output current is avoided.

Fig. 2 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to an embodiment of the present invention. In the embodiment shown in fig. 2, the set signal generating circuit 21 includes a voltage control circuit 220, a total current control circuit 210, and a logic circuit 230. The voltage control circuit 220 generates the voltage control signal Vctrl according to the comparison between the voltage feedback signal Vfb and the voltage reference signal Vref. The total current control circuit 210 generates a current control signal Ictrl according to the comparison between the current feedback signal Imon and the current reference signal Iref. The logic circuit 230 SETs the signal SET according to the voltage control signal Vctrl and the current control signal Ictrl. Wherein the logic circuit 230 generates the SET signal SET according to the voltage control signal Vctrl when the current control signal Ictrl is in a first state (e.g., low level), and the logic circuit 230 generates the SET signal SET according to the current control signal Ictrl when the current control signal Ictrl is in a second state (e.g., high level). In one embodiment, logic circuit 230 includes a not gate 231 and an and gate 232. The input terminal of the not gate circuit 231 receives the current control signal Ictrl, and the output terminal of the not gate circuit 231 provides an inverted signal of the current control signal Ictrl. The and circuit 232 has a first input terminal, a second input terminal, and an output terminal, the first input terminal of the and circuit 232 is coupled to the output terminal of the not circuit 231, the second input terminal of the and circuit 232 receives the voltage control signal Vctrl, and the output terminal of the and circuit 232 provides the SET signal SET according to the voltage control signal Vctrl and the current control signal Ictrl.

In the embodiment shown in fig. 2, the set signal generating circuit 21 further includes a reference voltage generating circuit 240. In one embodiment, the reference voltage generation circuit 240 provides a voltage reference signal Vref according to the sum of the desired voltage signal Vtarget and the first Slope compensation signal Slope1 (Vtarget + Slope 1). The desired voltage signal Vtarg represents the voltage required by the load, e.g. equal to 1V. In the embodiment shown in fig. 2, the reference voltage generating circuit 240 includes an operational circuit 221, and the operational circuit 221 receives the desired voltage signal Vtarg and the first Slope compensation signal Slope1 and provides a voltage reference signal Vref at an output terminal.

In the embodiment shown in fig. 2, the set signal generating circuit 21 further includes a reference current generating circuit 250. In one embodiment, the reference current generating circuit 250 provides the current reference signal Iref according to the sum (Itarg + Slope2) of the desired total current signal Itarg and the second Slope compensation signal Slope 2. The expected total current signal Itarg represents the current required by the load, for example equal to 200A. In the embodiment shown in fig. 2, the reference current generating circuit 250 includes an operation circuit 211. The operational circuit 211 receives the desired total current signal Itarg and the second Slope compensation signal Slope1, and provides a current reference signal Iref at an output terminal.

In the embodiment shown in fig. 2, the set signal generating circuit 21 further includes a Slope signal generating circuit 260 that generates a Slope compensation signal Slope1 and a Slope compensation signal Slope 2. In one embodiment, the ramp signal generating circuit 260 generates the ramp compensation signal Slope2 according to the current control signal Ictrl and generates the ramp compensation signal Slope1 according to the voltage control signal Vctrl.

Fig. 3 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 3, the reference voltage generating circuit 240 further includes a selecting circuit 222. The selection circuit 222 selects the operation signal Vcal or the desired voltage signal Vtarg as the voltage reference signal Vref according to the current control signal Ictrl, wherein the operation signal Vcal is equal to the sum (Vtarg + Slope1) of the desired voltage signal Vtarg and the first Slope compensation signal Slope 1. In one embodiment, when the current feedback signal Imon is continuously less than the current reference signal Iref for a certain period of time, the current control signal Ictrl is continuously in a first state, e.g., low level, and the reference voltage generating circuit 240 selects the operation signal Vcal as the voltage reference signal Vref, i.e., the voltage reference signal Vref is equal to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope 1(Vtarg + Slope1), otherwise when the current feedback signal Imon is greater than the current reference signal Iref, the current control signal Ictrl is changed to a second state, e.g., high level, and the reference voltage generating circuit 240 selects the desired voltage signal Vtarg as the voltage reference signal Vref. In the embodiment shown in fig. 3, the reference current generating circuit 250 further includes a selecting circuit 212. The selection circuit 212 selects the operation signal Ical or the expected total current signal Itarg as the current reference signal Iref according to the current control signal Ictrl, wherein the operation signal Ical is equal to the sum (Itarg + Slope2) of the expected total current signal Itarg and the second Slope compensation signal Slope 2. In one embodiment, when the current feedback signal Imon is continuously less than the current reference signal Iref for a certain period of time, the current control signal Ictrl is continuously in a first state, e.g., low level, the reference current generation circuit 250 selects the desired total current signal Itarg as the voltage reference signal Iref, otherwise when the current feedback signal Imon is greater than the current reference signal Iref, the current control signal Ictrl changes to a second state, e.g., high level, and the reference current generation circuit 250 selects the operation signal Ical as the current reference signal Iref, i.e., the current reference signal Iref is equal to the sum of the desired current signal Itarg and the second Slope compensation signal Slope 2(Itarg + Slope 2).

Fig. 4 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 4, the voltage reference signal Vref is equal to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope1 minus the Bias signal Bias1(Vtarg + Slope1-Bias 1). The current reference signal Iref is equal to the sum of the desired total current signal Itarg and the second Slope compensation signal Slope2 minus the Bias signal Bias2(Itarg + Slope2-Bias 2). The operation circuit 221 receives the desired voltage signal Vtarg, the first Slope compensation signal Slope1, and the Bias signal Bias1, and provides a voltage reference signal Vref at an output terminal according to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope1 minus the Bias signal Bias1(Vtarg + Slope1-Bias 1). The arithmetic circuit 211 receives the expected total current signal Itarg, the second Slope compensation signal Slope1, and the Bias signal Bias2, and subtracts the Bias signal Bias2(Itarg + Slope2-Bias2) from the sum of the expected total current signal Itarg and the second Slope compensation signal Slope2 at the output end to provide the current reference signal Iref.

In the embodiment shown in fig. 4, the set signal generating circuit 21 further includes a bias signal generating circuit 270. In one embodiment, the Bias signal generating circuit 270 generates the Bias signal Bias1 according to the first Slope compensation signal Slope1 and generates the Bias signal Bias2 according to the second Slope compensation signal Slope 2. The Bias signal Bias1 is, for example, equal to the amplitude of the first Slope compensation signal Slope1, and the Bias signal Bias2 is, for example, equal to the amplitude of the second Slope compensation signal Slope 2.

Fig. 5 shows a circuit schematic diagram of the set signal generating circuit 21 shown in fig. 1 according to another embodiment of the present invention. In the embodiment shown in fig. 5, the operation circuit 221 receives the desired voltage signal Vtarg, the first Slope compensation signal Slope1, and the Bias signal Bias1, and provides an operation signal Vcal at an output terminal, where the operation signal Vcal is equal to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope1, and then subtracts the Bias signal Bias1(Vtarg + Slope1-Bias 1). The reference voltage generating circuit 240 further includes a selection circuit 222. The selection circuit 222 selects the operation signal Vcal or the desired voltage signal Vtarg as the voltage reference signal Vref according to the current control signal Ictrl. In one embodiment, when the current feedback signal Imon is continuously less than the current reference signal Iref for a certain period of time, the current control signal Ictrl is continuously in a first state, e.g., a low level, and the reference voltage generating circuit 240 selects the operation signal Vcal as the voltage reference signal Vref, i.e., the voltage reference signal Vref is equal to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope1, and then subtracts the Bias signal Bias1(Vtarg + Slope1-Bias1), otherwise when the current feedback signal Imon is greater than the current reference signal Iref, the reference voltage generating circuit 240 selects the desired voltage signal Vtarg as the voltage reference signal Vref. In the embodiment shown in fig. 5, the arithmetic circuit 211 receives the expected total current signal Itarg, the second Slope compensation signal Slope1, and the Bias signal Bias2, and provides an arithmetic signal Ical at an output terminal, where the arithmetic signal Ical is equal to the sum of the expected total current signal Itarg and the second Slope compensation signal Slope2, and the Bias signal Bias2(Itarg + Slope2-Bias2) is subtracted. The reference current generating circuit 250 further includes a selection circuit 212. The selection circuit 212 selects the operation signal Ical or the expected total current signal Itarg as the current reference signal Iref according to the current control signal Ictrl. In one embodiment, when the current feedback signal Imon is continuously less than the current reference signal Iref for a certain period of time, the current control signal Ictrl is continuously in a first state, e.g., a low level, the reference current generating circuit 250 selects the expected total current signal Itarg as the voltage reference signal Iref, otherwise when the current feedback signal Imon is greater than the current reference signal Iref, the reference current generating circuit 250 selects the operation signal Ical as the current reference signal Iref, i.e., the current reference signal Iref is equal to the sum of the expected current signal Itarg and the second Slope compensation signal Slope2, and then the Bias signal as2(Itarg + Slope2-Bias2) is subtracted from the current reference signal Iref.

Fig. 6 illustrates a waveform diagram for the multiphase switching converter 100 of fig. 1 in accordance with an embodiment of the present invention. Fig. 6 shows a waveform diagram sequentially showing a voltage feedback signal Vfb, a voltage reference signal Vref, a voltage control signal Vctrl, a first Slope compensation signal Slope1, a current reference signal Iref, a current feedback signal Imon, a current control signal Ictrl, a second Slope compensation signal Slope2, and a SET signal SET from top to bottom. In the waveform diagram shown in fig. 6, the current feedback signal Imon is continuously smaller than the current reference signal Iref for a certain period of time, for example, during one switching period or a plurality of switching periods, the current control signal Ictrl keeps a low level state, and the second Slope compensation signal Slope2 keeps an initial value, for example, equal to zero. The voltage reference signal Vref is equal to the sum of the desired voltage signal Vtarg and the first Slope compensation signal Slope1 minus the Bias signal Bias1, and the current reference signal Iref is equal to the desired total current signal Itarg. The controller 20 generates the SET signal SET according to the comparison result of the voltage feedback signal Vfb and the voltage reference signal Vref. As shown in the waveform diagram of fig. 6, when the voltage feedback signal Vfb decreases to be less than the voltage reference signal Vref, the voltage control signal Vctrl becomes high level, the SET signal SET becomes high level, and the controller 20 controls the corresponding switch circuit to be turned on.

In one embodiment, when the controller 20 controls the turn-on of the corresponding switching circuit according to the output voltage Vo (time t 1), the first Slope compensation signal Slope1 maintains an initial value for a next first time period (time t1 to time t 2), and then gradually increases with a first Slope (time t2 to time t 3). Until time t3, the controller 20 controls the next-phase switching circuit to be turned on according to the output voltage Vo, and the first Slope compensation signal Slope recovers to the initial value and maintains the initial value for the next first time period. The initial value of the first Slope compensation signal Slope is, for example, equal to zero.

Fig. 7 illustrates a waveform diagram of the multiphase switching converter 100 of fig. 1 in accordance with another embodiment of the invention. Fig. 7 shows a waveform diagram sequentially showing a voltage feedback signal Vfb, a voltage reference signal Vref, a voltage control signal Vctrl, a first Slope compensation signal Slope1, a current feedback signal Imon, a current reference signal Iref, a current control signal Ictrl, a second Slope compensation signal Slope2, and a SET signal SET from top to bottom. In the waveform diagram shown in fig. 7, when the current feedback signal Imon is greater than the current reference signal Iref, the voltage reference signal Vref is equal to the desired voltage signal Vtarg, the current reference signal Iref is equal to the sum of the desired total current signal Itarg and the second Slope compensation signal Slope2, and then the Bias signal Bias2 is subtracted, the controller 20 controls the SET signal SET to remain at a low level, and the controller 20 controls the corresponding switch circuit to temporarily turn off, that is, even if the voltage feedback signal Vfb is less than the voltage reference signal Vref, the SET signal SET remains at a low level to control the corresponding switch circuit to remain off until the current feedback signal Imon is reduced to be less than the current reference signal Iref, the current control signal Ictrl becomes at a high level, the SET signal SET becomes at a high level, and the controller 20 controls the corresponding switch circuit to turn on.

In one embodiment, when the controller 20 controls the conduction of the corresponding switch circuit according to the total output current Io (time t 4), the second Slope compensation signal Slope2 maintains the initial value for the next second time period (time t4 to time t 5), and then gradually increases with the second Slope (time t5 to time t 6). Until t6, the controller 20 controls the next phase switch circuit to be turned on according to the total output current Io, and the second Slope compensation signal Slope2 restores the initial value and maintains the initial value for the next first time period. The initial value of the second Slope compensation signal Slope2 is, for example, equal to zero.

FIG. 8A illustrates a circuit schematic of the sub-control circuit 25-i of FIG. 1 according to an embodiment of the present invention. In the embodiment shown in FIG. 8A, sub-control circuit 25-i includes a logic circuit 251 and a trigger circuit 252. The logic circuit 251 has a first input terminal coupled to the corresponding output terminal of the frequency divider circuit 22 for receiving the frequency-divided signal FDi, a second input terminal for receiving the over-current signal OCi, and an output terminal for generating the sub-set signal SETi according to the frequency-divided signal FDi and the over-current signal OCi. The trigger circuit 252 has a set terminal S coupled to the logic circuit 251 to receive the sub-set signal SETi, a reset terminal R to receive the on-duration control signal COTi for controlling the on-duration of the corresponding switch circuit 10-i, and an output terminal Q coupled to the corresponding switch circuit 10-i to provide the switch control signal PWMi, and controls the on-time of the corresponding switch circuit based on the frequency division signal FDi and the over-current signal OCi, and controls the off-time of the corresponding switch circuit based on the on-duration control signal COTi. When the over-current signal OCi indicates that the current phase switching circuit is over-current, the corresponding switching circuit is non-conductive.

In one embodiment, sub-control circuits 25-i further include on-period control circuit 253. The on-time control circuit 253 generates an on-time control signal COTi according to the switch control signal PWMi and the on-time signal TONi to control the on-time of the corresponding switch circuit 10-i. The on-time period TONi of the switch circuit 10-i may be set to a constant value or may be a variable value related to the input voltage Vin and/or the output voltage Vo.

FIG. 8B illustrates a circuit schematic of the sub-control circuit 25-i of FIG. 1 according to another embodiment of the present invention. In the embodiment shown in FIG. 8B, sub-control circuit 25-i triggers circuit 252. The trigger circuit 252 has a set terminal S coupled to a corresponding output terminal of the frequency dividing circuit 22 to receive the frequency dividing signal FDi, a reset terminal R to receive the on-duration control signal COTi for controlling the on-duration of the corresponding switch circuit 10-i, and an output terminal Q coupled to the corresponding switch circuit 10-i to provide the switch control signal PWMi, and controls the on-time of the corresponding switch circuit based on the frequency dividing signal FDi and the off-time of the corresponding switch circuit based on the on-duration control signal COTi.

Fig. 9 shows a circuit schematic of the total current calculation circuit 26 of fig. 1 according to an embodiment of the present invention. In one embodiment, total current calculation circuit 26 includes a current summing circuit 261 and an output circuit 262. The current summing circuit 261 is coupled to the plurality of switching circuits 10-1,10-2, … … 10-n to receive the plurality of current sampling signals CS1, CS2, … … CSn, and provides a current summing signal Iinh, representing the sum of the plurality of current sampling signals CS1+ CS2+ … … + CSn, based on the plurality of current sampling signals CS1, CS2, … … CSn. The output circuit 262 provides at its output a current feedback signal Imon representing the total output current of the plurality of switching circuits based on the current addition signal Iinh. In one embodiment, the current summing circuit 261 includes a plurality of resistors 26-1,26-2, … … 26-n, each resistor 26-i (i ═ 1,2, … … n) having one end receiving a respective current sample signal CSi and another end coupled together to provide a current sum signal Iinh. In one embodiment, the output circuit 262 includes a current mirror 263, a bias circuit 264, and an output resistor 265. The input end of the current mirror 263 receives the current addition signal Iinh, the bias end is coupled to the bias circuit 264, and the output end outputs the mirror current Iexh of the current addition signal Iinh. The mirror current Iexh flows through the output resistor 265, and a voltage is generated across the output resistor 265 as a current feedback signal Imon. In one embodiment, the current feedback signal Imon may be represented by the following formula (1).

Imon＝Gain*(CS1+CS2+……+CSn)+Bias (1)

Where Bias represents the voltage at the Bias terminal of the output circuit 262. Gain represents the Gain provided by the current addition circuit 261 and the current mirror 263.

Fig. 10 illustrates a state transition diagram 500 for the frequency divider circuit 22 of fig. 1, including state 50, states 50-1, 50-2, … … 50-n, in accordance with an embodiment of the present invention.

In state 50, divider circuit 22 completes the initial configuration before transitioning to state 51-1.

In the state 51-1, when the SET signal SET is active, e.g., high level, the frequency-divided signal FD1 is active, e.g., becomes high level. When the switch control signal PWM1 controls the switch circuit 10-1 to conduct, for example, when the PWM1 is 1, or when an overcurrent is detected in the switch circuit 10-1, the state transitions to state 51-2.

In the state 51-2, when the SET signal SET is active, e.g., high level, the frequency-divided signal FD2 is active, e.g., becomes high level. When the switch control signal PWM2 controls the switch circuit 10-2 to conduct, for example, when the PWM2 is 1, or when the switch circuit 10-2 is detected to be overcurrent, the next state is shifted. Until state 51-n is entered.

In state 51-n, when the SET signal SET is active, e.g., high, the frequency-divided signal FDn is active, e.g., goes high. When the switch control signal PWMn controls the switch circuit 10-n to be on, for example, PWMn is 1, or an overcurrent is detected in the switch circuit 10-n, the state transitions to the state 51-1. This is repeated.

Fig. 11 shows a block circuit diagram of a multiphase switching converter 100 according to another embodiment of the invention. In the embodiment shown in fig. 6, the switching circuits 10-i (i ═ 1,2, … … n) comprise a driver circuit 61-i, an upper switching tube 62-i, a lower switching tube 63-i, and an inductor 64-i, each switching circuit 10-i further comprising a current sampling circuit 65-i for sampling the current flowing through the switching circuit 10-i, for example the current flowing through the inductor 64-i, or the current flowing through the upper switching tube 62-i and/or the lower switching tube 63-i, and providing a current sampling signal CSi.

FIG. 12 shows a flowchart 800 of the operation of a multiphase switching converter according to an embodiment of the invention, including steps S81-S85.

In step S81, a voltage control signal is generated based on the voltage reference signal and the output voltage.

In step S82, a current control signal is generated based on the current reference signal and the total output current of the plurality of switching circuits.

In step S83, a plurality of switch control signals are generated based on the voltage control signal and the current control signal to control the plurality of switch circuits to be turned on in sequence.

In step S84, when the total output current of the plurality of switching circuits is greater than the current reference signal, the current-phase switching circuit remains off until the total output current of the plurality of switching circuits is less than the current reference signal, and the current-phase switching circuit is controlled to be on based on the output voltage and the voltage reference signal.

In step S85, when overcurrent is detected in the current-phase switching circuit, the current-phase switching circuit remains off, and control is performed on the next-phase switching circuit.

Note that in the flowcharts described above, functions noted in the blocks may also occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the particular functionality involved.

While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.