阅读说明：本技术 电子部件及其制造方法 (Electronic component and method for manufacturing the same ) 是由 大庭悠辅 吉田健一 大塚隆史 奥山祐一郎 花井智也 深江优 于 2021-03-24 设计创作，主要内容包括：本发明提供一种电子部件,其具有底填材料容易浸入的结构。电子部件(1)包括：形成在基片(2)上的、将导体层(M1～M4)和绝缘层(6～8)交替层叠而成的功能层(10)；和设置在绝缘层(8)上的端子电极(41～44)。位于最上层的绝缘层(8),其平面形状为大致矩形,且具有在俯视时从各边(E1～E4)起在平面方向上突出的突出部(81～84)。由此,当在上下反转装载于母板后,供给底填材料时,底填材料因以突出部(81～84)为起点的表面张力而浸入到母板与电子部件的间隙。因此,即使在母板和电子部件的间隙窄的情况下,也能够使底填材料容易浸入。(The invention provides an electronic component having a structure in which an underfill material is easily impregnated. An electronic component (1) includes: a functional layer (10) formed on the substrate (2) and formed by alternately laminating conductive layers (M1-M4) and insulating layers (6-8); and terminal electrodes (41-44) provided on the insulating layer (8). The insulating layer (8) positioned on the uppermost layer has a substantially rectangular planar shape and has protrusions (81-84) protruding in the planar direction from each side (E1-E4) in a plan view. Thus, when the underfill material is supplied after being loaded on the motherboard in a vertically reversed manner, the underfill material enters the gap between the motherboard and the electronic component due to the surface tension starting from the protruding portions (81-84). Therefore, even when the gap between the motherboard and the electronic component is narrow, the underfill material can be easily impregnated.)

1. An electronic component, comprising:

a substrate;

a functional layer formed on the substrate and formed by alternately laminating a plurality of conductor layers and a plurality of insulating layers; and

a plurality of terminal electrodes disposed on an uppermost insulating layer among the plurality of insulating layers,

the insulating layer located at the uppermost layer has a substantially rectangular planar shape and has a protruding portion protruding in the planar direction from at least one side in a plan view.

2. The electronic component of claim 1, wherein:

the protruding portion overlaps with the substrate in a plan view.

3. The electronic component of claim 1 or 2, wherein:

the protruding portion is located at a substantially central portion of the one side.

4. The electronic component of claim 3, wherein:

the plurality of terminal electrodes include a 1 st terminal electrode and a 2 nd terminal electrode,

the one side of the uppermost insulating layer has a 1 st section and a 2 nd section adjacent to the 1 st and 2 nd terminal electrodes, respectively,

the protrusion is located between the 1 st section and the 2 nd section.

5. A method for manufacturing an electronic component, comprising:

a first step of alternately laminating a plurality of conductor layers and a plurality of insulating layers on an aggregate substrate; and

a 2 nd step of cutting the collective substrate to singulate a plurality of electronic components including 1 st and 2 nd electronic components adjacent to each other,

an insulating layer located at an uppermost layer among the plurality of insulating layers, including a 1 st portion belonging to the 1 st electronic component, a 2 nd portion belonging to the 2 nd electronic component, and a bridging structure portion partially connecting the 1 st portion and the 2 nd portion,

the step 1 includes forming a seed layer over the entire surface after forming the insulating layer located at the uppermost layer, and forming a plurality of terminal electrodes by performing electrolytic plating in which the seed layer serves as a power supply body,

in the 2 nd step, the bridge structure portion is divided.

6. An electronic component, comprising:

a substrate;

a functional layer formed on the substrate and formed by alternately laminating a plurality of conductor layers and a plurality of insulating layers; and

a plurality of terminal electrodes disposed on an uppermost insulating layer among the plurality of insulating layers,

the plane size of the insulating layer positioned on the uppermost layer in the insulating layers is smaller than that of the insulating layer positioned on the next upper layer in the insulating layers, so that one part of the upper surface of the insulating layer positioned on the next upper layer in the insulating layers is not covered by the insulating layer positioned on the uppermost layer in the insulating layers and is exposed.

7. The electronic component of claim 6, wherein:

a portion of the upper surface is located at one side thereof.

8. The electronic component of claim 6, wherein:

one side of the insulating layer positioned on the uppermost layer in the insulating layers comprises a 1 st part which is positioned on the inner side of one side of the insulating layer positioned on the next upper layer in the insulating layers in a plan view and a 2 nd part which is consistent with the one side of the insulating layer positioned on the next upper layer in the insulating layers in the plan view.

9. The electronic component of claim 6, wherein:

the maximum width in the 1 st direction of the insulating layer located on the uppermost layer among the plurality of insulating layers is the same as the maximum width in the 1 st direction of the insulating layer located on the second uppermost layer among the plurality of insulating layers.

10. The electronic component of claim 9, wherein:

a maximum width in a 2 nd direction perpendicular to the 1 st direction of an uppermost insulating layer among the plurality of insulating layers is the same as a maximum width in the 2 nd direction of an insulating layer located on a next upper layer among the plurality of insulating layers.

Technical Field

The present invention relates to an electronic component and a method of manufacturing the same, and more particularly to an electronic component in which a substrate is turned upside down and mounted on a motherboard, and a method of manufacturing the same.

Background

Patent documents 1 and 2 disclose electronic components in which a capacitor and an inductor are formed on a substrate. The electronic components described in patent documents 1 and 2 include: a lower electrode and an inductor pattern formed on the lowermost conductor layer; a dielectric film covering the lower electrode and the inductor pattern; and an upper electrode opposed to the lower electrode via the dielectric film. The uppermost conductor layer constitutes a terminal electrode, and is mounted on the motherboard in a state in which the substrate is turned upside down. After the electronic component is mounted on the motherboard, an underfill material may be filled in a gap between the motherboard and the electronic component for the purpose of improving reliability.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2007-142109

Patent document 2: japanese patent laid-open No. 2008-34626

Disclosure of Invention

Problems to be solved by the invention

However, if the gap between the motherboard and the electronic component is narrow, there is a problem that the underfill material is difficult to infiltrate into the gap between the motherboard and the electronic component.

Accordingly, the present invention provides an electronic component mounted on a motherboard with a substrate turned upside down, and a method of manufacturing the same, wherein: has a structure in which the underfill material is easily impregnated.

Means for solving the problems

The present invention provides an electronic component, including: a substrate; a functional layer formed on the substrate and formed by alternately laminating a plurality of conductor layers and a plurality of insulating layers; and a plurality of terminal electrodes provided on the uppermost insulating layer among the plurality of insulating layers, wherein the uppermost insulating layer has a substantially rectangular planar shape and has a protruding portion protruding in a planar direction from at least one side in a plan view.

According to the present invention, if the underfill material is supplied after the motherboard is loaded in the upside-down reverse manner, the underfill material enters the gap between the motherboard and the electronic component by the surface tension starting from the protruding portion. Therefore, even when the gap between the motherboard and the electronic component is narrow, the underfill material can be easily impregnated.

In the present invention, the protruding portion may overlap with the substrate in a plan view. Thus, the planar size of the electronic component is not increased by the protruding portion.

In the present invention, the protruding portion may be located at a substantially central portion of one side. This makes it easy for the underfill material that has entered from the protruding portion to diffuse throughout the gap between the motherboard and the electronic component. In this case, the plurality of terminal electrodes include a 1 st terminal electrode and a 2 nd terminal electrode, and have a 1 st segment and a 2 nd segment adjacent to the 1 st and 2 nd terminal electrodes, respectively, on one side of the uppermost insulating layer, and the protrusion is located between the 1 st segment and the 2 nd segment. This makes it possible to avoid the terminal electrode from being immersed in the underfill material.

The present invention provides a method for manufacturing an electronic component, comprising: a first step of alternately laminating a plurality of conductor layers and a plurality of insulating layers on an aggregate substrate; and a 2 nd step of cutting the collective substrate to singulate a plurality of electronic components including 1 st and 2 nd electronic components adjacent to each other, wherein an insulating layer located on an uppermost layer among the plurality of insulating layers includes a 1 st portion belonging to the 1 st electronic component, a 2 nd portion belonging to the 2 nd electronic component, and a bridging structure portion locally connecting the 1 st portion and the 2 nd portion, the 1 st step includes a step of forming a seed layer on an entire surface after forming the insulating layer located on the uppermost layer, and forming a plurality of terminal electrodes by performing electrolytic plating in which the seed layer serves as a power supply body, and the 2 nd step separates the bridging structure portion.

According to the present invention, since the insulating layer located on the uppermost layer has the bridge structure portion, the seed layer is not electrically disconnected even if peeling occurs due to shrinkage of the insulating layer. Therefore, electrolytic plating using the seed layer as a power feeder can be reliably performed. In addition, when the bridge structure portion is cut in the 2 nd step, since the protruding portion is formed in the insulating layer located on the uppermost layer, the penetration of the underfill material can be promoted.

ADVANTAGEOUS EFFECTS OF INVENTION

Thus, according to the present invention, an electronic component having a structure in which an underfill material is easily impregnated and a method for manufacturing the same can be provided.

Drawings

Fig. 1 is a schematic plan view for explaining the structure of an electronic component 1 according to an embodiment of the present invention.

Fig. 2 is a general sectional view taken along line a-a of fig. 1.

Fig. 3 is a schematic plan view showing the pattern shapes of the conductor layers M1 and MM.

Fig. 4 is a schematic plan view showing the pattern shape of the conductor layer M2.

Fig. 5 is a schematic plan view showing the pattern shape of the conductor layer M3.

Fig. 6 is an equivalent circuit diagram of the electronic component 1.

Fig. 7 is a schematic cross-sectional view showing a state in which the electronic component 1 is mounted on the motherboard 50.

Fig. 8 is a schematic plan view for explaining the flow of the underfill material UF.

Fig. 9 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 10 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 11 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 12 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 13 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 14 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 15 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 16 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 17 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 18 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 19 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 20 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 21 is a process diagram for explaining a method of manufacturing the electronic component 1.

Fig. 22 is a plan view showing a state after the conductor layer M1 is formed.

Fig. 23 is a plan view showing a state after the conductor layer MM is formed.

Fig. 24 is a plan view showing a state after forming via holes 21b to 28b in insulating layer 6.

Fig. 25 is a plan view showing a state after the conductor layer M2 is formed.

Fig. 26 is a plan view showing a state after forming through holes 31b to 36b in insulating layer 7.

Fig. 27 is a plan view showing a state after the conductor layer M3 is formed.

Fig. 28 is a plan view showing a state after forming through holes 41b to 48b in insulating layer 8.

Fig. 29 is a schematic sectional view taken along line B-B shown in fig. 28.

Fig. 30 is a schematic plan view for explaining the structure of an electronic component 1A according to modification 1.

Fig. 31 is a schematic plan view for explaining the structure of an electronic component 1B according to modification 2.

Description of the reference numerals

1. 1A, 1B electronic component

1a finally becoming the area of an electronic component

2 substrate (Integrated substrate)

3 planarization layer

4 dielectric film

5 passivation film

6 to 8 insulating layers

10 functional layers

11 to 18, 21 to 27, 31 to 36 conductor patterns

19. 29, 39 sacrificial patterns

21a to 27a, 31a to 34a, 36a, 41a to 44a via hole conductors

21b to 28b, 31b to 36b, 41b to 48b

21c, 22c, 25c openings

41-44 terminal electrode

50 mother board

51. 52 pad pattern

53 solder

81-84 protrusion

91-94 bridge structure part

Sides E1-E4

M1, MM, M2, M3 and M4 conductor layers

P coating

R1, R2 resist layer

S seed layer

Interval S1, S2

UF underfill material (underfil)

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic plan view of a structure of an electronic component 1 used in one embodiment of the present invention. Fig. 2 is a schematic sectional view taken along line a-a of fig. 1.

The electronic component 1 of the present embodiment is an LC filter, and includes a substrate 2, and conductor layers M1, MM, M2, M3, M4, and insulating layers 6 to 8 formed on a main surface of the substrate 2, as shown in fig. 1 and 2. The insulating layers 6 to 8 are made of a resin material having high insulating properties. The conductive layers M1 to M4 and the insulating layers 6 to 8 are alternately stacked, and a portion composed of the conductive layer M1 to the insulating layer 8 constitutes the functional layer 10 functioning as an LC filter. Fig. 3 shows the pattern shapes of the conductor layers M1 and MM, fig. 4 shows the pattern shape of the conductor layer M2, fig. 5 shows the pattern shape of the conductor layer M3, and fig. 1 shows the pattern shape of the conductor layer M4.

The material of the substrate 2 is not particularly limited as long as it is chemically stable, thermally stable, generates little stress, and can maintain the smoothness of the surface, but silicon single crystal, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO single crystal, or the like can be used₃Single crystals, surface silica, glass, quartz, ferrite, and the like. The surface of the substrate 2 is covered by a planarization layer 3. As the planarization layer 3, alumina, silicon oxide, or the like can be used.

The conductor layer M1 is the conductor layer located at the lowermost layer, and includes conductor patterns 11 to 17, as shown in FIG. 3. The conductor patterns 11 to 14 are terminal electrode patterns, the conductor pattern 15 is a lower electrode of a capacitor, and the conductor pattern 16 is an inductor pattern. One ends of the conductor pattern 15 constituting the lower electrode and the conductor pattern 16 constituting the inductor pattern are connected to the conductor pattern 11 via a conductor pattern 17. These conductor patterns 11 to 17 are each composed of a thin seed layer S in contact with the planarization layer 3 and a plating layer P provided on the seed layer S and having a larger film thickness than the seed layer S. Similarly, the conductor patterns located in the other conductor layers MM, M2, M3, and M4 are composed of a laminate of the seed layer S and the plating layer P. Of the conductive patterns 11 to 17, at least the upper surface and the side surface of the conductive pattern 15 constituting the lower electrode of the capacitor are covered with a dielectric film (capacitor insulating film) 4.

A conductive pattern 18 is formed on the upper surface of the conductive pattern 15 via the dielectric film 4. The conductor pattern 18 belongs to the conductor layer MM located between the conductor layer M1 and the conductor layer M2, and constitutes an upper electrode of the capacitor. Thus, a capacitor is formed in which the conductive pattern 15 is a lower electrode and the conductive pattern 18 is an upper electrode. The conductor layer M1 and the conductor layer MM are covered with the insulating layer 6 via the passivation film 5. In the present embodiment, the dielectric film 4 and the passivation film 5 are both made of an inorganic insulating material. The inorganic insulating material constituting the dielectric film 4 and the inorganic insulating material constituting the passivation film 5 may be the same material or different materials.

The conductor layer M2 is a second conductor layer provided on the surface of the insulating layer 6, and includes conductor patterns 21 to 27 as shown in fig. 4. The conductor patterns 21 to 24 are terminal electrode patterns, the conductor pattern 25 is a lead electrode of a capacitor, and the conductor pattern 26 is an inductor pattern. The conductor pattern 26 has the same pattern shape as the conductor pattern 16 and is formed at the same planar position. Therefore, the conductor patterns 16 and 26 overlap in a plan view. The conductor pattern 25 is connected to the conductor pattern 18 as an upper electrode and to the conductor pattern 22 via a via conductor 25a provided to penetrate the insulating layer 6. One end of the conductor pattern 26 constituting the inductor pattern is connected to the conductor pattern 21 via the conductor pattern 27. Further, one end of the conductor pattern 26 is connected to one end of the conductor pattern 16 via a via conductor 26a provided through the insulating layer 6, and the other end of the conductor pattern 26 is connected to the other end of the conductor pattern 16 via a via conductor 27a provided through the insulating layer 6. The conductor patterns 21 to 24 are connected to the conductor patterns 11 to 14 through via-hole conductors 21a to 24a provided to penetrate the insulating layer 6. The conductor layer M2 is covered with an insulating layer 7.

The conductor layer M3 is a third conductor layer provided on the surface of the insulating layer 7, and includes conductor patterns 31 to 36 as shown in fig. 5. The conductor patterns 31 to 34 are terminal electrode patterns, the conductor pattern 35 is an extraction electrode of an inductor, and the conductor pattern 36 is an inductor pattern. One end of a conductor pattern 36 constituting the inductor pattern is connected to the other end of the conductor pattern 26 via a via conductor 36a provided to penetrate the insulating layer 7, and the other end of the conductor pattern 36 is connected to the conductor patterns 33 and 34 via a conductor pattern 35. Further, the conductor patterns 31 to 34 are connected to the conductor patterns 21 to 24 through via-hole conductors 31a to 34a provided to penetrate the insulating layer 7. The conductor layer M3 is covered with the insulating layer 8 located on the uppermost layer.

The conductor layer M4 is a fourth conductor layer provided on the surface of the insulating layer 8, and includes terminal electrodes 41 to 44 as shown in fig. 1. The terminal electrodes 41 to 44 are connected to the conductor patterns 31 to 34 through via-hole conductors 41a to 44a provided to penetrate the insulating layer 8.

Fig. 6 is an equivalent circuit diagram of electronic component 1 of the present embodiment.

As shown in fig. 6, the electronic component 1 of the present embodiment has a circuit configuration in which a capacitor C is connected between the terminal electrode 41 and the terminal electrode 42, and an inductor L is connected between the terminal electrode 41 and the terminal electrodes 43 and 44. The capacitor C is composed of a conductor pattern 15 as a lower electrode, a conductor pattern 18 as an upper electrode, and a dielectric film 4 located between the conductor patterns 15 and 18. On the other hand, the inductor L has a circuit configuration in which parallel coils formed of the conductor patterns 16 and 26 and a coil formed of the conductor pattern 36 are connected in series.

As shown in fig. 2, in the present embodiment, the conductor thickness H1 of the conductor layer M1 is thinner than the conductor thickness H2 of the conductor layer M2. If the conductor thickness H1 of the conductor layer M1 is reduced, the step between the dielectric film 4 and the passivation film 5 is reduced, so that the stress is relaxed, and the effect of making the interface between the dielectric film 4 and the conductor layer M1 difficult to peel off is obtained. On the other hand, if the conductor thickness H1 of the conductor layer M1 is made thin, the resistance value of the conductor layer M1 becomes high, and therefore, if the conductor pattern 16 belonging to the conductor layer M1 is simply used as an inductor pattern, the characteristics of the LC filter may be degraded. In view of this, in the electronic component 1 of the present embodiment, the conductor pattern 16 belonging to the conductor layer M1 and the conductor pattern 26 belonging to the conductor layer M2 are connected in parallel, thereby reducing the resistance value. This prevents the separation of the interface between the dielectric film 4 and the conductor layer M1, and reduces the resistance value of the inductor L.

The conductor thickness of the conductor layers M3 and M4 is not particularly limited, but is preferably set to be about the same as the conductor thickness H2 of the conductor layer M2.

As shown in fig. 1, the planar shape of the insulating layer 8 located on the uppermost layer is substantially rectangular. The insulating layer 8 has protrusions 81-84 protruding in the planar direction from the respective sides E1-E4 in plan view. Specifically, when the sides extending in the x direction among the respective sides of the insulating layer 8 in a plan view are E1 and E2, and the sides extending in the y direction are E3 and E4, the protruding portions 81 and 82 protruding in the y direction are present in the substantially central portions of the sides E1 and E2, respectively, and the protruding portions 83 and 84 protruding in the x direction are present in the substantially central portions of the sides E3 and E4, respectively. The x-direction position of the protruding portion 81 does not overlap with the terminal electrodes 41 and 42, the x-direction position of the protruding portion 82 does not overlap with the terminal electrodes 43 and 44, the y-direction position of the protruding portion 83 does not overlap with the terminal electrodes 41 and 43, and the y-direction position of the protruding portion 84 does not overlap with the terminal electrodes 42 and 44. That is, when the sections adjacent to the terminal electrodes 41 and 42 (the sections overlapping with the terminal electrodes 41 and 42 in the y direction) in the side E1 are S1 and S2, respectively, the protrusion 81 is located between the section S1 and the section S2. The same applies to the other protrusions 82 to 84.

The projecting amount of the projecting parts 81-84 is suppressed to be not more than the range of the substrate 2. That is, the projections 81 to 84 overlap the substrate 2 in a plan view, and do not project beyond the substrate 2. Therefore, the planar size of the electronic component 1 is not increased by the presence of the protruding portions 81 to 84. The edges of the projections 81 to 84 may be flush with the side surfaces of the substrate 2.

Fig. 7 is a schematic cross-sectional view showing a state in which the electronic component 1 of the present embodiment is mounted on the motherboard 50.

In the cross section shown in fig. 7, land patterns 51 and 52 are formed on a motherboard 50, and an electronic component 1 is mounted so that terminal electrodes 41 and 42 are connected to the land patterns 51 and 52, respectively, via solder 53. In addition, for the purpose of improving reliability, underfill UF is filled in the gap between motherboard 50 and electronic component 1. The underfill UF is filled by supplying the low-viscosity underfill UF to the surface of the motherboard 50 after the electronic component 1 is mounted on the motherboard 50. In this case, if the gap between the motherboard 50 and the electronic component 1 is narrow, the underfill material UF is difficult to penetrate, but in the present embodiment, since the protrusions 81 to 84 are provided in the insulating layer 8 located at the lowermost layer when mounted, the underfill material UF easily penetrates into the gap between the motherboard 50 and the electronic component 1 due to surface tension from the protrusions 81 to 84 as shown by arrows in fig. 8, which is a schematic plan view.

However, in the present embodiment, since the protrusions 81 to 84 are provided at substantially central portions of the sides E1 to E4 of the insulating layer 8, the underfill UF enters from 4 directions. Since the projections 81 to 84 are provided at positions not interfering with the terminal electrodes 41 to 44, the underfill UF that has entered from the projections 81 to 84 is likely to diffuse in the entire gap between the motherboard 50 and the electronic component 1.

Next, a method for manufacturing the electronic component 1 of the present embodiment will be described.

Fig. 9 to 21 are process diagrams for explaining a method of manufacturing the electronic component 1 according to the present embodiment. In the manufacturing process of the electronic component 1, a plurality of electronic components 1 are obtained using a collective substrate, but the manufacturing process shown in fig. 9 to 21 focuses on one electronic component 1.

First, as shown in fig. 9, a planarization layer 3 is formed on a substrate (collective substrate in this case) 2 by sputtering or the like, and the surface thereof is smoothed by a mirror surface treatment such as polishing or CMP. Then, a seed layer S is formed on the surface of the planarization layer 3 by sputtering or the like. Next, as shown in fig. 10, after a resist layer R1 was spin-coated on the seed layer S, the resist layer R1 was patterned so that the seed layer S in the region where the conductor layer M1 was to be formed was exposed. In this state, electrolytic plating using the seed layer S as a power feeder is performed, whereby a plating layer P is formed on the seed layer S as shown in fig. 11. The stacked body of the seed layer S and the plating layer P constitutes the conductor layer M1. In the cross section shown in fig. 11, the conductor layer M1 includes conductor patterns 11, 12, 15, and 17. Further, as shown in fig. 12, if the seed layer S exposed on the surface is removed after the resist layer R1 is removed, the conductor layer M1 is completed. The seed layer S can be removed by etching or ion milling.

Fig. 22 is a plan view showing a state after the conductor layer M1 is formed. The region surrounded by the broken line 1a in fig. 22 is a region which is finally one electronic component 1. The region outside the dotted line 1a is a cutting margin when singulation is performed by cutting. As shown in fig. 22, a sacrificial pattern 19 as a part of the conductor layer M1 is formed in a portion to be a cutting margin and a region slightly inside the broken line 1 a.

Next, as shown in fig. 13, dielectric film 4 is formed on the entire surface including the upper surface and the side surfaces of conductor layer M1. As the dielectric film 4, for example, a known ferroelectric material other than a common dielectric material such as silicon nitride (SiNx) and silicon oxide (SiOx) can be used. As a film forming method of the dielectric film 4, a sputtering method, a plasma CVD method, an MOCVD method, a sol-gel method, an electron beam evaporation method, or the like can be used.

Next, as shown in fig. 14, a conductor pattern 18 is formed on the upper surface of the conductor pattern 15 via the dielectric film 4 by using the same method as the method for forming the conductor layer M1. The conductor pattern 18 is also composed of a laminate of the seed layer S and the plating layer P. This completes the conductor layer MM, and a capacitor is formed with the conductor pattern 15 as a lower electrode and the conductor pattern 18 as an upper electrode. Fig. 23 is a plan view showing a state after the conductor layer MM is formed.

Next, as shown in fig. 15, after the passivation film 5 covering the conductor layers M1 and MM is formed, the insulating layer 6 is formed. Next, as shown in fig. 16, the insulating layer 6 is patterned to form via holes 21b to 28b in the insulating layer 6. Fig. 24 is a plan view showing a state after forming via holes 21b to 28b in the insulating layer 6. Thereby, the passivation film 5 covering the conductor layer M1 or MM is exposed at the bottom of the through holes 21b to 28b, respectively.

Next, as shown in fig. 17, after a resist layer R2 is formed on the insulating layer 6, openings 21c, 22c, and 25c overlapping the through holes 21b, 22b, and 25b are formed in the resist layer R2, and ion milling or the like is performed in this state. Thereby, the passivation film 5 exposed in the opening 25c is removed, and the passivation film 5 and the dielectric film 4 exposed in the openings 21c and 22c are removed, so that the upper surfaces of the conductor layers M1 and MM are exposed. The other through holes 23b, 24b, 26b to 28b not shown in fig. 17 also form similar openings. Thereby, the sacrificial pattern 19 is exposed at the bottom of the via hole 28 b.

Next, after the resist layer R2 was removed, as shown in fig. 18, a conductor layer M2 was formed on the insulating layer 6 by the same method as the method for forming the conductor layer M1. Fig. 25 is a plan view showing a state after the conductor layer M2 is formed. As shown in fig. 25, a sacrificial pattern 29 which is a part of the conductor layer M2 is formed in a portion which becomes the dicing margin and a region slightly inside the broken line 1 a.

Next, as shown in fig. 19, after the insulating layer 7 covering the conductor layer M2 is formed, the insulating layer 7 is patterned to form the via holes 31b to 36b in the insulating layer 7. Fig. 26 is a plan view showing a state after forming through holes 31b to 36b in insulating layer 7. Thereby, the conductor layer M2 is exposed at the bottom of each of the through holes 31b to 36 b. The sacrificial pattern 29 is exposed at the bottom of the via hole 35 b.

Next, as shown in fig. 20, a conductor layer M3 was formed on the insulating layer 7 by the same method as the method for forming the conductor layers M1 and M2. Fig. 27 is a plan view showing a state after the conductor layer M3 is formed. As shown in fig. 27, a sacrificial pattern 39 as a part of the conductor layer M3 is formed in a part of the portion to be the dicing margin and a region slightly inside the broken line 1 a. Here, the sacrifice pattern 39 is provided so as to overlap a substantially central portion of a portion which becomes each side of the electronic component in a plan view.

Next, as shown in fig. 21, after the insulating layer 8 covering the conductor layer M3 is formed, the insulating layer 8 is patterned to form the via holes 41b to 48b in the insulating layer 8. Fig. 28 is a plan view showing a state after forming through holes 41b to 48b in insulating layer 8. Thus, the conductor patterns 31 to 34 are exposed at the bottoms of the through holes 41b to 44b, respectively, and the sacrificial patterns 29 and 39 are exposed at the bottoms of the through holes 45b to 48 b.

Fig. 29 is a schematic sectional view taken along line B-B shown in fig. 28.

As shown in fig. 28 and 29, the insulating layer 8 located on the uppermost layer has no openings over the entire outer periphery of each electronic component, and has bridge structure portions 91 to 94 that partially connect adjacent electronic components. Specifically, the insulating layer 8 belonging to the electronic component located at the center in fig. 28 is connected to the insulating layer 8 belonging to the electronic component located on the upper side at the bridge structure portion 91, connected to the insulating layer 8 belonging to the electronic component located on the lower side at the bridge structure portion 92, connected to the insulating layer 8 belonging to the electronic component located on the left side at the bridge structure portion 93, and connected to the insulating layer 8 belonging to the electronic component located on the right side at the bridge structure portion 94.

Next, as shown in fig. 2, a conductor layer M4 was formed on the insulating layer 8 by the same method as the method for forming the conductor layers M1 to M3. In the step of forming the conductor layer M4, after the insulating layer 8 is formed, a seed layer S is formed on the entire surface, and electrolytic plating is performed using the seed layer S as a power supply body, thereby forming the terminal electrodes 41 to 44. Since shrinkage occurs in the curing step after the formation of the through holes 41b to 48b in the insulating layer 8, there is a possibility that peeling may occur at the interface between the insulating layer 8 and the conductor layer M3 at the stage of forming the seed layer S. If peeling occurs at the interface between the insulating layer 8 and the conductor layer M3, the seed layer S may be broken at the peeled portion, and a part of the seed layer S may be electrically broken due to the peeled state.

However, in the present embodiment, since the insulating layer 8 has the bridge structures 91 to 94, even if partial peeling occurs at the interface between the insulating layer 8 and the conductor layer M3, electrical connection is ensured by the seed layer S formed on the surfaces of the bridge structures 91 to 94. Therefore, the terminal electrodes 41 to 44 can be reliably formed by electrolytic plating using the seed layer S as a power supply.

Then, the electronic component 1 of the present embodiment is completed by cutting the substrate 2 so as to divide the bridge structures 91 to 94 into pieces after removing the sacrificial patterns 19, 29, and 39 with an etchant such as acid in a state where the terminal electrodes 41 to 44 are covered with a resist layer not shown. If the bridge structures 91 to 94 are divided by cutting, the protrusions 81 to 84 shown in FIG. 1 are formed on the insulating layer 8. The protrusions 81-84 are part of the bridging structures 91-94, respectively.

As described above, in the manufacturing process of the electronic component 1 of the present embodiment, when the through-hole is formed in the insulating layer 8 located on the uppermost layer, the insulating layer 8 is not separated into the electronic components by the through-hole, and the portions belonging to the adjacent electronic components are connected to each other by the bridge structures 91 to 94, so that the electrolytic plating failure due to the division of the seed layer S can be prevented.

Fig. 30 is a schematic plan view for explaining the structure of an electronic component 1A according to modification 1.

The electronic component 1A of modification 1 is different from the electronic component 1 of the above embodiment in that the protruding portions 81 to 84 have a tapered shape in a plan view. Since other basic configurations are the same as those of the electronic component 1 of the above embodiment, the same elements are denoted by the same reference numerals, and redundant description thereof is omitted. As exemplified in the electronic component 1A of modification 1, the planar shape of the protruding portions 81 to 84 is not particularly limited.

Fig. 31 is a schematic plan view for explaining the structure of an electronic component 1B according to modification 2.

The electronic component 1B of modification 2 is different from the electronic component 1 of the above embodiment in that a plurality of protrusions 81 to 84 are provided. Since other basic configurations are the same as those of the electronic component 1 of the above embodiment, the same elements are denoted by the same reference numerals, and redundant description thereof is omitted. In modification 2, the number of the projections 81 and 82 on the long sides E1 and E2 is 3, and the number of the projections 83 and 84 on the short sides E3 and E4 is 2. As exemplified in the electronic component 1B of modification 2, the number of the protruding portions 81 to 84 is not limited.

While the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

For example, although the above embodiment has been described by taking as an example the case where the present invention is applied to an LC filter, the electronic component to be the object of the present invention is not limited to the LC filter, and may be applied to other types of electronic components.

In the above embodiment, the bridge structures 91 to 94 are provided in the insulating layer 8 located on the uppermost layer, but bridge structures may be provided not only in the insulating layer 8 but also in the other insulating layers 6 and 7.