阅读说明：本技术 用于电光集成磷化铟基相位调制器的改进构建块 (Improved building block for electro-optically integrated indium phosphide-based phase modulator ) 是由 拉斯特科·帕伊科维奇 埃尔温·安东纽斯·约瑟夫斯·玛丽亚·本特 斯特凡诺斯·安德烈乌 特奥多鲁 于 2020-02-07 设计创作，主要内容包括：一种光子集成电路PIC,其包括衬底上的多个半导体层,所述多个半导体层形成PIN或PN掺杂结构,所述PIC包括：波导,其被布置用于传导光波；光学元件,其连接到波导,其中所述光学元件在操作中处于反向偏置模式,并且其中光学元件包括被布置用于连接到电压源的接触层；其中波导包括靠近光学元件的导电触点,并且其中PIC还包括布置在光学元件和导电触点之间的至少一个隔离部分。本文还提出了此类PIC的对应操作方法。(A photonic integrated circuit, PIC, comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming a PIN or PN doped structure, the PIC comprising: a waveguide arranged to conduct light waves; an optical element connected to the waveguide, wherein the optical element is in a reverse bias mode in operation, and wherein the optical element comprises a contact layer arranged for connection to a voltage source; wherein the waveguide comprises a conductive contact proximate to the optical element, and wherein the PIC further comprises at least one isolated portion disposed between the optical element and the conductive contact. Corresponding methods of operation of such PICs are also presented herein.)

1. A photonic integrated circuit, PIC, (60) comprising a plurality of semiconductor layers (62, 63, 64, 65, 66, 67) on a substrate (68), the plurality of semiconductor layers (62, 63, 64, 65, 66, 67) forming a PIN or PN doped structure, the PIC (60) comprising:

-a waveguide (74) arranged for guiding light waves, the waveguide comprising a waveguide layer (65) being one of the plurality of semiconductor layers (62, 63, 64, 65, 66, 67);

-an optical element (10, 20, 30) comprising a waveguide layer (65) being one of the plurality of semiconductor layers (62, 63, 64, 65, 66, 67), the waveguide (74) and the waveguide layer (65) of the optical element (10, 20, 30) being connected to each other, wherein the optical element (10, 20, 30) is configured in operation in a reverse bias mode, and wherein the optical element (10, 20, 30) comprises a contact layer (61) arranged for connection to a voltage source; wherein the waveguide (74) comprises at least one electrically conductive contact (69) proximate to the optical element (10, 20, 30), and wherein the PIC (60) further comprises:

-at least one isolating portion (72) arranged between the contact layer (61) and the at least one electrically conductive contact (69).

2. The photonic integrated circuit of claim 1, wherein the at least one isolation portion is disposed between the optical element and the conductive contact.

3. The photonic integrated circuit according to any of the preceding claims, wherein the at least one electrically conductive contact is arranged on both sides of the optical element with respect to the direction of the light waves in the waveguide.

4. The photonic integrated circuit according to any of the preceding claims, wherein the at least one conductive contact extends substantially over the entire waveguide.

5. The photonic integrated circuit according to any of the preceding claims, wherein the at least one conductive contact is connected to an electrical ground.

6. The photonic integrated circuit of claim 5, wherein the PIC further comprises a ground hole arranged to allow contact between a conductive contact and the n-doped layer, wherein a distance between an edge of the ground hole and the waveguide is at least 10 μm, the distance being measured in a direction perpendicular to a direction of propagation of light in the waveguide layer.

7. The photonic integrated circuit of claim 6, wherein at least one dimension of a cross-section of the ground hole in a plane parallel to a direction of propagation of light in the waveguide layer is at least 20 μm.

8. The photonic integrated circuit according to any of the preceding claims, wherein the length of the conductive contact measured in the direction of propagation of light in the waveguide layer is at least 20 μ ι η.

9. The photonic integrated circuit according to any of the preceding claims, wherein the at least one conductive contact comprises any of titanium and/or gold and/or platinum.

10. The photonic integrated circuit according to any of the preceding claims, wherein the optical element is any of the following:

an electrorefractive modulator ERM, and

-a photodetector.

11. The photonic integrated circuit according to any of the preceding claims, comprising a plurality of conductive contacts, wherein the plurality of conductive contacts are interconnected by a metallic conductive layer.

12. A method of operating a photonic integrated circuit as claimed in any one of the preceding claims, wherein a reverse bias voltage is applied to the at least one conductive contact.

13. A method of operating the photonic integrated circuit of any one of claims 1 to 11, wherein the at least one conductive contact is connected to electrical ground.

Technical Field

The present disclosure relates generally to the field of photonic integrated circuits, and in particular to an apparatus having a reduced level of interference between different components of a photonic integrated circuit.

Background

A photonic integrated circuit PIC or integrated optical circuit is a device that integrates multiple photonic functions. It differs from electronic integrated circuits primarily in that PICs provide functionality for information signals applied at optical wavelengths in the visible or near infrared spectrum. Different components (such as low loss interconnection waveguides, power splitters, optical amplifiers, optical modulators, filters, lasers and detectors) form the PIC. In general, a PIC includes both active and passive components. The active components are for example semiconductor optical amplifiers SOA, electrorefractive modulators ERM and the passive components are for example waveguides.

Examples of PICs include monolithic tunable lasers, wide tunable lasers, externally modulated lasers and transmitters, integrated receivers. In such a PIC, parameters of the light (such as frequency and phase) are important, and information may be conveyed according to a change in one of these properties. Therefore, it is desirable to be able to finely control such parameters.

For example, the phase of the light is adjusted by using ERM. ERM changes phase by adjusting the refractive index of the material, which in turn can be controlled by influencing the electric field applied in the material. In normal practice, the electric field is precisely controlled by adjusting the bias voltage.

It has been tested that there appears to be cross talk between the active components, thereby introducing an additional electric field, which in turn affects the phase of the light passing through the active components. This is not preferable. In addition, such additional electric fields are also observed on passive elements (such as waveguides). As a result, the phase of the light passing through is changed more than expected.

The present inventors have identified a problem with a standard phase modulator, which is the ERM in a generic multi-project wafer MPW integration process when used in reverse bias. This problem has led to the discovery that similar problems with other components in the indium phosphide InP MPW process, not just the phase modulator, are also solved.

This problem is found during characterization of tunable lasers with filters based on three asymmetric mach-zehnder interferometers AMZI in series. This particular arrangement is implemented in the MPW operation of the smart photonics operation 17, SP17 on an n-type doped substrate and packaged in a Technobis standard package. The layout of the device is schematically depicted in fig. 1 and further elucidated with reference to fig. 1.

The device 1 has three AMZIs 10, 20, 30, each having two ERM11, 12; 21. 22; 31. 32, a first step of removing the first layer; its length is 2.118mm plus a so-called in-line ERM 40 to tune the cavity mode independently. All ERM had isolated sections 30 microns (μm) long on both ends. The ERM operates with a voltage that places the pin junction of the device under reverse bias.

We have found that there are two related problems in this circuit. The first problem is that there may be a large amount of electrical crosstalk between different ERM's. A second problem directly related to this is that the passive waveguide between the two ERM's is biased due to the bias of the surrounding ERM's and acts as a phase modulator. These problems become apparent in the results of the laser measurements presented herein. In this measurement, the long waveguide arm of the coarse-tuned (minimum path length difference) AMZI is reverse biased by a voltage Vset. Voltage levels of other unbiased ERM were measured using a Keithley source table. The chip is grounded at the bottom n-contact. The measurement results are presented in fig. 2. Presented is the voltage recorded on the ERM, which is the short arm of the coarse tuned AMZI in 51; at 52 is the long arm of the medium AMZI; in 53 is the long arm of the fine tune AMZI as a function of the voltage Vset.

Crosstalk to different ERM's is clearly visible. This means that the passive waveguide between the ERM and the MMI have a certain voltage on the p-doped layer. Therefore, they will also act as phase modulators. More data on the tuning of the AMZI is available, which also emphasizes the role of the passive waveguide.

The cause of the crosstalk is that the isolation part has a resistance of several mega ohms (M Ω) and the resistance of the reverse biased pin diode structure is similar or higher. The reverse bias current (in the dark) at-4 volts (V) is 80 to 100 nanoamperes (nA), which means a resistance of about 40M Ω. Note that as light passes through the ERM, it affects the current passing through the ERM, and thus its effective resistance. This will affect the crosstalk to the passive waveguide section and other ERM's.

Disclosure of Invention

In a first aspect of the present disclosure, there is provided a photonic integrated circuit, PIC, comprising a plurality of semiconductor layers on a substrate, the plurality of semiconductor layers forming a PIN or PN doped structure, the PIC comprising: a waveguide comprising a waveguide layer and arranged for guiding light waves, the waveguide layer being one of the plurality of semiconductor layers; an optical element comprising a waveguide layer, which is one of the plurality of semiconductor layers, the waveguide and the waveguide layer of the optical element being connected to each other, wherein the optical element is in a reverse bias mode in operation, and wherein the optical element comprises a contact layer arranged for connection to a voltage source;

wherein the waveguide comprises at least one conductive contact proximate to the optical element, and wherein the PIC further comprises at least one isolation portion disposed between the contact layer and the at least one conductive contact.

As understood in the art, a photonic integrated circuit PIC or an integrated optical circuit is a device that integrates multiple photonic functions. The PIC, in turn, may be composed of several active and/or passive components. PICs are typically formed by arranging several layers of semiconductor material on a substrate. These layers are doped to form a PIN or PN doped structure. An example of such a doping structure is presented in fig. 3b and described in detail in the corresponding section below.

It has been identified in the preceding section that the inventors have found that although the isolation section is contained in the elements of the PIC, there are adverse effects such as crosstalk occurring between components or passive components (such as waveguides) and thus additional phase modulation being introduced. The inventors have found that by providing an additional at least one electrically conductive contact close to the contact layer, the optical element can be effectively isolated from the influence of neighbouring optical elements.

According to one embodiment, at least one isolating section is arranged between the optical element and the electrically conductive contact.

For example, the isolation portion may ensure that multiple of the semiconductor layers of the optical element and the waveguide are isolated such that not all of the semiconductor layers of the optical element are directly connected to their respective corresponding semiconductor layers of the waveguide.

According to one embodiment, the at least one electrically conductive contact is arranged on both sides of the optical element with respect to the direction of light in the waveguide. This is a preferred arrangement to ensure improved isolation of the optical elements in question.

According to one embodiment, the at least one electrically conductive contact extends over substantially the entire waveguide. The inventors believe that it is advantageous to ensure effective isolation of the waveguides by placing at least one electrically conductive contact over substantially the whole of the waveguide. In this way, the waveguide remains passive and is not biased by an adjacent electric field.

In an exemplary embodiment, at least one of the conductive contacts is connected to an electrical ground. This has the advantage that the isolation becomes more efficient. The electrical grounding may be achieved by means of a grounding hole arranged to allow contact between the conductive contact and the n-doped layer, wherein the distance between the edge of the grounding hole and the waveguide is at least 10 μm, wherein said distance is measured in a direction perpendicular to the direction of propagation of light in the waveguide. In a preferred embodiment, it may be advantageous to maintain a certain voltage on the metal contacts.

As mentioned above, the length is measured in a direction perpendicular to the propagation direction of the light. The value of 10 μm is chosen such that any bias applied to the conductive contact does not affect the propagation of light in the waveguide. Current technical limitations dictate that such distances be currently at least 10 μm. It is understood by the person skilled in the art that if the technical improvements allow such a reduction of the distance, the distance may be further reduced in the future. The determining factor is that the distance should be chosen such that the bias applied to the conductive contacts does not affect the propagation of light in a manner that is detrimental to the function of the device.

Preferably, at least one dimension of a cross-section of the ground hole in a plane parallel to the direction of propagation of light in the waveguide is at least 20 μm. This limitation is also a result of the currently used technology. Future technologies may allow smaller size ground holes.

According to one embodiment, the length of the conductive contact, measured in the direction of propagation of the light, is at least 20 μm. The inventors believe that in order to achieve isolation in a more efficient manner, it is necessary to ensure that the conductive contacts extend at least 20 μm, and more preferably at least 50 μm.

According to any embodiment, the conductive contact comprises any of titanium and/or gold and/or platinum. The inventors have recognized that these are the metals typically used during the fabrication of such PICs. Those skilled in the art will also recognize other metals or materials having suitable conductivity that may be employed for the purposes set forth in this disclosure.

According to the present disclosure, the optical element is any one of:

an electrorefractive modulator ERM, and

-a photodetector.

The inventors consider that both elements are most susceptible to the surrounding electric field and that it is advantageous to ensure isolation of both elements. For example, ERM modulates the phase of light by adjusting the refractive index of the material. Thereby adjusting the refractive index by changing the electric field. Thus, if the ERM is not effectively isolated, an undesirable or unexpected phase output is observed.

According to one embodiment, the PIC includes a plurality of conductive contacts, wherein the plurality of conductive contacts are connected to each other by a metal conductive layer. In such embodiments, all of the conductors proximate to different optical elements are connected to each other. This may be advantageous because only one electrical ground may be required.

In a second aspect of the invention, there is provided a method of operating a photonic integrated device according to the present disclosure as described above, wherein a reverse bias voltage is applied to the conductive contacts. The inventors believe it is advantageous to connect the conductive contacts to a voltage source and apply a reverse bias voltage thereto. This has the effect that it reduces propagation losses and stabilizes the optical path length to a higher degree than in the present case. This is particularly useful when an applied reverse bias is applied to a conductive contact on a passive component, such as a waveguide.

In another embodiment of the second aspect of the present disclosure, a method of operating a photonic integrated device according to the present disclosure as described above is presented, wherein the conductive contact is connected to an electrical ground. In addition to connecting the contacts to a reverse bias, the conductive contacts may also be grounded. The invention may be understood in more detail with reference to the accompanying drawings and the description thereof.

Drawings

Fig. 1 shows a schematic layout of a tunable laser commonly used in photonic integrated circuits PIC.

FIG. 2 shows the voltage levels measured across different electro-refractive modulators ERM as a function of the voltage applied to the ERM in the long arm of the coarse-tuned AMZI.

Fig. 3a shows a cross section of a device according to the present disclosure.

Fig. 3b shows the different layers of the device according to the present disclosure.

Fig. 3c shows a cross section of a device according to the present disclosure.

Fig. 4 shows a cross-section of a grounded waveguide section according to the present disclosure.

Figure 5 shows a three-dimensional sketch of a waveguide ridge with two isolated sections, a ground section and an opening to the substrate layer.

Detailed Description

Fig. 1 shows a schematic layout of a tunable laser commonly used in photonic integrated circuits PIC. The device 1 has three AMZIs 10, 20, 30, each having two ERM11, 12; 21. 22; 31. 32, a first step of removing the first layer; its length is 2.118mm plus a so-called in-line ERM 40 to tune the cavity mode independently. All ERM had a 30 μm long spacer at both ends. The ERM operates with a voltage that places the pin junction of the device under reverse bias. The layout also includes a semiconductor optical amplifier SOA 41.

Fig. 2 shows the voltage levels measured across the different electro-refractive modulators ERM as a function of the voltage applied to the ERM in the long arm of the coarse tuning AMZI at 50. Presented is the voltage recorded on the ERM, which is the short arm of the coarse tuned AMZI in 51; at 52 is the long arm of the medium AMZI; and in 53 is the long arm of the fine tuning AMZI. At 54, the measured voltage on the fine tuning AMZI is presented when both ERM of the cavity ERM and the medium tuning AMZI are grounded. This clearly shows that by effectively grounding an optical element, interference with other adjacent optical elements can be effectively reduced. The latter observation indicates a possible solution and improvement of the ERM building block. This is depicted in fig. 3.

Figure 3a illustrates a cross-section of a photonic integrated circuit according to the present disclosure. There will be isolated portions 72 on both sides next to ERM11 and there will be another short ERM portion next to isolated portion 72 that will be connected to ground 71. The waveguide 74 comprises a waveguide layer 65 and is arranged for guiding light waves. According to the present disclosure, waveguide 74 also includes an electrically conductive contact 69 that allows connection to a voltage source or electrical ground.

The length of the isolated portion determines to a large extent the dark current of the ERM. A typical length of the isolation portion 72 is currently 50 μm. This length stems from current design rules for intelligent photonics processes. However, if the etch depth of this portion (down to about intermediate layer III-1) is similar and if the application allows to increase the dark current on the ERM, the length can in principle be shortened to about 20 μm. The 20 μm limitation stems from the manufacturing process of the currently used metallization process (lift-off process).

The length of the ground portion will also be 50 μm, determined by current design rules. It may be shorter. It is estimated that the current to be flowed is at most of the order of microamperes. Therefore, even a 20 μm long ground contact (a practical limitation of current technology) is not expected to have excessive resistance. For the etch depth, it is important that the highly doped layer III-2 is completely etched away. It is possible that the depth of the etch in the waveguide for isolation is small, but the current level from the ERM to the ground contact will start to rise. Whether this can be tolerated depends on the application of the circuit and the electronic device. The metallization for the ground contact may be the same as the metallization for the phase modulator. For example, the contacts are made of any of titanium/platinum/gold (Ti/Pt/Au), the contacts having a thickness of 300 nanometers (nm) of gold deposited by evaporation.

It should be noted that photonic integrated devices on InP are described here, but in principle other integration schemes and other semiconductor systems using ridge waveguide-like technology will have similar problems. However, we are not aware of other material systems commercially available for this purpose.

In current smart photonics integration schemes, the extra ground contact 71 as in fig. 3a is contacted using metal wiring on the chip surface. This will result in a large number of metal connections on the chip. The different layers are further elucidated with the aid of fig. 3 b.

Fig. 3b shows the different layers of the device according to the present disclosure. Fig. 3b and the corresponding description are to be understood as examples. The features of the present disclosure are not limited to the precise values presented herein. Layer III-3, labeled 61, is a p-type doped contact layer having a high doping concentration of about 1.5E 19. A typical material used may be p-type doped InGaAs. Layer 61 is 300nm thick. Layer III-2, designated 62, is also p-type doped, but has about per cubic centimeter (cm)^-3) Lower doping concentration of 1E 18. Layer 62 is made of InP and has a thickness of 1000 nm.

Layer III-1, labeled 63, is a p-doped layer made of InP, which is about 300nm thick. The layer has a thickness of about 1E17 cm^-3Lower doping concentration. Layer II-2, designated 64, is an n-doped layer made of InP, which is about 200nm thick. Doping concentration of about 1E16 cm^-3In (1). Layer II-1, designated 65, is an n-Q1.25 waveguide layer. The waveguide layer 65 has about 1E16 cm^-3And is 500nm thick.

Layers I-2 and I-1, labeled 66 and 67, respectively, are both n-doped and have 1E17 cm, respectively^-3And 1E18 cm^-3Is doped toAnd (4) degree. They are all made of InP and each have a thickness of 500 nm. Layer 68 is the substrate on which all subsequent layers are assembled. It is also known as I-0 and is typically doped to a concentration of 1E18 cm^-3To 4E18 cm^-3Is doped with InP. As previously mentioned, these values are exemplary only and not limiting.

Fig. 3c shows a cross section of a device according to the present disclosure. There are a number of issues that need to be considered. Isolation in the vertical direction of the waveguide may need to be considered. The trench next to the passive waveguide is 20 μm wide as shown in fig. 3 c. The etch is deeper than the isolation etch but the distance is typically three to five times, perhaps more or less.

Fig. 4 shows a cross-section of a grounded waveguide section according to the present disclosure at 100. It is more common to provide contacts on the phase modulator. It is also applicable to other reverse biased components such as amplifiers used in detectors and in passive components. Another point is that it may be advisable to contact all passive components and hold them at a reverse bias voltage of about 3 to 4 volts. There are many reasons why this is desirable. Having contacts 102 on all passive devices solves the electrical isolation problem with much fewer required contacts (without changing the technology). The contact design of the passive components may differ slightly from that of fig. 4.

The cross-section of the waveguide will be similar to that in fig. 4. If one wants to contact a passive device such as a multimode interference coupler, the waveguide section will become significantly wider (e.g. 8 μm instead of 2 μm). Metallization of such wider structures may cause problems in manufacturing. The application of voltage also reduces the free carrier concentration in the waveguide, thereby reducing the propagation loss up to 0.5dB per centimeter. It also clears free carriers generated in the passive waveguide from light passing through the waveguide (which can lead to increased absorption). The maximum power capacity of the passive waveguide may also increase, but this requires investigation. A third advantage is that the light induced carriers generate phase noise on the optical signal. This can be a problem in very narrow linewidth CW lasers and certainly will work in mode-locked lasers. Due to thermal effects, the free carrier concentration can change over time, and the built-in potential of the PIN structure can cause the waveguide to forward bias itself (e.g., a solar cell) in a manner that is difficult to predict. This light-generated current can enter anywhere in the p-doped layer and flow to the less intense waveguide portion. The free carrier effect in passive waveguides is currently being investigated.

Fig. 5 shows a three-dimensional sketch 110 of a waveguide ridge with two isolated sections 112, a ground section 113 and an opening 114 to a substrate layer 111. One possible way to avoid this is to make local contact to the n-doped layer in the substrate, as schematically depicted in fig. 4. This would require changes to existing processing schemes. Holes must be etched to the highly doped layer I-0 beside the waveguide where contact is made to the waveguide.

Metallization schemes such as the currently used Ti-Pt-Au layer system (typical thicknesses of 60-75-500nm, respectively) and contact anneal may be used as it will provide good ohmic contact on n-doped InP and p-doped InGaAs. The dimension 116 of the opening 114 towards layer I-0 may be as long as the ground contact and it is estimated that it will require a minimum of 20 μm wide. In fig. 5, a 2 μm wide ridge waveguide having two 20 μm isolated sections with a 20 μm long ground section in between and an opening to layer I-0 before planarization and metallization are applied is drawn to scale to show the structure. The opening 114 is 10 μm away 115 from the waveguide so as not to interfere with the propagation of light in the waveguide.

Since the current level is expected to be limited to 1 μ a or less, the resistance value of the contact may be relatively high (e.g., several hundred Ω). The depth of the etched hole may be the same as the depth of the deep etched ridge waveguide, in which case the metal will be in contact with the lower doped InP layer. This requires more research and experimentation.

In semi-insulating substrate technology, grounding of the p-side of the waveguide will be easier to achieve. In such a solution, where a top n-contact layer is already available, this can be used to connect the top p-contact of the grounded waveguide part.

These combinations of two isolated sections and one grounded section may also be used with other reverse bias components. A specific example is a photodetector where it will prevent leakage currents and dark current levels to other detectors or bias components and dark currents due to photo-generated currents in other passive waveguide components connected to the photodetector.

There is a need to address the electrical isolation of phase modulator building blocks in intelligent photonics platforms. A possible solution is to add a ground contact near the phase modulators separated by an isolating section. The ground contact can in principle be realized by forming the contact locally on the n-side of the chip. It is controversial to have all passive components touching and held at a ground voltage connected to the n-side, or a reverse bias voltage of a few volts, to reduce propagation losses and possibly stabilize the optical path length to a higher degree than in the present case.

In general, the present invention includes the use of ground contacts and isolation portions to prevent cross-talk between any components (including active and passive) in a smart photonics platform. The application of an electro-optical phase modulator is only one example of an active component.