阅读说明：本技术 一种用于控制大功率变流器输出电压的shepwm控制系统及方法 (SHEPWM control system and method for controlling output voltage of high-power converter ) 是由 张持 龙云波 徐永海 张曦 于 2021-01-20 设计创作，主要内容包括：本发明公开了一种用于控制大功率变流器输出电压的SHEPWM控制系统及方法,所述控制系统包括一个过零比较器、一个四倍频电路、一个触发器、一个DSP系统,所述控制方法首先输入50Hz工频的电压信号得到50Hz方波信号及200Hz同步信号,接着计算DSP控制系统需要输出的开关角度值,然后设计输出开关控制信号所需中断流程,进行多次重复输出完整的周期波形。本发明避免了周期内计算的累计误差,改善输出波形周期内对称性,降低了输出电压的输出谐波含量,提高了输出波形的质量。(The invention discloses a SHEPWM control system and a method for controlling the output voltage of a high-power converter, wherein the control system comprises a zero-crossing comparator, a quadruple frequency circuit, a trigger and a DSP system, the control method comprises the steps of firstly inputting a voltage signal of 50Hz power frequency to obtain a 50Hz square wave signal and a 200Hz synchronous signal, then calculating a switching angle value required to be output by the DSP control system, then designing an interrupt flow required by outputting a switching control signal, and repeatedly outputting a complete periodic waveform for many times. The invention avoids the accumulated error of calculation in the period, improves the symmetry in the period of the output waveform, reduces the output harmonic content of the output voltage and improves the quality of the output waveform.)

1. A SHEPWM control system for controlling the output voltage of a high-power converter comprises a zero-crossing comparator, a quadruple frequency circuit, a trigger and a DSP system,

the quadruple frequency circuit consists of a phase-locked loop integrated circuit CD4046 and a frequency divider CD4017, wherein the INH end of the 5 th pin of the CD4046 is grounded and is at a low level, the CX1 of the 6 th pin and the CX2 of the 7 th pin are externally connected with an oscillation capacitor C1, and the R1 end of the 11 th pin is grounded through an oscillation resistor R3; the 13 th pin PC 2OUT end of the CD4046 is led OUT to the 9 th pin VCOIN end of the CD4046 through a resistor R1, and the resistor R1 is grounded through a resistor R2 and a capacitor C2; in the 13 th pin of the CD4017, a timing sequence allowable end E is grounded and is at a low level; the 10 th pin count output end Q4 of the CD4017 is connected with the 15 th pin reset end MR and the 3 rd pin input end COMPIN of the CD 4046; the 14 th pin clock signal input end CLK of the CD4017 is connected with the 4 th pin voltage-controlled oscillator output end VCOOUT of the CD 4046; the C1 is 22nF, R3 is 47k omega, R1 is 1M omega, R2 is 100k omega, and C2 is 2 muF;

the DSP system is a DSP control chip TMS320F 28335;

an output end VCOOUT of a voltage-controlled oscillator of the No. 4 pin of the CD4046 is connected with a GPIO34/ECAP1 pin of a DSP control chip TMS320F28335, and an output synchronous signal of the output synchronous signal generates an interrupt signal EPWM1INT through an ePWM module in the TMS320F 28335; the 14 th pin SIGIN end of the CD4046 is connected with a GPIO07/ECAP2 pin of a DSP control chip TMS320F28335, and an output synchronous signal generates an interrupt signal EPWM2INT through an ePWM module in the TMS320F 28335.

2. A control method applying the SHEPWM control system according to claim 1, characterized by comprising the steps of:

step 1: obtaining a 50Hz square wave signal by passing a 50Hz power frequency power supply voltage signal through a zero-crossing comparator, inputting the 50Hz square wave signal into a 14 th pin SIGIN end of the CD4046 in the phase-locked quadruple frequency circuit, and generating a 200Hz synchronous signal at a 4 th pin voltage-controlled oscillator output end VCOOUT of the CD 4046;

step 2: calculating a switch angle value required to be output by the DSP system; specifically, when EPWM1INT interruption is generated each time, another interruption TIMER1 is generated, and each time TIMER1 interrupts reading of the next switch angle in the register, a trigger delay angle is obtained, the trigger delay angle is converted into a digital quantity and then accurately output, and then the level of the initial level is judged to be used as the basis for next level inversion;

and step 3: designing interrupt flows required by outputting switch control signals, wherein the interrupt flows comprise an EPWM1INT interrupt flow, an EPWM2INT interrupt flow and a TIMER1 interrupt flow;

wherein, the EPWM2INT interruption process is as follows: triggering EPWM2INT interruption when the 50Hz square wave reaches a rising edge, resetting the EPWM1INT interruption position count, and then exiting EPWM2INT interruption;

the EPWM1INT interruption process comprises the following steps: assuming that in each complete cycle, the numbers are 0, 1,2 and 3 according to 0-pi/2, pi/2-pi, pi-3 pi/2 and 3 pi/2-2 pi respectively, when EPWM1INT interruption is entered each time, the DSP system detects the current phase, namely, counting the EPWM1INT interruption position, determining the approximate area where the switching angle is located, after the EPWM2INT interruption exits, counting the EPWM1INT interruption position to 0, at this time, looking up a table by the expected output voltage amplitude to obtain a switching angle alpha 1 numerical value, sequentially loading the switching angles into a TIMER1 interruption position marking register, comparing the current phase with the switching angle numerical value to obtain a triggering delay angle numerical value interrupted by TIMER1, determining the initial state of a waveform, and loading the waveform numerical value into a TIMER1 interrupted period register;

after each TIMER1 interruption, the TIMER1 position marker count is incremented by 1; after the complete cycle of the 200Hz synchronous signal is finished, the EPWM1INT interrupt position count is increased by 1, the TIMER1 interrupt position mark register is cleared, and the next switch angle area is entered;

let the switching angles of 1,2, and 3 regions be represented by β, γ, and δ, respectively, the switching angle of each region is calculated by the following formula:

wherein N is 1,2,3, …, and N is the number of switching angles in each 1/4 period;

the TIMER1 interruption process comprises the following steps: after the TIMER1 interruption, looking up the table to obtain alpha according to the obtained TIMER1 cycle register value, namely the switch angle and the output voltage amplitude_nThe value of angle, where N is 2,3, …, N; determining the current switch angle and the current switch angle alpha according to the TIMER1 interruption position and the switch angle alpha subscript n_nAngle alpha to next switch_n+1The difference value is the trigger delay angle, and the value of the trigger delay angle is loaded to a TIMER1 period register;

and 4, step 4: taking the switch delay angle value in the TIMER1 period register as the reference of a DSP system control switch device, outputting a control signal according to the switch delay angle value, adding 1 to the marker count of the interrupt position of the TIMER1 after the control signal is output, and exiting TIMER1 interrupt;

repeating the steps 1-4 each time along with the interruption of EPWM1INT, thereby outputting continuous SHEPWM waveform and realizing SHEPWM control on the output voltage of the high-power converter.

Technical Field

The invention belongs to the field of control of power electronic converters, relates to a high-power converter output voltage modulation technology, and particularly relates to a SHEPWM control system and method for controlling the output voltage of a high-power converter.

Background

Modern power electronic technology is rapidly developed in recent years, and voltage source type inverters are widely applied to the fields of new energy distributed power generation grid connection, variable frequency speed regulation devices, electric vehicles, reactive compensation, active power filters, uninterruptible power supplies and the like. Pulse Width Modulation (PWM) is a main voltage Modulation method for a voltage source inverter, which can realize accurate control of output voltage under the condition of determining the switching frequency and the output voltage waveform of the inverter by the Pulse equivalent principle, and reduce the harmonic content of the output voltage by setting a higher switching frequency.

However, in the application fields of high-power converters such as electric locomotive dragging and reactive power compensation, the on-off loss of the switching device is obviously increased, so that the high switching frequency of the conventional PWM brings high switching loss, and the switching frequency has to be reduced to reduce the switching loss. According to the principle of PWM control, the switching frequency determines the degree of sinusoidality of the output waveform, which inevitably degrades the quality of the output waveform. When the switching frequency of the PWM is reduced to several hundred hz, the distortion of the output voltage is severe, and harmonic components are increased in the output waveform of the inverter, which may threaten the safe operation of the inverter and the power system. In order to solve the problems, the characteristic Harmonic output of the inverter under low switching frequency needs to be improved through special optimization, and Specific Harmonic Elimination Pulse Width Modulation (SHEPWM) is the most representative output voltage Modulation mode, a mathematical model is obtained through Fourier analysis on output voltage, then a nonlinear equation set is solved to obtain an inverter switching angle, the on-off of a switching device is controlled at the proper position of the output voltage, and a PWM output waveform is controlled through multiple times of commutation of the inverter, so that the purpose of eliminating specific subharmonics is achieved. Compared with the conventional PWM, the SHEPWM does not need high-frequency carrier waves, can obtain the effect similar to the PWM output voltage with higher switching frequency by utilizing lower switching frequency, and has small switching loss and high efficiency.

The implementation of SHEPWM is described below by taking the example of a general inverter that eliminates the 5, 7, 11 and 13 th harmonic voltages and outputs the corresponding fundamental voltage. According to the symmetry of the sine wave, the fourier decomposition of the output voltage in a quarter of a cycle can be written as:

wherein n is the harmonic order, b_nIs the amplitude of the n-th harmonic wave, U_dcIs the DC side voltage, N is the number of switching angles in 1/4 cycles, alpha_iIs the switching angle.

To zero the harmonics of the 5, 7, 11 and 13 orders in the output voltage, a system of equations can be obtained:

in the formula, alpha₁、α₂、α₃、α₄、α₅The on-off delay angle of the switching device in a quarter cycle of the inverter is 0<α₁<α₂<α₃<α₄<α₅<π/2，M＝U_ref/U_dcThe modulation degree is shown. By solving the equations set forth above, the delay angle of the inverter switches can be obtained while ensuring the fundamental voltage output amplitude. Because the solving process of the nonlinear equations listed above is complicated, at present, an equation set is usually solved offline, the relation between the modulation degree and the trigger delay angle obtained by solving is stored in a control chip of the control system in a data table form, and the switching delay angle can be obtained by looking up the table according to the determined output voltage during control.

One of the main methods for realizing SHEPWM at present is to solve the switching angle according to the switching angle calculation method, calculate all the switching angles in each period, store the calculated switching angles in a register, read the value of the switching angle and calculate the switching delay by interrupting on the premise of calculating the switching angle by taking the rising edge of a 50Hz square wave signal as a reference, and output a control signal. The steps are repeated every time a period passes, and the PWM waveform with specific subharmonics eliminated can be obtained. In the SHEPWM implementation method, the voltage zero-crossing time is used as a counting base point for the switching angle in each complete period, the counter counts in sequence to obtain the corresponding time of the corresponding trigger delay angle, the power electronic switch is controlled to act, the preset inverter output level is output, and after the next voltage zero-crossing interruption occurs, the DSP counter is reset to be used as the counting base point of the next period. Because an error exists between the counting value of the DSP counter and the actual time, the switching time in one period is sequentially loaded after one counting base point, the deviation of the triggering time caused by accumulated errors of the last delay angles in the whole period can be caused, the symmetry of the waveform of the whole period is influenced, the waveform of the output voltage is distorted, the content of harmonic voltage is increased, different harmonic components can be caused to appear in the output waveform by different errors, and the load with higher power quality requirement can be damaged in different degrees.

Therefore, according to the parity symmetry of the sine waveform in one period, the counter of the DSP is cleared once every 1/4 power frequency periods, and the delay angle counting and triggering operations in 1/4 periods are started with a new time scale, so as to reduce the influence of the accumulated error on the distortion of the output waveform, and the basic solution idea is as follows: the switching angle value in 1/4 periods is calculated in advance and stored in a register, a quadruple frequency signal synchronous with the phase of a power frequency signal of 50Hz of a power grid is generated, so that the power frequency period is quartered by using a hardware circuit, the quartered power frequency period is used as a timing base point to generate interruption, the level control of a switching device is realized through a program, and the voltage distortion problem caused by the accumulated error of a counter is reduced.

Object of the Invention

The present invention is directed to solve the above problems in the prior art, and a control method for improving symmetry in a SHEPWM cycle includes a zero-crossing comparator, a quadruple frequency circuit, a flip-flop, and a DSP system. 50Hz power frequency signals of the power grid output 50Hz square waves through a zero crossing comparator, the 50Hz square waves output 200Hz synchronous signals through a phase-locked quadruple frequency circuit, and the 200Hz synchronous signals are used as the reference of the switch angle trigger signals. In each period, the DSP calculates a switching angle according to 1/4 periods of input 50Hz square waves, the switching angle is used as the switching angle in a complete period of a 200Hz synchronous signal, the aim of improving symmetry in the period is achieved, after each period is finished, the DSP system sends an interrupt request, a counter in the DSP is cleared, the next period repeats the steps, and continuous SHEPWM waveforms can be output.

Disclosure of Invention

According to one aspect of the invention, a SHEPWM control system for controlling the output voltage of a high-power converter is provided, which comprises a zero-crossing comparator, a quadruple frequency circuit, a trigger and a DSP system;

the quadruple frequency circuit consists of a phase-locked loop integrated circuit CD4046 and a frequency divider CD4017, wherein the INH end of the 5 th pin of the CD4046 is grounded and is at a low level, the CX1 of the 6 th pin and the CX2 of the 7 th pin are externally connected with an oscillation capacitor C1, and the R1 end of the 11 th pin is grounded through an oscillation resistor R3; the 13 th pin PC 2OUT end of the CD4046 is led OUT to the 9 th pin VCOIN end of the CD4046 through a resistor R1, and the resistor R1 is grounded through a resistor R2 and a capacitor C2; in the 13 th pin of the CD4017, a timing sequence allowable end E is grounded and is at a low level; the 10 th pin count output end Q4 of the CD4017 is connected with the 15 th pin reset end MR and the 3 rd pin input end COMPIN of the CD 4046; the 14 th pin clock signal input end CLK of the CD4017 is connected with the 4 th pin voltage-controlled oscillator output end VCOOUT of the CD 4046; the C1 is 22nF, R3 is 47k omega, R1 is 1M omega, R2 is 100k omega, and C2 is 2 muF;

the DSP system is a DSP control chip TMS320F 28335;

an output end VCOOUT of a voltage-controlled oscillator of the No. 4 pin of the CD4046 is connected with a GPIO34/ECAP1 pin of a DSP control chip TMS320F28335, and an output synchronous signal of the output synchronous signal generates an interrupt signal EPWM1INT through an ePWM module in the TMS320F 28335; the 14 th pin SIGIN end of the CD4046 is connected with a GPIO07/ECAP2 pin of a DSP control chip TMS320F28335, and an output synchronous signal generates an interrupt signal EPWM2INT through an ePWM module in the TMS320F 28335.

According to another aspect of the present invention, there is provided a SHEPWM control method using the above control system, comprising the steps of:

step 1: obtaining a 50Hz square wave signal by passing a 50Hz power frequency power supply voltage signal through a zero-crossing comparator, inputting the 50Hz square wave signal into a 14 th pin SIGIN end of the CD4046 in the phase-locked quadruple frequency circuit, and generating a 200Hz synchronous signal at a 4 th pin voltage-controlled oscillator output end VCOOUT of the CD 4046;

step 2: calculating a switch angle value required to be output by the DSP system; specifically, when EPWM1INT interruption is generated each time, another interruption TIMER1 is generated, and each time TIMER1 interrupts reading of the next switch angle in the register, a trigger delay angle is obtained, the trigger delay angle is converted into a digital quantity and then accurately output, and then the level of the initial level is judged to be used as the basis for next level inversion;

and step 3: designing interrupt flows required by outputting a switch control signal, wherein the interrupt flows comprise an EPWM1INT interrupt flow, an EPWM2INT interrupt flow and a TIMER1 interrupt flow;

wherein, the EPWM2INT interruption process is as follows: triggering EPWM2INT interruption when the 50Hz square wave reaches a rising edge, resetting the EPWM1INT interruption position count, and then exiting EPWM2INT interruption;

the EPWM1INT interruption process comprises the following steps: assuming that in each complete cycle, the numbers are 0, 1,2 and 3 according to 0-pi/2, pi/2-pi, pi-3 pi/2 and 3 pi/2-2 pi respectively, when EPWM1INT interruption is entered each time, the DSP system detects the current phase, namely, counting the EPWM1INT interruption position, determining the approximate area where the switching angle is located, after the EPWM2INT interruption exits, counting the EPWM1INT interruption position to 0, at this time, looking up a table by the expected output voltage amplitude to obtain a switching angle alpha 1 numerical value, sequentially loading the switching angles into a TIMER1 interruption position marking register, comparing the current phase with the switching angle numerical value to obtain a triggering delay angle numerical value interrupted by TIMER1, determining the initial state of a waveform, and loading the waveform numerical value into a TIMER1 interrupted period register;

after each TIMER1 interruption, the TIMER1 position marker count is incremented by 1; after the complete cycle of the 200Hz synchronous signal is finished, the EPWM1INT interrupt position count is increased by 1, the TIMER1 interrupt position mark register is cleared, and the next switch angle area is entered;

let the switching angles of 1,2, and 3 regions be represented by β, γ, and δ, respectively, the switching angle of each region can be obtained by the following equation:

wherein N is 1,2,3, …, and N is the number of switching angles in each 1/4 period;

the TIMER1 interruption process comprises the following steps: after the TIMER1 interruption, looking up the table to obtain alpha according to the obtained TIMER1 cycle register value, namely the switch angle and the output voltage amplitude_nThe value of angle, where N is 2,3, …, N; determining the current switch angle and the current switch angle alpha according to the TIMER1 interruption position and the switch angle alpha subscript n_nAngle alpha to next switch_n+1The difference value is the triggered delay angle, the value of the triggered delay angle is loaded into the TIMER1 period register,

and 4, step 4: taking the switch delay angle value in the TIMER1 period register as the reference of a DSP system control switch device, outputting a control signal according to the switch delay angle value, adding 1 to the marker count of the interrupt position of the TIMER1 after the control signal is output, and exiting TIMER1 interrupt;

repeating the steps 1-4 each time along with the interruption of EPWM1INT, thereby outputting continuous SHEPWM waveform and realizing SHEPWM control on the output voltage of the high-power converter.

Drawings

Fig. 1 shows a topology diagram of a quadruple frequency circuit in a SHEPWM control system for the output voltage of a high power converter according to the present invention.

Fig. 2 is a flowchart of the output voltage control method for the high-power converter according to the present invention.

FIG. 3 is a EPWM1INT interrupt flow chart of the control method of the present invention.

FIG. 4 is a EPWM2INT interrupt flow diagram of the control method of the present invention.

FIG. 5 is a TIMER1 interrupt flow chart of the control method of the present invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The invention relates to a SHEPWM control system for output voltage of a high-power converter, which comprises a zero-crossing comparator, a quadruple frequency circuit, a trigger and a DSP system. Fig. 1 is a topological diagram of a quadruple frequency circuit in a SHEPWM control system for the output voltage of a high-power converter according to the present invention. As shown in FIG. 1, a 50Hz square wave signal is obtained from a 50Hz power frequency power supply voltage signal through a zero-crossing comparator, and the 50Hz square wave signal generates a 200Hz synchronous signal through a phase-locked quadruple frequency circuit. The quadruple frequency circuit consists of a phase-locked loop integrated circuit CD4046 and a frequency divider CD4017, and the specific connection relationship is as follows: the inhibit terminal (pin 5) of CD4046 is grounded (low); 6. a 7-pin external oscillation capacitor C1(22 nF); pin 11 is grounded through an oscillating resistor R3(47k omega); the output end (pin 13) of the phase comparator II is led out to the control end (pin 9) of the voltage-controlled oscillator through R1(1M omega), and R1 is grounded through R2(100k omega) and C2(2 muF); the CD4017 time sequence allows the end (13 feet) to be grounded (low level); the counting output end Q4 (pin 10) is connected with the reset end (pin 15) and the CD4046 comparison signal input end (pin 3); the clock signal input (pin 14) is connected to the output (pin 4) of the CD4046 voltage controlled oscillator.

The principle of the frequency multiplier circuit is as follows: the phase detector finds that the feedback signal and the input signal have phase difference and converts the phase difference into a corresponding voltage signal, the voltage signal is filtered and corrected by the loop filter and then sent to the voltage-controlled oscillator, and the voltage-controlled oscillator converts the sent voltage into a corresponding frequency and transmits the corresponding frequency to the frequency divider (the steps are finished inside 4046). The frequency divider feeds back to the input end for phase discrimination again through 4 frequency division (corresponding to a Q4 counting end) until the phase difference is zero, the phase-locked loop is in a locked state, the frequency of the input signal is the same as that of the 4 frequency division feedback signal, and the purpose of 4 frequency multiplication of the input signal is achieved.

The specific process of using the control system to carry out SHEPWM control on the output voltage of the high-power converter is as follows:

50Hz square wave signals are input through a CD4046 signal input end (14 pins), and 200Hz synchronous signals are output at an output end (4 pins) of the voltage-controlled oscillator. By utilizing the characteristic, 1/4 periods of the 50Hz square wave and a complete period of the 200Hz synchronous signal form a corresponding relation on a time domain, so that the initial time (marked as number 0) of the 200Hz synchronous signal is determined by the rising edge (or the falling edge) of the 50Hz square wave, and the rising edge of the 50Hz square wave passes each time, the trigger triggered by the edge triggers the interruption, so that the internal register is cleared.

Selecting a DSP control chip TMS320F28335 as a DSP system of a control system; in the quadruple frequency circuit, the output end VCOOUT of the voltage-controlled oscillator with the 4 th pin of the CD4046 is connected with the GPIO34/ECAP1 pin of the DSP control chip TMS320F28335, and the output synchronous signal generates an interrupt signal EPWM1INT through an ePWM module in the TMS320F 28335; the 14 th pin SIGIN end of the CD4046 is connected with a GPIO07/ECAP2 pin of a DSP control chip TMS320F28335, and an output synchronous signal generates an interrupt signal EPWM2INT through an ePWM module in the TMS320F 28335.

When EPWM1INT interruption is generated each time, another interruption TIMER1 is generated by the interruption, and the next switch angle in the register is read in an interruption mode by TIMER1 each time, namely a trigger delay angle is obtained and is accurately output after being converted into a digital quantity; and then, judging the level of the initial level, and taking the initial level as the basis of next level inversion. Passing through the above process every 1/4 cycles can achieve a SHEPWM signal output within 1/4 cycles. Due to the symmetry of the output waveform, after 1/4 periods are finished, the switching angle in the lower 1/4 period is obtained according to the fact that the switching angle in the register is symmetrical about 90 degrees, namely according to alpha₁+α_NCalculating the switching angle at 90 degrees, and obtaining the switching angle in the next half period according to the operation, namely obtaining the switching angle symmetrically about 180 degrees and 270 degrees from the previous 1/4 periods respectively, so that the SHEPWM waveform in a complete period can be output.

Fig. 2 is a flow chart of the output voltage control method for the high-power converter according to the invention.

The complete interrupt flow is described below with the 50Hz square wave rising edge as the natural starting point. Fig. 3, 4, and 5 are interrupt flow charts of the EPWM1INT, EPWM2INT, and TIMER1 interrupt flows, respectively, and as shown in the figure, the specific interrupt flows are as follows:

the EPWM2INT interruption process comprises the following steps: and when the 50Hz square wave reaches a rising edge, triggering EPWM2INT interruption, clearing the EPWM1INT interruption position count, and exiting the EPWM2INT interruption.

The EPWM1INT interruption process comprises the following steps: in each complete period, the numbers of 0-pi/2, pi/2-pi, pi-3 pi/2 and 3 pi/2-2 pi are respectively 0, 1,2 and 3, when EPWM1INT interruption is entered each time, the DSP system detects the phase (EPWM1INT interruption position count) at the moment, namely, the approximate area where the switching angle is located is determined, and after the EPWM2INT interruption exits, the EPWM1INT interruption position count should be 0. At this time, according to the above-mentioned switching angle solving process, the switching angle α is obtained by looking up the table from the expected output voltage amplitude₁And the switching angle sequence (i.e. the subscript of the solving process switching angle) is loaded into the TIMER1 interrupt position flag register, and the current phase and switching angle values are compared to obtain the triggered delay angle value of TIMER1 interrupt, i.e. the initial state of the waveform is determined and loaded into the period register of TIMER1 interrupt. Each time the TIMER1 interruption is complete, the TIMER1 position marker count is incremented by 1. After the 200Hz synchronous signal complete period is finished, the EPWM1INT interrupt position count is increased by 1, the TIMER1 interrupt position mark register is cleared, and the next switch angle area is entered.

Let the switching angles of 1,2, and 3 regions be represented by β, γ, and δ, respectively, the switching angle of each region can be obtained by the following equation:

wherein N is 1,2,3, …, and N is the number of switching angles in each 1/4 cycles.

TIMER1 interruption flow as shown in FIG. 5, each time TIMER1 interruption is entered, the table is looked up according to the obtained TIMER1 period register value (switch angle) and output voltage amplitude to obtain alpha_n(N-2, 3, …, N) angle value, from the TIMER1 interrupt position (switch angle index), the current switch angle (α), can be determined_n) Angle (alpha) to next switch_n+1) The difference value of (a) is the triggered delay angle, and the value is loaded into the TIMER1 period register and the TIMER1 period registerThe turn-off delay angle value is the reference of the DSP system for controlling the switch device, and a control signal is output according to the value. After outputting the control signal, TIMER1 increments the flag for interrupt position by 1, exiting TIMER1 interrupt. The above process is repeated each time with an EPWM1INT interrupt.

3) After each complete cycle of the 50Hz square wave signal (4 complete cycles of the 200Hz synchronous signal, namely the areas numbered 0, 1,2 and 3 are finished outputting the control signal according to the process), the rising edge of the 50Hz square wave enables the trigger to send an interrupt request to the DSP system through the interrupt EPWM2INT, the DSP internal register is cleared, the steps are repeated after resetting, and therefore continuous SHEPWM waveforms are output, and SHEPWM control over the output voltage of the high-power converter is achieved.

In summary, the control system and method of the invention realize the effect of using 200Hz synchronous signal to replace 50Hz power frequency signal as the reference of the trigger signal of the switch angle, and synchronize the timer by realizing a quarter period according to the symmetry of the sine wave, thereby reducing the accumulated error caused by counting the timer of the switch delay angle in the whole power frequency period by the control system, improving the control precision of the switch delay angle, ensuring the symmetry of the output voltage in the whole power frequency period, achieving the purpose of improving the symmetry in the output waveform period, and improving the quality of the output voltage waveform.