阅读说明：本技术 一种基于开关电容的伪电阻矫正电路 (Pseudo resistance correction circuit based on switched capacitor ) 是由 陈铭易 郝禹植 李永福 陈威富 于 2020-12-31 设计创作，主要内容包括：本发明涉及模拟集成电路技术领域,公开了一种基于开关电容的伪电阻矫正电路,通过开关电容矫正电路产生一基准电阻,其阻值大小仅与开关电容的电容值和开关的频率有关,使用并联转串联的电路设计方案以及电压积分器将控制电压提取来控制伪电阻,可以得到阻值为基准电阻XYZ倍的伪电阻,该伪电阻阻值精确可调,对PVT波动的鲁棒性好,线性度相比传统伪电阻有提高。(The invention relates to the technical field of analog integrated circuits, and discloses a pseudo resistor correction circuit based on a switched capacitor.)

1. A pseudo resistance correction circuit based on a switched capacitor comprises a switched capacitor correction loop (1), a voltage integrator (2) and a level conversion module (3); the switched capacitor correction circuit is characterized in that the switched capacitor correction circuit (1) generates a reference resistor, the voltage integrator (2) extracts control voltage and controls the pseudo resistor (4) through the level transfer module (3) to obtain the pseudo resistor with the resistance value being XYZ times of that of the reference resistor.

2. The switched capacitor-based pseudo resistance correction circuit according to claim 1, wherein the resistance of the reference resistor is related to the capacitance of the switched capacitor and the frequency of the switch, and is independent of PVT fluctuations.

3. Switched capacitor-based pseudo-resistance correction circuit according to claim 1 or 2, characterized in that the switched capacitor correction loop (1) comprises a switched capacitor (11), a feedback loop (12) and an X:1 current mirror (13);

the switch capacitor (11) is composed of two CMOS switches connected end to end and a first capacitor (C), an intermediate node connected with the two CMOS switches is connected with one end of the first capacitor (C), the other end of the first capacitor (C) is grounded, and two ports of the two CMOS switches are respectively connected with a constant potential (Vcm) and a port of a current mirror (13) through which X-time current flows; the signals for controlling the on and off of the two CMOS switches are generated by an additional control circuit;

the feedback loop (12) is formed by a first operational amplifier (op)₁) And Y parallel P-type metal oxide semiconductor field effect transistors (M)_p1…M_py) Composition is carried out;

the current mirror (13) is composed of a first P-type transistor (M) with the same channel length and the width ratio of X:1₁) And a second P-type transistor (M)₂) Composition, said first P-type transistor (M)₁) And a first P-type transistor (M)₁) Is connected to form a diode connection, the voltage generated is used to control the gate voltage of two P-type transistors, the first P-type transistor (M)₁) Is connected to an external port of a CMOS switch of said switched capacitor (11), said second p-type transistor (M)₂) The drain gate of which is connected to the source of Y parallel P-type transistors in the feedback loop (12), the body terminals of the Y parallel P-type transistors being connected to the source, the drain of each P-type transistor being connected to a constant potential (Vcm); the gate voltages of the parallel Y P-type transistors are controlled by the first operational amplifier (op)₁) The first operational amplifier (op)₁) Is connected to a port of the current mirror (13) through which a current of X times flows, the first operational amplifier (op)₁) Is connected to the port of the current mirror (13) through which a current of 1 times flows.

4. According to claim 1The switched capacitor-based pseudo resistance correction circuit of claim 2, wherein the voltage integrator (2) is a Y P-type transistors (M) connected in parallel in one duty cycle of the switched capacitor correction loop (1)_p1…M_py) Integrating the gate-source voltage (Vgs _1) of the first transistor and outputting an average value (Vgs _2) of the gate-source voltage (Vgs _1) in one period; the three working states are reset, sampled and integrated, and state switching signals among different working states are generated by an additional control circuit.

5. The switched-capacitor based pseudo-resistance correction circuit according to claim 1, wherein: the level conversion module (3) consists of four switches and a second capacitor (C)_b2) The device comprises two working states of sampling and correcting:

sampling the working state: when the output of the voltage integrator (2) is stable, the output voltage of the voltage integrator (2) relative to the constant potential (Vcm) is sampled and stored in the second capacitor (C)_b2) The above step (1);

and (3) correcting the working state: a second capacitance (C)_b2) The output voltage is applied to the gate-source capacitance (C) of said dummy resistor (4)_b1) The gate-source voltage (Vgs _2) of the pseudo resistor (4) is corrected by using the voltage, so that the resistance value of the pseudo resistor is corrected.

6. The switched-capacitor based pseudo-resistance correction circuit according to claim 1, wherein: the pseudo resistor (4) comprises Z P-type transistors (M) connected in series_pr1…M_prz) And a gate-source capacitance (C) connected between the gate and the source of the P-type transistor_b1) The gate-source capacitance (C)_b1) The voltage is used for storing voltage, the charging and discharging of the voltage are controlled by the level conversion module (3), and the voltage can be used for controlling the resistance value of the pseudo resistor (4) in real time.

7. The switched-capacitor based pseudo-resistance correction circuit according to claim 1, wherein: the Y P-type metal oxide semiconductor field effect transistors (M)_p1…M_py) And Z P-type transistors (M)_pr1…M_prz) Are the same size.

Technical Field

The invention relates to the technical field of analog integrated circuits, in particular to a pseudo-resistance correction circuit based on a switched capacitor.

Background

The rapid development of analog integrated circuits and the expansion of biomedical markets in recent years have made the integration of circuit design and biomedical technology an irreversible trend. In various wearable physiological signal detection devices, a physiological signal acquisition amplifier with a band-pass characteristic is designed in order to suppress offset voltage of an electrode, and a very large capacitance or resistance is often required in order to form a very low high-pass cut-off frequency (lower than 0.67Hz for ECG acquisition), which is usually realized by using an off-chip device, and is not beneficial to improving the integration level, so that it is very important for a biomedical circuit to realize the very low high-pass cut-off frequency by using the on-chip device.

Common methods for achieving very low high-pass cut-off frequency on-chip can be divided into: 1. the feedback network of the amplifier is directly formed by a large resistor, the band-pass characteristic is formed by a capacitor connected with the resistor in parallel, and 2, the output signal is integrated by a direct current servo loop (DSL for short) and fed back to the input. However, since it is still necessary to form an integrator with a very low frequency in DSL, it is still necessary to implement a large resistance or a large capacitance on the chip.

For the limited area on the chip, realizing large capacitance on the chip wastes a large amount of chip area and increases the design cost, so that one G (10) is realized on the chip⁹) A resistance in the order of ohms is a more reasonable choice. In order to realize such a resistor, a conventional method includes a switched capacitor resistor (SC), a Duty Cycle Resistor (DCR) and a Pseudo Resistor (PR). With the SC and DCR method, a maximum number of G ohms of resistors can be implemented on a chip, but such a resistance value is still small, and in order to achieve a specified high-pass cut-off frequency, a capacitance of 100pF order of magnitude still needs to be implemented on a chip, which causes waste of area, while with the PR resistors, a number of T ohms can be achieved, but the resistance value is uncontrollable and can vary with the process, the supply voltage and temperature (PVT for short), and the voltage difference between two ends of the device, thereby reducing the linearity of the amplifier.

Since the application of the pseudo-resistor technology to the field of biomedical science was proposed in 2003, various pseudo-resistor correction technologies were developed to achieve resistance controllability and improve robustness to PVT. Although the digital-to-analog converter is used for providing the bias voltage for the pseudo resistor, the resistance value is controllable and has good linearity, but the robustness of the resistance value to PVT is poor. The pseudo resistor is biased by using the current source which is in direct proportion to the absolute temperature, so that the resistance value can be accurately controlled, good PVT robustness is achieved, the pseudo resistor can only work near a set working point, and the linear area of an output signal is small.

Disclosure of Invention

The invention aims to solve the problems that the existing pseudo resistor correction circuit is poor in PVT robustness, small in output signal linear area and incapable of accurately controlling resistance, and provides a switched capacitor-based pseudo resistor correction circuit which is low in power consumption, small in area and capable of achieving multi-pseudo resistor multiplexing.

The invention is realized by adopting the following technical scheme:

a pseudo resistance correction circuit based on a switched capacitor comprises a switched capacitor correction loop, a voltage integrator and a level conversion module; the switch capacitor correction circuit is characterized in that the switch capacitor correction circuit generates a reference resistor, the voltage integrator extracts control voltage and controls the pseudo resistor through the level transfer module to obtain the pseudo resistor with the resistance value being XYZ times of the reference resistor.

The resistance value of the reference resistor is only related to the capacitance value of the switch capacitor and the frequency of the switch, and is not related to the fluctuation of PVT.

The switch capacitor correction loop comprises a switch capacitor, a feedback loop and an X:1 current mirror;

the switch capacitor is composed of two CMOS switches connected end to end and a first capacitor, the middle node connected with the two CMOS switches is connected with one end of the first capacitor, the other end of the first capacitor is grounded, and two ports of the two CMOS switches are respectively connected with a constant potential and a port through which X-time current flows by a current mirror; the signals for controlling the on and off of the two CMOS switches are generated by an additional control circuit;

the feedback loop consists of a first operational amplifier and Y P-type metal oxide semiconductor field effect transistors connected in parallel;

the current mirror is composed of a first P-type transistor and a second P-type transistor, the length of the channel of the first P-type transistor is the same, the width ratio of the channel of the first P-type transistor to the width of the channel of the second P-type transistor is X:1, the grid electrode of the first P-type transistor is connected with the drain electrode of the first P-type transistor to form diode connection, the generated voltage is used for controlling the grid electrode voltage of the two P-type transistors, the drain electrode of the first P-type transistor is connected with the outer port of a CMOS switch of the switch capacitor, the drain electrode of the second P-type transistor is connected with the source electrodes of Y parallel P-type transistors in the feedback loop, the body ends of the Y parallel P-type transistors are connected with the source electrodes, and the drain electrode of each P-; the grid voltage of the Y parallel P-type transistors is controlled by the output of the first operational amplifier, the positive input port of the first operational amplifier is connected with the port of the current mirror through which the X-time current flows, and the negative input port of the first operational amplifier is connected with the port of the current mirror through which the 1-time current flows.

The voltage integrator is used for integrating the grid source voltages of Y P-type transistors which are connected in parallel in one working period of the switched capacitor correction loop circuit and outputting the average value of the grid source voltages in one working period; the three working states are reset, sampled and integrated, and state switching signals among different working states are generated by an additional control circuit.

The level conversion module consists of four switches and a second capacitor, and has two working states of sampling and correcting:

sampling the working state: after the output of the voltage integrator is stable, sampling the output voltage of the voltage integrator relative to the constant potential, and storing the output voltage on a second capacitor;

and (3) correcting the working state: the output voltage of the second capacitor) is applied to the gate-source capacitor of the pseudo resistor, and the average value of the gate-source voltage of the pseudo resistor is corrected through the voltage, so that the aim of correcting the resistance value of the pseudo resistor is fulfilled.

The pseudo resistor comprises Z P-type transistors connected in series and a gate-source capacitor connected between the grid and the source of the P-type transistors, the gate-source capacitor is used for storing voltage, the charge and discharge of the gate-source capacitor are controlled by the level conversion module, and the voltage can be used for controlling the resistance value of the pseudo resistor in real time.

The Y P-type metal oxide semiconductor field effect transistors and the Z P-type transistors have the same size.

The beneficial technical effects of the invention are as follows:

by adopting a design scheme of a switched capacitor correction loop and a parallel-to-serial circuit, the resistance value of the pseudo resistor is amplified to XYZ times of the resistance value of the switched capacitor, the resistance value of the pseudo resistor is adjustable, the robustness of the pseudo resistor to PVT is improved, the gate-source voltage of the pseudo resistor cannot change along with the voltage at two ends of the pseudo resistor, and the linearity of the resistor is improved.

Drawings

FIG. 1 is a schematic diagram of a structural framework of a pseudo resistance correction circuit based on a switched capacitor according to the present invention;

FIG. 2 is a schematic circuit diagram of a switched capacitor based pseudo resistance correction circuit according to the present invention;

FIG. 3 is a circuit schematic of a pseudo resistor of the present invention;

FIG. 4 is a schematic diagram of the working timing sequence of the pseudo resistance correction circuit based on the switched capacitor according to the present invention;

FIG. 5 is a schematic diagram of the first, second and third operational amplifiers of the present invention;

FIG. 6 is a relationship between pseudo resistance and control signal frequency;

FIG. 7 is a graph showing a comparison of the resistance change of the corrected pseudo resistor with that of a conventional pseudo resistor at different temperatures and at three process corners (tt, ff, ss);

FIG. 8 is a graph showing a comparison of the resistance change of the corrected pseudo resistor with that of the conventional pseudo resistor at different power supply voltages and three process corners (tt, ff, ss);

fig. 9 is a diagram for comparing the linearity of the corrected pseudo resistor with that of the conventional pseudo resistor.

Detailed Description

The following detailed description of the present invention is provided in connection with the accompanying drawings and the preferred embodiments, but should not be construed to limit the scope of the present invention.

As shown in fig. 1, the invention provides a switched capacitor-based pseudo resistor correction circuit, which amplifies the resistance of a pseudo resistor to XYZ times of the resistance of a switched capacitor through a switched capacitor correction loop and a parallel-to-serial circuit, and the resistance of the pseudo resistor is adjustable, and improves the robustness of the pseudo resistor to PVT, the gate-source voltage of the pseudo resistor does not change with the voltages at the two ends of the pseudo resistor, and the linearity of the resistor is improved.

As shown in fig. 2, a specific structure of a switched capacitor based pseudo resistance correction circuit includes: the device comprises a switched capacitor rectification loop 1, a voltage integrator 2 and a level conversion module 3;

the switched capacitor correction loop consists of a switched capacitor 11, a feedback loop 12 (consisting of an operational amplifier and Y parallel P-type metal oxide semiconductor field effect transistors) and an X:1 current mirror 13. The switch capacitor 11 is composed of two CMOS switches and a capacitor C, the two CMOS switches are connected end to end, the middle node is connected with one end of the capacitor C, the other end of the capacitor C is grounded, the other ports of the two CMOS switches are respectively connected to the port of the current mirror 13 through which the X-fold current flows and a constant potential Vcm, and a signal phi for controlling the two CMOS switches to be switched on and off₂、Generated by additional control circuitry. The current mirror 13 is composed of two P-type transistors M with the same channel length and the same width ratio of X:1₁、M₂Composition of P-type transistor M with width X times₁Is connected to the drain to form a diode connection, and the generated voltage is used to control two P-type transistors M in the current mirror 13₁、M₂The gate voltage of (c). P-type transistor M for passing X times of current in current mirror 13₁Is connected with the upper end of the switch capacitor 11, and a p-type transistor M with 1 time current flows in the current mirror 13₂Is connected to the sources of Y parallel P-type transistors M in the feedback loop 12_p1～M_pyThe body terminals of which are connected to the source, and the drains are both connected to a constant potential Vcm, to which the lower terminal of the switched capacitor 11 is also connected. Parallel Y P-type transistors M_p1～M_pyThe positive input port of the operational amplifier is connected to the port of the current mirror 13 through which X times of current flows, and the negative input port of the operational amplifier is connected to the port of the current mirror 13 through which 1 time of current flows. Under the action of the current mirror 13 and the feedback network, the current flowing through each of the Y parallel P-type transistors is one XY times of that flowing through the switch capacitor 11, and V₁Is equal to V₂So that each of the parallel P-type transistorsThe resistance of the transistor is XY times of the resistance of the switch capacitor, the transistor works in a subthreshold region, the resistance value of the transistor is only controlled by Vgs voltage, and the grid voltage of the transistor is determined by the output of the operational amplifier in the feedback loop 12.

The voltage integrator 2 is composed of a switch capacitance integrator, integrates the grid-source voltage Vgs of Y P-type transistors which are connected in parallel in one working period of the switch capacitance correction loop, and outputs the average value of Vgs in one period, and the switch capacitance integrator has three working states of reset, sampling and integration which are respectively represented by phi₃，And phi₁Three signals control, the switching signals between different states being generated by additional control circuits, in the voltage integrator 2 module, C_s1To sample the capacitance, C_s2For integrating capacitance, in the sampling phase C_s1Sample Vgs of Y transistors in parallel, and integrate C_s1Charge on to C_s2To above, C_s1And C_s2The capacitance is proportioned so that the integrator outputs a voltage amount of an average value Vgs _2 of Y transistors Vgs in one period.

The level conversion module 3 comprises four switches and a second capacitor C_b2Is composed of two states of sampling and correcting, each of which is composed ofAnd phi₄Control, in the sampling state, when the voltage integrator 2 outputs a stabilized voltage Vgs _2 of the sampled voltage integrator 2 with respect to the constant potential Vcm, to store the voltage Vgs _2 in the second capacitor C_b2In the correcting state, the voltage Vgs _2 on the sampling capacitor is applied to the gate-source capacitor C of the pseudo resistor_b1In the above way, the gate-source voltage Vgs _3 of the pseudo resistor can be corrected to Vgs _2, so as to achieve the purpose of correcting the resistance value of the pseudo resistor.

As shown in FIG. 3, in order to correct the structure of the dummy resistor 4, a gate-source capacitor C is arranged between the gate and the source of the dummy resistor 4_b1For holding the voltage Vgs _3 of the voltage,the voltage Vgs _3 can be used for controlling the resistance value of the pseudo resistor 4 in real time, and when the correction circuit reaches a stable working state, the gate-source capacitor C_b1The voltage Vgs _3 is stabilized, and the charge on the level conversion module 3 is only used for compensating the grid source capacitance C_b1The pseudo resistor 4 is composed of Z P-type transistors M due to the error caused by leakage_pr1～M_przThe series connection is formed, and has the same size as the Y P-type transistors connected in parallel in the switched capacitor rectifying circuit 1. Finally, the effect of correcting the resistance value of the pseudo resistor 4 to be XYZ times of the resistance value of the switch capacitor is achieved, meanwhile, since the reference resistor is composed of the switch capacitor 11, the resistance value is easy to adjust and cannot be influenced by PVT fluctuation, and the gate-source capacitor C is used in the pseudo resistor 4_b1The Vgs of the series-connected P-type transistors is controlled, so that the resistance value of the pseudo resistor is adjustable, the PVT stability is good, and the linearity of the pseudo resistor 4 is improved.

As shown in FIG. 4, the timing of each switch in the pseudo-resistance correction circuit based on the switched capacitor is shown₁φ₂φ₃φ₄Are all generated by a clock signal. Exemplified below at phi₂The switch capacitor 11 completes one charge and discharge in one period of signal and simultaneously starts to work at phi₁Signal controlled switched capacitor integrator at phi₂Four sampling integrations are carried out in one period of the signal, and phi is used before the integrator works₃The signal resets the integrator at phi₂In the next period of the signal, the integrator is no longer operating but remains outputting, and the output voltage is controlled by phi₄The voltage conversion module controlled by the signal samples, and the sampled voltage is used for correcting the voltage on the capacitor between the grid sources in the pseudo resistor 4, so that the aim of controlling the resistance value of the pseudo resistor is fulfilled.

Fig. 5 shows an operational amplifier used in the pseudo resistance correction circuit based on the switched capacitor in the above example.

As shown in FIG. 6, the relationship between the pseudo resistance and the clock frequency is shown, in the above example, the clock frequency is φ₂The signal frequency is 8 times, so the pseudo resistance and phi are also expressed₂The relationship of the signal frequency.

As shown in FIG. 7, in order to compare the corrected pseudo resistor with the conventional pseudo resistor at 0-85 ℃ under different process angles, the maximum fluctuation of the resistance value is reduced from 1800 times to 2 times.

As shown in fig. 8, the supply voltage of 3.3V is taken as an example, and the supply voltage fluctuates from 3V to 3.6V under different process corners, and the corrected pseudo resistor has a resistance fluctuation reduced from 530 times to 2.5 times compared with the conventional pseudo resistor.

As shown in fig. 9, in order to correct the comparison between the linearity of the pseudo resistor and the conventional pseudo resistor, the range of the linearity of the resistor is improved by 10%.

The invention generates a reference resistor through the switched capacitor correction circuit 1, the reference resistor is composed of switched capacitors, the resistance value of the reference resistor is only related to the capacitance value of the switched capacitors and the switching frequency, but is not related to the fluctuation of PVT, the pseudo resistor 4 is controlled by using a parallel-to-serial circuit design scheme and the voltage integrator 2 to extract the control voltage, the pseudo resistor 4 with the resistance value being XYZ times of that of the reference resistor can be obtained, the resistance value of the pseudo resistor 4 is adjustable, the robustness to PVT fluctuation is good, and the linearity is improved compared with that of the traditional pseudo resistor.

Although particular embodiments of the present invention have been described above, it will be understood by those skilled in the art that these are by way of example only and that various changes or modifications may be made to these embodiments without departing from the spirit and scope of the invention and, therefore, the scope of the invention is to be defined by the appended claims.