阅读说明：本技术 一种异步真四相握手协议电路及其控制方法 (Asynchronous true four-phase handshake protocol circuit and control method thereof ) 是由 袁甲 胡晓宇 于增辉 于 2021-03-26 设计创作，主要内容包括：本发明涉及一种异步真四相握手协议电路及其控制方法,电路包括：第一反相器、第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第八MOS管、第一反相装置和第二反相装置；第一反相器的输入端连接第一请求信号；第三MOS管的栅极连接第二请求信号,第四MOS管的栅极和第七MOS管的栅极均连接第二应答信号,第一反相装置的一端连接第一应答信号；第二反相装置的一端连接第二请求信号。本发明在请求信号上升沿到来时仅回复应答信号,在请求信号下降沿到来时捕获数据,因此本发明能够降低延迟链的开销,提升电路的工作速度。(The invention relates to an asynchronous true four-phase handshake protocol circuit and a control method thereof, wherein the circuit comprises: the MOS transistor comprises a first phase inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first phase-inverting device and a second phase-inverting device; the input end of the first inverter is connected with a first request signal; the grid electrode of the third MOS tube is connected with a second request signal, the grid electrode of the fourth MOS tube and the grid electrode of the seventh MOS tube are both connected with a second response signal, and one end of the first inverting device is connected with a first response signal; one end of the second inverting device is connected with the second request signal. The invention only replies the response signal when the rising edge of the request signal arrives, and captures data when the falling edge of the request signal arrives, so the invention can reduce the expense of the delay chain and improve the working speed of the circuit.)

1. An asynchronous true four-phase handshake protocol circuit, comprising:

the MOS transistor comprises a first phase inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first phase-inverting device and a second phase-inverting device;

the input end of the first phase inverter is connected with a first request signal, and the output end of the first phase inverter is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the first MOS tube and the source electrode of the fourth MOS tube are both connected with a working voltage end, and the drain electrode of the first MOS tube is connected with a first node; the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with a second request signal, and the source electrode of the third MOS tube and the source electrode of the eighth MOS tube are both connected with a common ground terminal; the grid electrode of the fourth MOS tube and the grid electrode of the seventh MOS tube are both connected with a second response signal, and the drain electrode of the fourth MOS tube is connected with the source electrode of the fifth MOS tube; the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are both connected with a second node, and the substrate of the fifth MOS tube and the substrate of the fourth MOS tube are connected with a working voltage end; the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are both connected with the first node, and the source electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube; the source electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube;

one end of the first inverting device is connected with the first node, and the other end of the first inverting device is connected with a first response signal; one end of the second inverting device is connected with the second node, and the other end of the second inverting device is connected with a second request signal.

2. The asynchronous true four-phase handshake protocol circuit according to claim 1, wherein the first inverting means comprises a second inverter and a third inverter connected in parallel;

the input end of the second phase inverter is respectively connected with the output end of the third phase inverter and the first node, and the output end of the second phase inverter is respectively connected with the input end of the third phase inverter and the first response signal.

3. The asynchronous true four-phase handshake protocol circuit according to claim 2, wherein the third inverter has a driving capability of one eighth of that of the second inverter.

4. The asynchronous true four-phase handshake protocol circuit according to claim 1, wherein the second inverting means comprises a fourth inverter and a fifth inverter connected in parallel;

the input end of the fourth phase inverter is connected with the output end of the fifth phase inverter and the second node respectively, and the output end of the fourth phase inverter is connected with the input end of the fifth phase inverter and the second request signal respectively.

5. The asynchronous true four-phase handshake protocol circuit according to claim 4, wherein the fifth inverter has a driving capability of one eighth of that of the fourth inverter.

6. The asynchronous true four-phase handshake protocol circuit according to claim 1, wherein the first MOS transistor, the fourth MOS transistor and the fifth MOS transistor are PMOS transistors.

7. The asynchronous true four-phase handshake protocol circuit according to claim 1, wherein the second MOS transistor, the third MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are NMOS transistors.

8. A control method of an asynchronous true four-phase handshake protocol circuit, which is applied to the asynchronous true four-phase handshake protocol circuit according to any one of claims 1 to 7, the control method comprising:

in an initial state, setting the first request signal to be at a low level, setting the first response signal to be at a high level, and setting the second request signal to be at a low level;

when data is transmitted, the first request signal is changed from low level to high level, at the moment, the first node is changed to high level, the first response signal is changed to low level, and after the first response signal is changed to low level, the first request signal is reset to low level;

when the first request signal changes from high level to low level, the second node changes to low level, the second request signal changes to high level, and when the second request signal changes to high level, the first node changes to low level, the first response signal changes to high level, and data is correctly acquired;

and when the data is correctly acquired, setting the second request signal to be low level.

9. The method for controlling an asynchronous true four-phase handshake protocol circuit according to claim 8, wherein the second request signal is connected to a flip-flop, and the flip-flop captures data for transmission at a rising edge of the second request signal.

Technical Field

The invention relates to the field of electronic product design, in particular to an asynchronous true four-phase handshake protocol circuit and a control method thereof.

Background

In the applications of wearable electronics, medical electronics, wireless sensing nodes and the like, the power consumption of the system needs to be reduced for better endurance time of the system, and the asynchronous circuit does not need clock driving and only works when data arrives, so that the power consumption of the system can be effectively reduced.

A common bundled data asynchronous circuit structure is shown in fig. 1, and the delay of the delay chain is larger than the delay of the data path to ensure that the flip-flop can correctly capture data. In the conventional four-phase handshake protocol circuit, the controller captures data when receiving a rising edge of a previous-stage request signal, and therefore, the delay of the rising edge of the request signal transmitted by the delay chain needs to be greater than the delay of the data path. The delay of the falling edge of the delay chain transmission cannot be used for delay matching of the data path, and the working speed of the circuit is limited.

Disclosure of Invention

The invention aims to provide an asynchronous true four-phase handshake protocol circuit and a control method thereof, which can reduce the expense of a delay chain and improve the working speed of the circuit.

In order to achieve the purpose, the invention provides the following scheme:

an asynchronous true four-phase handshake protocol circuit, comprising:

the MOS transistor comprises a first phase inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first phase-inverting device and a second phase-inverting device;

the input end of the first phase inverter is connected with a first request signal, and the output end of the first phase inverter is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the first MOS tube and the source electrode of the fourth MOS tube are both connected with a working voltage end, and the drain electrode of the first MOS tube is connected with a first node; the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with a second request signal, and the source electrode of the third MOS tube and the source electrode of the eighth MOS tube are both connected with a common ground terminal; the grid electrode of the fourth MOS tube and the grid electrode of the seventh MOS tube are both connected with a second response signal, and the drain electrode of the fourth MOS tube is connected with the source electrode of the fifth MOS tube; the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are both connected with a second node, and the substrate of the fifth MOS tube and the substrate of the fourth MOS tube are connected with a working voltage end; the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are both connected with the first node, and the source electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube; the source electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube;

one end of the first inverting device is connected with the first node, and the other end of the first inverting device is connected with a first response signal; one end of the second inverting device is connected with the second node, and the other end of the second inverting device is connected with a second request signal.

Preferably, the first inverting means comprises a second inverter and a third inverter connected in parallel;

the input end of the second phase inverter is respectively connected with the output end of the third phase inverter and the first node, and the output end of the second phase inverter is respectively connected with the input end of the third phase inverter and the first response signal.

Preferably, the third inverter has a driving capability of one eighth of that of the second inverter.

Preferably, the second inverting means comprises a fourth inverter and a fifth inverter connected in parallel;

the input end of the fourth phase inverter is connected with the output end of the fifth phase inverter and the second node respectively, and the output end of the fourth phase inverter is connected with the input end of the fifth phase inverter and the second request signal respectively.

Preferably, the fifth inverter has a driving capability of one eighth of that of the fourth inverter.

Preferably, the first MOS transistor, the fourth MOS transistor and the fifth MOS transistor are PMOS transistors.

Preferably, the second MOS transistor, the third MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are all NMOS transistors.

A control method of an asynchronous true four-phase handshake protocol circuit is applied to the asynchronous true four-phase handshake protocol circuit, and comprises the following steps:

in an initial state, setting the first request signal to be at a low level, setting the first response signal to be at a high level, and setting the second request signal to be at a low level;

when data is transmitted, the first request signal is changed from low level to high level, at the moment, the first node is changed to high level, the first response signal is changed to low level, and after the first response signal is changed to low level, the first request signal is reset to low level;

when the first request signal changes from high level to low level, the second node changes to low level, the second request signal changes to high level, and when the second request signal changes to high level, the first node changes to low level, the first response signal changes to high level, and data is correctly acquired;

and when the data is correctly acquired, setting the second request signal to be low level.

Preferably, the second request signal is connected to a flip-flop, and the flip-flop captures data for transmission on a rising edge of the second request signal.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention provides an asynchronous true four-phase handshake protocol circuit and a control method thereof, wherein the asynchronous true four-phase handshake protocol circuit comprises the following steps: the MOS transistor comprises a first phase inverter, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first phase-inverting device and a second phase-inverting device; the input end of the first phase inverter is connected with a first request signal, and the output end of the first phase inverter is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the first MOS tube and the source electrode of the fourth MOS tube are both connected with a working voltage end, and the drain electrode of the first MOS tube is connected with a first node; the drain electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube; the grid electrode of the third MOS tube is connected with a second request signal, and the source electrode of the third MOS tube and the source electrode of the eighth MOS tube are both connected with a common ground terminal; the grid electrode of the fourth MOS tube and the grid electrode of the seventh MOS tube are both connected with a second response signal, and the drain electrode of the fourth MOS tube is connected with the source electrode of the fifth MOS tube; the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are both connected with a second node, and the substrate of the fifth MOS tube and the substrate of the fourth MOS tube are connected with a working voltage end; the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube are both connected with the first node, and the source electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube; the source electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube; one end of the first inverting device is connected with the first node, and the other end of the first inverting device is connected with a first response signal; one end of the second inverting device is connected with the second node, and the other end of the second inverting device is connected with a second request signal. According to the invention, only the response signal is replied when the rising edge of the request signal arrives, and the data is captured when the falling edge of the request signal arrives, so that the data transmission process comprises the transmission process of the rising edge and the falling edge of the request signal, and the correct capture of the data can be ensured only by ensuring that the sum of the transmission delay of the rising edge and the transmission delay of the falling edge of the request signal is greater than the transmission delay of the data path, therefore, the invention can reduce the cost of a delay chain and improve the working speed of a circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a diagram of a prior art bundled data asynchronous circuit;

FIG. 2 is a schematic diagram of a circuit structure of an asynchronous true four-phase handshake protocol according to an embodiment of the present invention;

fig. 3 is a flowchart of a control method of the asynchronous true four-phase handshake protocol circuit according to the present invention.

Description of the symbols:

m1-a first MOS transistor, M2-a second MOS transistor, M3-a third MOS transistor, M4-a fourth MOS transistor, M5-a fifth MOS transistor, M6-a sixth MOS transistor, M7-a seventh MOS transistor, M8-an eighth MOS transistor, INV 1-a first inverter, INV 2-a second inverter, INV 3-a third inverter, INV 4-a fourth inverter, NET 1-a first node, NET 2-a second node, Req _ L-a first request signal, Ack _ L-a first acknowledgement signal, Req _ R-a second request signal, Ack _ R-a second acknowledgement signal, VDD-a working voltage terminal, VSS-a common ground terminal.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide an asynchronous true four-phase handshake protocol circuit and a control method thereof, which can reduce the expense of a delay chain and improve the working speed of the circuit.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Fig. 2 is a schematic diagram of a structure of an asynchronous true four-phase handshake protocol circuit in an embodiment provided by the present invention, and as shown in fig. 2, the present invention provides an asynchronous true four-phase handshake protocol circuit and a control method thereof, including:

the transistor comprises a first inverter INV1, a first MOS transistor M1, a first MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first inverting device and a second inverting device.

An input end of the first inverter INV1 is connected to a first request signal Req _ L, and an output end of the first inverter INV1 is connected to a gate of the first MOS transistor M1, a gate of the first MOS transistor M2 and a gate of the eighth MOS transistor M8, respectively; the source electrode of the first MOS transistor M1 and the source electrode of the fourth MOS transistor M4 are both connected to a working voltage terminal VDD, and the drain electrode of the first MOS transistor M1 is connected to a first node NET 1; the drain electrode of the first MOS transistor M2 is connected with the drain electrode of the first MOS transistor M1, and the source electrode of the first MOS transistor M2 is connected with the drain electrode of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to a second request signal Req _ R, and the source of the third MOS transistor M3 and the source of the eighth MOS transistor M8 are both connected to a common ground terminal VSS; the gate of the fourth MOS transistor M4 and the gate of the seventh MOS transistor M7 are both connected to a second acknowledge signal Ack _ R, and the drain of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5; the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 are both connected to a second node NET2, and the substrate of the fifth MOS transistor M5 and the substrate of the fourth MOS transistor M4 are connected to a working voltage terminal VDD; the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6 are both connected to the first node NET1, and the source of the sixth MOS transistor M6 is connected to the drain of the seventh MOS transistor M7; the source of the seventh MOS transistor M7 is connected to the drain of the eighth MOS transistor M8.

One end of the first inverting device is connected with the first node NET1, and the other end of the first inverting device is connected with a first acknowledgement signal Ack _ L; one end of the second inverting device is connected to the second node NET2, and the other end of the second inverting device is connected to a second request signal Req _ R.

Preferably, the first inverting means includes a second inverter INV2 and a third inverter INV3 connected in parallel.

An input end of the second inverter INV2 is connected to an output end of the third inverter INV3 and the first node NET1, respectively, and an output end of the second inverter INV2 is connected to an input end of the third inverter INV3 and the first response signal Ack _ L, respectively.

Preferably, the driving capability of the third inverter INV3 is one eighth of that of the second inverter INV 2.

Preferably, the second inverting means includes a fourth inverter INV4 and a fifth inverter connected in parallel;

an input end of the fourth inverter INV4 is connected to an output end of the fifth inverter and the second node NET2, respectively, and an output end of the fourth inverter INV4 is connected to an input end of the fifth inverter and the second request signal Req _ R, respectively.

Preferably, the driving capability of the fifth inverter is one eighth of that of the fourth inverter INV 4.

Preferably, the first MOS transistor M1, the fourth MOS transistor M4, and the fifth MOS transistor M5 are PMOS transistors.

Preferably, the first MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8 are all NMOS transistors.

The basic working flow of the circuit is as follows: in the initial state, Req _ L is low, Ack _ L is high, Req _ R is low, and Ack _ R is high. When data arrives at the preceding stage, Req _ L goes high, M1 turns on, M2 turns off, NET1 goes high, and Ack _ L goes low. When receiving the low level of Ack _ L, the preceding stage sets Req _ L low, and when receiving the low level of the preceding stage Req _ L, M2 is turned on, M1 is turned off, M8 is turned on, and M6, M7 are already in the on state, so NET2 becomes low, and Req _ R becomes high. The Req _ R may be a clock signal of the flip-flop of the present stage, and captures data of the previous stage at a rising edge of the Req _ R to be transferred to the subsequent stage. After Req _ R goes high, M3 is turned on, NET1 is set low, and Ack _ L goes high, indicating that the data has been properly captured. The drive capacities of INV3 and INV5 are set weak, and are empirically designed to be the drive capacities 1/8 of INV2 and INV 4.

According to the work flow of the circuit, in the process of transmitting data from the previous stage to the current stage, the transmission of the rising edge of the request signal is carried out, and the transmission of the falling edge of the request signal is also carried out, so that the sum of the transmission delay of the rising edge and the transmission delay of the falling edge of the request signal can be matched with the data delay in the process of carrying out time sequence matching, and the expense of a delay chain is greatly reduced.

Fig. 3 is a flowchart of a control method of an asynchronous true four-phase handshake protocol circuit according to the present invention, and as shown in fig. 3, the control method of an asynchronous true four-phase handshake protocol circuit and a control method thereof according to the present invention is applied to an asynchronous true four-phase handshake protocol circuit and a control method thereof, and the control method includes:

step 100: in an initial state, the first request signal Req _ L is set to a low level, the first response signal Ack _ L is set to a high level, and the second request signal Req _ R is set to a low level;

step 200: when data is transmitted, the first request signal Req _ L is changed from low level to high level, at this time, the first node NET1 is changed to high level, the first acknowledgement signal Ack _ L is changed to low level, and after the first acknowledgement signal Ack _ L is changed to low level, the first request signal Req _ L is reset to low level;

step 300: when the first request signal Req _ L changes from high level to low level, the second node NET2 changes to low level, the second request signal Req _ R changes to high level, and when the second request signal Req _ R changes to high level, the first node NET1 changes to low level, the first response signal Ack _ L changes to high level, and data is correctly retrieved at this time;

step 400: when the data is correctly acquired, the second request signal Req _ R is set to a low level.

Preferably, the second request signal Req _ R is connected to a flip-flop, and the flip-flop captures data for transmission on a rising edge of the second request signal Req _ R.

The invention has the following beneficial effects:

in the invention, the circuit only replies a response signal after receiving the rising edge of the request signal, does not capture data, and captures data after receiving the falling edge of the request signal, so that the data transmission process experiences the transmission of the rising edge and the falling edge of the request signal, and the correct capture of the data can be ensured only by ensuring that the sum of the delay of the rising edge and the falling edge of the request signal is greater than the transmission delay of the data when the delay matching is carried out.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.