阅读说明：本技术 具有可控输出模式的运算放大器 (Operational amplifier with controllable output mode ) 是由 K·E·库提斯 W·布朗 J·沙赖斯 S·肯内利 D·苏达 H·周 C·罗杰斯 M·古 于 2019-06-19 设计创作，主要内容包括：本发明公开了一种运算放大器,该运算放大器具有图腾柱连接的输出晶体管,该输出晶体管具有耦接到多路复用器的输入以用于可选择地耦接该多路复用器的信号和电压电平。除了正常耦接该多路复用器的信号之外,该高输出晶体管和低输出晶体管可被迫硬导通或硬截止。该输出晶体管的操作可被动态地改变以仅传递正向信号、负向信号,被置于三态高阻抗状态,被硬连接到供电电压和/或被硬连接到供电公共回路。核心独立外围设备(CIP)也可耦接到该运算放大器以用于实时动态地改变该多路复用器输入,耦接到该多路复用器的控制的电路外部控制信号也可实时动态地改变该多路复用器输入。(An operational amplifier has a totem-pole connected output transistor having an input coupled to a multiplexer for selectively coupling a signal and a voltage level of the multiplexer. The high and low output transistors may be forced to be hard on or hard off in addition to the signal normally coupled to the multiplexer. The operation of the output transistor may be dynamically changed to pass only positive-going signals, negative-going signals, placed in a tri-state high impedance state, hardwired to a supply voltage and/or hardwired to a supply common loop. A Core Independent Peripheral (CIP) may also be coupled to the operational amplifier for dynamically changing the multiplexer input in real time, as well as a circuit external control signal coupled to the control of the multiplexer.)

1. An operational amplifier having a controllable output mode, the operational amplifier comprising:

a differential input transistor pair;

a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of a first output transistor;

a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor; and

a control circuit coupled to the first and second multiplexers for selecting the inputs of the first and second multiplexers.

2. The operational amplifier of claim 1, wherein the first output transistor and the second output transistor are totem-pole configured and have an output therebetween, wherein the first output transistor is coupled to the supply voltage and the second output transistor is coupled to the supply common loop.

3. The operational amplifier of any of claims 1-2, wherein the first output transistor is turned on hard when the first input of the first multiplexer is selected.

4. The operational amplifier of any of claims 1-3, wherein the first output transistor is controlled by the differential input transistor pair when the second input of the first multiplexer is selected.

5. The operational amplifier of any of claims 1-4, wherein the first output transistor is turned off when the third input of the first multiplexer is selected.

6. The operational amplifier of any of claims 1-5, wherein the second output transistor is turned off when the first input of the second multiplexer is selected.

7. The operational amplifier of any of claims 1-6, wherein the second output transistor is controlled by the differential input transistor pair when the second input of the second multiplexer is selected.

8. The operational amplifier of any of claims 1-7, wherein the second output transistor is turned on hard when the third input of the second multiplexer is selected.

9. The operational amplifier of any one of claims 1 to 8, further comprising an external connection to the control circuit to externally control the selection of the inputs of the first and second multiplexers.

10. The operational amplifier of any one of claims 1-9, further comprising a Core Independent Peripheral (CIP) coupled to the control circuit.

11. The operational amplifier of claim 10, wherein the CIP has an input coupled to an input of the differential input transistor pair for measuring a voltage thereon.

12. The operational amplifier of any one of claims 1 to 22, wherein the CIP has an input coupled to outputs of the first and second output transistors for measuring an output voltage therefrom.

13. A circuit for at least partially tracking an input signal, the circuit comprising:

a differential input transistor pair having inputs coupled to a signal;

a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of a first output transistor;

a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor;

the first output transistor and the second output transistor are configured totem-pole with an output therebetween, wherein the first output transistor is coupled to the supply voltage and the second output transistor is coupled to the supply common; and

a control circuit coupled to the first and second multiplexers for selecting the inputs of the first and second multiplexers;

wherein selection of a particular combination of the first multiplexer input and the second multiplexer input determines which portion of the signal is tracked.

14. The circuit of claim 13, wherein a positive input voltage amplitude tracking circuit is configured when the second input of the first multiplexer and the first input of the second multiplexer are selected.

15. The circuit of any of claims 13-14, wherein a negative input voltage amplitude tracking circuit is configured when the third input of the first multiplexer and the second input of the second multiplexer are selected.

16. The circuit of any of claims 13 to 15, wherein the positive input voltage track and hold circuit comprises:

a capacitor coupled between the outputs of the first and second output transistors and the supply common;

selecting the second input of the first multiplexer; and is

Selecting the first input of the second multiplexer;

whereby the capacitor is charged when the voltage input of the differential input transistor pair is positive.

17. The circuit of claim 16, wherein the capacitor is discharged when the third input of the first multiplexer and the third input of the second multiplexer are selected.

18. The circuit of any of claims 13 to 17, wherein the negative voltage track and hold circuit comprises:

a capacitor coupled between the outputs of the first and second output transistors and the supply voltage;

selecting the third input of the first multiplexer; and is

Selecting the second input of the second multiplexer;

whereby the capacitor is charged when the voltage input of the differential input transistor pair is negative.

19. The circuit of claim 18, wherein the capacitor is discharged when the first input of the first multiplexer and the first input of the second multiplexer are selected.

20. The circuit of any of claims 13 to 20, wherein the maximum and minimum DC amplitude track and hold circuits comprise:

a capacitor coupled between the outputs of the first and second output transistors and the supply common,

when the second input of the first multiplexer and the first input of the second multiplexer are selected and the voltage input of the differential input transistor pair is positive, the capacitor is charged, and

the capacitor is discharged when the third input of the first multiplexer and the second input of the second multiplexer are selected and the voltage input of the differential input transistor pair is negative.

21. The circuit of claim 20, wherein a control circuit is coupled to the first multiplexer and the second multiplexer and controls the selection of the first multiplexer input and the second multiplexer input.

22. A method for configuring operation of an operational amplifier output, the method comprising the steps of:

providing a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of the first output transistor;

providing a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor; and

selecting inputs of the first and second multiplexers to configure operation of the first and second output transistors.

23. The method of claim 22, further comprising the step of selecting the inputs of the first and second multiplexers by a Core Independent Peripheral (CIP).

24. A circuit for at least partially tracking an input signal, the circuit comprising:

any one of the operational amplifiers of claims 1-12;

wherein:

the differential input transistor pair includes an input coupled to a signal;

the circuit further comprises a control circuit coupled to the first and second multiplexers for selecting the inputs of the first and second multiplexers; and is

The selection of a particular combination of the first multiplexer input and the second multiplexer input is configured to determine which portion of the signal is tracked.

25. A method of operating an operational amplifier, the method comprising operating any one of the operational amplifiers of claims 1-12.

Technical Field

The present disclosure relates to operational amplifiers, and more particularly, to operational amplifiers having controllable output modes.

Background

AC coupled waveforms typically require DC level restoration for processing. In order to achieve such detection of the minimum value and the maximum value, the voltage of the signal waveform needs to generate an offset. The circuit may be used to track in real time the minimum or maximum voltage amplitude value of the signal waveform and provide that voltage level to the DC level recovery circuit. Typically, this tracking is achieved using an operational amplifier and an external diode/transistor, as shown in fig. 1a and 1 b.

Known designs use external diodes/transistors to convert the totem-pole output of the operational amplifier into only high-side/low-side drivers. This has two problems, the forward bias voltage of the diode/transistor reduces the common mode range, and the inability to dynamically control the output configuration limits the design to the selected circuit layout option. Furthermore, an external switch is required to reset the operational amplifier output and/or to perform output signal blanking, as shown in fig. 2a and 2 b.

Disclosure of Invention

Accordingly, there is a need for a method of tracking maximum and/or minimum waveform amplitudes in real time with an increased common mode range and without the need for external diodes and/or switches coupled to the peak detect operational amplifier.

According to an embodiment, an operational amplifier having a controllable output mode may include: a differential input transistor pair; a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of a first output transistor; a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor; and a control circuit coupled to the first multiplexer and the second multiplexer for selecting the inputs of the first multiplexer and the second multiplexer.

According to another embodiment, the first output transistor and the second output transistor may be totem pole configured and have an output therebetween, wherein the first output transistor may be coupled to the supply voltage and the second output transistor may be coupled to the supply common. According to another embodiment, the first output transistor may be turned on hard when the first input of the first multiplexer may be selected. According to another embodiment, the first output transistor may be controlled by the differential input transistor pair when the second input of the first multiplexer may be selected. According to another embodiment, the first output transistor may be turned off when the third input of the first multiplexer may be selected. According to another embodiment, the second output transistor may be turned off when the first input of the second multiplexer may be selected. According to another embodiment, the second output transistor may be controlled by the differential input transistor pair when the second input of the second multiplexer may be selected. According to another embodiment, the second output transistor may be turned on hard when the third input of the second multiplexer may be selected.

According to another embodiment, an external connection to the control circuit may be used to externally control the selection of the inputs of the first and second multiplexers. According to another embodiment, a Core Independent Peripheral (CIP) may be coupled to the control circuit. According to another embodiment, the CIP may have an input coupled to the inputs of the differential input transistor pair for measuring a voltage thereon. According to another embodiment, the CIP may have an input coupled to the outputs of the first and second output transistors for measuring an output voltage therefrom.

According to another embodiment, a circuit for at least partially tracking an input signal may comprise: a differential input transistor pair having inputs coupled to a signal; a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of a first output transistor; a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor; the first output transistor and the second output transistor may be totem pole configured and have an output therebetween, wherein the first output transistor may be coupled to the supply voltage and the second output transistor may be coupled to the supply common; and a control circuit coupled to the first and second multiplexers for selecting the inputs of the first and second multiplexers; wherein the selection of a particular combination of the first multiplexer input and the second multiplexer input determines which portion of the signal can be tracked.

According to another embodiment, a positive input voltage amplitude tracking circuit may be configured when the second input of the first multiplexer and the first input of the second multiplexer may be selected. According to another embodiment, a negative input voltage amplitude tracking circuit may be configured when the third input of the first multiplexer and the second input of the second multiplexer may be selected.

According to another embodiment, a positive input voltage track and hold circuit may comprise: a capacitor coupled between the outputs of the first and second output transistors and the supply common; the second input of the first multiplexer may be selected; and the first input of the second multiplexer is selectable; whereby the capacitor may be charged when the voltage input of the differential input transistor pair may be positive. According to another embodiment, the capacitor may be discharged when the third input of the first multiplexer and the third input of the second multiplexer may be selected.

According to another embodiment, a negative voltage track and hold circuit may comprise: a capacitor coupled between the outputs of the first and second output transistors and the supply voltage; the third input of the first multiplexer may be selected; and the second input of the second multiplexer is selectable; whereby the capacitor may be charged when the voltage input of the differential input transistor pair may be negative. According to another embodiment, the capacitor may be discharged when the first input of the first multiplexer and the first input of the second multiplexer may be selected.

According to another embodiment, the maximum and minimum DC amplitude track and hold circuits may comprise: a capacitor may be coupled between the outputs of the first and second output transistors and the supply common, the capacitor may be charged when the second input of the first multiplexer and the first input of the second multiplexer may be selected and a voltage input of the differential input transistor pair may be positive, and the capacitor may be discharged when the third input of the first multiplexer and the second input of the second multiplexer may be selected and the voltage input of the differential input transistor pair may be negative. According to another embodiment, a control circuit may be coupled to the first multiplexer and the second multiplexer and control selection of the first multiplexer input and the second multiplexer input.

According to yet another embodiment, a method for configuring operation of an operational amplifier output may comprise the steps of: providing a first multiplexer having a first input coupled to a supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to a supply common, and an output coupled to an input of the first output transistor; providing a second multiplexer having a first input coupled to the supply voltage, a second input coupled to the differential input transistor pair, a third input coupled to the supply common, and an output coupled to an input of a second output transistor; and selecting inputs of the first multiplexer and the second multiplexer to configure operation of the first output transistor and the second output transistor. According to another embodiment of the method, the step of selecting the inputs of the first multiplexer and the second multiplexer may be done by a Core Independent Peripheral (CIP).

Drawings

A more complete understanding of the present disclosure may be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a prior art schematic and waveform diagram of maximum and minimum DC amplitude tracking circuits including operational amplifiers and diodes/transistors in the output path;

FIG. 2 shows a prior art schematic of a maximum and minimum DC amplitude detection circuit with reset including an operational amplifier, diodes/transistors and switches in the output path;

FIG. 3 shows a schematic diagram of a typical operational amplifier;

FIG. 4 shows a schematic diagram of an operational amplifier with a controllable output mode, according to a specific example embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram and waveform diagram of maximum and minimum DC amplitude tracking circuits, according to certain exemplary embodiments of the present disclosure;

FIG. 6 illustrates a schematic diagram and waveform diagram of maximum and minimum DC amplitude track and hold circuits with reset capability, according to certain exemplary embodiments of the present disclosure;

FIG. 7 illustrates a schematic diagram and waveform diagram of maximum and minimum DC amplitude track and hold circuits with directional control, according to certain exemplary embodiments of the present disclosure; and is

Fig. 8 illustrates a schematic diagram of the operational amplifier and core independent peripherals shown in fig. 4, according to a specific example embodiment of the present disclosure.

While the disclosure is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific exemplary embodiments is not intended to limit the disclosure to the forms disclosed herein.

Detailed Description

Embodiments of the present disclosure may include a device having an operational amplifier and a multiplexer to control its output configuration. This embodiment, in accordance with the teachings of the present disclosure, does not require an external device for maximum or minimum peak waveform detection, and has the added advantage that its output can be tri-stated (switched to high impedance) to achieve output blanking in the event of fast transient noise.

The operational amplifier may have multiple output modes; for example, in particular, the high-side driver is disabled (off), the low-side driver is disabled (off), the high-side output transistor is continuously conducting to the rail voltage, and the low-side output transistor is continuously conducting to common or tri-state. The operational amplifier may become a peak (maximum) track-and-hold amplifier if the low-side transistor is driven off. If the high-side transistor is driven off, the operational amplifier can become a minimum amplitude tracking and holding amplifier. Because the op-amp configuration control can be implemented as a Core Independent Peripheral (CIP), external logic can dynamically control both high and low drivers for peak/minimum hold with noise blanking.

Core Independent Peripherals (CIPs) handle tasks without code or supervision at a Central Processing Unit (CPU), e.g., a Microcontroller Core Unit (MCU), once initialized in the system, CIP may provide steady-state closed-loop embedded control with zero intervention by the MCU's core, then the CPU may idle or enter a sleep mode to save system power, CIP may be, for example, but not limited to, a configurable operational amplifier, a digitally controlled oscillator (NCO), a configurable logic unit (CLC), an analog-to-digital converter (ADC) with a state machine that does not require the CPU to transmit converted data, a Pulse Width Modulator (PWM), a Cyclic Redundancy Check (CRC), a mathematical accelerator, a programmable switch mode controller, a watchdog timer, an angle timer, a Complementary Waveform Generator (CWG), or a timer.https://www.microchip.com/design-centers/8- bit/peripherals/core-independentProvide more information about its CIP.

The preferred embodiments disclosed herein simplify peak/minimum tracking and holding implementations of Automatic Gain Control (AGC) systems, DC level restoration and peak hold systems, which may include, but are not limited to, integrated circuit functions requiring only external capacitors and/or resistors.

Preferred embodiments of the present disclosure may include an operational amplifier CIP peripheral having the ability to disable a high side output driver and/or a low side driver using either software and/or the connection of two internal CIPs with a timer/configurable logic unit (CLC).

Only one component (e.g., a resistor or capacitor) needs to be coupled with the operational amplifier and the output mode selection of the operational amplifier can be dynamically changed based on internal digital controls. This also eliminates the need for the output switch to implement a noise blanking function.

Referring now to the drawings, the details of exemplary embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

Referring to fig. 1(a) and 1(b), prior art schematic and waveform diagrams of maximum and minimum DC amplitude tracking circuits including operational amplifiers and diodes/transistors in the output path are depicted. The operational amplifier with output diode shown in fig. 1(a) is a maximum amplitude waveform tracker and will provide a forward input voltage at its output referenced to a common voltage potential. The operational amplifier with output diode shown in fig. 1(b) is a minimum amplitude waveform tracker and will provide a negative input voltage at its output referenced to a + V (e.g., 5vdc) voltage potential.

Referring to fig. 2(a) and 2(b), prior art schematic diagrams of maximum and minimum DC detection circuits with reset including operational amplifiers, diodes/transistors and switches in the output path are depicted. An external switch is necessary to perform the reset function. The operational amplifier with output diode, capacitor and reset switch shown in fig. 2(a) is a maximum (peak) amplitude waveform detector and will provide a forward input voltage at its output referenced to the common voltage potential. The capacitor charges up to the maximum (peak) amplitude of the input waveform and will hold that maximum amplitude voltage until discharged by the switch shorting it to the common voltage potential. The operational amplifier with output diode, capacitor and reset switch shown in fig. 2(b) is a minimum amplitude waveform detector and will provide a negative input voltage at its output referenced to a + V (e.g., 5vdc) voltage potential. The capacitor charges up to the minimum amplitude of the input waveform and will hold that minimum amplitude voltage until discharged by the switch shorting it to the + V voltage potential.

Referring to fig. 3, a schematic diagram of a typical operational amplifier is depicted. The operational amplifier shown in fig. 3 may include differentially connected input transistors 302 and 304 and totem-pole connected single-ended output transistors 306 and 308. The operational amplifier may amplify the difference between the input voltages Vin + and Vin-and output the voltage difference as Vout (with or without amplification).

Referring to fig. 4, a schematic diagram of an operational amplifier with a controllable output mode is depicted, according to a specific example embodiment of the present disclosure. An operational amplifier having a controllable output mode, generally indicated by the numeral 400, may be adapted for maximum and minimum peak voltage detection, tracking and hold output modes. Operational amplifier 400 may include differential input transistors 402 and 404, multiplexers 410 and 412, control circuitry 414, totem-pole coupled output transistors 406 and 408, and other operational amplifier circuit components. Multiplexer 410 may be used to select what signal or voltage is provided to the base/gate of transistor 406 and multiplexer 412 may be used to select what signal or voltage is provided to the base/gate of transistor 408. Control lines (two signals each) are used to couple control circuit 414 to multiplexers 410 and 412 for its input selection. By inputting to Ext (e.g. I)²C. SPI, etc.) to apply external control commands, the output of operational amplifier 400 may be configured as desired. Exemplary output configurations are described in table I below. Transistors 406 and 408 are shown in fig. 4 as bipolar junction transistors, however, metal oxide field effect transistors MOSFETs may be used equally effectively, with the drain substantially equivalent to the collector, the gate substantially equivalent to the base, and the source substantially equivalent to the emitter.

When the input a of multiplexer 410 is selected, then transistor 406 is turned on hard and Vout is forced to + V. When the input b of the multiplexer 410 is selected, then the output of transistor 406 will be controlled by the differential input Vin, and Vout will follow Vin, as in the operational amplifier of fig. 3, unless transistor 408 is turned hard on (selecting input f of multiplexer 412). When the input c of the multiplexer 410 is selected, then the transistor 406 will remain off.

When the input d of the multiplexer 412 is selected, then the transistor 408 will remain off. When the input e of the multiplexer 412 is selected, the output of the transistor 408 will be controlled by the differential input Vin, and Vout will follow Vin, as in the operational amplifier of fig. 3, unless the transistor 406 is turned on hard (selecting input a of the multiplexer 410). When the input f of the multiplexer 412 is selected, then the transistor 408 is turned on hard and Vout is forced to the common voltage potential.

In order to set the output of the operational amplifier 400 to a high impedance state (tri-state), the following configuration may be used. When input c of multiplexer 410 is selected, transistor 406 will be off, and when input d of multiplexer 412 is selected, transistor 408 will be off, placing the junction (Vout) between transistors 406 and 408 in a high impedance state. Various combinations of inputs a-f may be used to perform high or low reset, output signal blanking, tri-state, open collector/drain, open emitter/source, and totem pole output of operational amplifier 400, as described in table I below.

Referring to table I below, a table summary of output configurations based on the multiplexer input selection of the operational amplifier circuit shown in fig. 4 is depicted, according to certain exemplary embodiments of the present disclosure. Using appropriate control signals from control circuitry 414, the combined input of multiplexer 410 selects input a, b, or c; and inputs d, e, or f of multiplexer 412 may be selected (in response to an internal or external command) to produce operation of operational amplifier 400 having outputs configured as, but not limited to, those listed in table I below.

TABLE I

Output deviceDevice for placing	Multiplexer input selection
		Hi-Z tri-state (output transistor off)	Multiplexer 410(c), multiplexer 412(d)
Totem pole output	Multiplexer 410(b), multiplexer 412(e)
		Open collector/drain	Multiplexer 410(c), multiplexer 412(e)
Open emitter/source	Multiplexer 410(b), multiplexer 412(d)
		Common circuit for forcing output to supply power	Multiplexer 410(c), multiplexer 412(f)
Forcing the output to the supply voltage	Multiplexer 410(a), multiplexer 412(d)

Referring to fig. 5(a) and 5(b), schematic and waveform diagrams of maximum and minimum DC amplitude tracking circuits according to certain exemplary embodiments of the present disclosure are depicted. The circuits shown in fig. 5(a) and 5(b) utilize an operational amplifier 400 having a controllable output mode, as described more fully above. The circuit of fig. 5(a) may be used as a maximum amplitude waveform tracker by selecting (see fig. 4) the b input of multiplexer 410 and the d input of multiplexer 412. This configuration effectively allows the output (Vout) of transistor 406 to follow the positive drift (extension) of the input Vin, where the output Vout is additionally pulled to the common voltage potential (ground) through a resistor coupled between the output and the common voltage potential, since transistor 408 remains off in response to the selected d-input.

The circuit of fig. 5(b) may be used as a minimum amplitude tracker by selecting (see fig. 4) the c input of multiplexer 410 and the e input of multiplexer 412. This configuration effectively allows the output (Vout) of transistor 408 to follow the negative drift of the input Vin, where the output Vout is additionally pulled to + V through a resistor coupled between the output and + V, since transistor 406 remains off in response to the selected c-input.

Referring to fig. 6(a) and 6(b), schematic and waveform diagrams of maximum and minimum DC amplitude track and hold circuits with reset capability are depicted, according to certain exemplary embodiments of the present disclosure. The circuits shown in fig. 6(a) and 6(b) utilize an operational amplifier 400 having a controllable output mode, as described more fully above. The operational amplifier circuit of fig. 6(a) may be used as a maximum amplitude track and hold circuit by selecting (see fig. 4) the b input of multiplexer 410 and the d input of multiplexer 412. This configuration effectively allows the output (Vout) of transistor 406 to follow the positive drift of the input Vin and charge a capacitor coupled between the output and the common voltage potential. Transistor 408 remains off in response to the selected d input. The voltage on the capacitor may be discharged by selecting the c input of multiplexer 410 and the f input of multiplexer 412.

The circuit of fig. 6(b) may be used as a minimum amplitude track and hold circuit by selecting (see fig. 4) the c input of multiplexer 410 and the e input of multiplexer 412. This configuration effectively allows the output (Vout) of transistor 408 to follow the negative drift of the input Vin and charge the capacitor coupled between the output and + V. The voltage on the capacitor may be discharged by selecting the a input of multiplexer 410 to pull Vout up to + V (5 volts) via transistor 406, and selecting the d input of multiplexer 412 to set transistor 408 to off.

Referring to fig. 7, a schematic diagram and waveform diagram of maximum and minimum DC amplitude track and hold circuits with directional control are depicted, according to certain exemplary embodiments of the present disclosure. The operational amplifier configuration shown in fig. 8 may be used to charge a capacitor coupled between the output and the common voltage potential during the positive half cycle, and the capacitor may be discharged during the negative half cycle. The capacitor may be charged during the positive input voltage half cycle by selecting input b of multiplexer 410 and input d of multiplexer 412. The capacitor may be discharged during the negative half cycle by selecting input c of multiplexer 410 and input e of multiplexer 412. This control may be implemented using a directional control signal (Dir) to change the input selection of multiplexers 410 and 412. The directional control signal at the input Dir may be controlled, for example, with a timer (not shown) configured for the period of the input waveform and/or a voltage comparator (not shown) measuring the input voltage.

Fig. 8 illustrates a schematic diagram of the operational amplifier 400 and core independent peripherals illustrated in fig. 4, according to a specific example embodiment of the present disclosure. Core Independent Peripheral (CIP)416 may be coupled to the operational amplifier 400 shown in fig. 4. The CIP 416 may include at least one or more voltage comparators, configurable logic units (CLC), voltage references, analog-to-digital converters (ADCs), adders, subtractors, multipliers, dividers, registers, and the like. The CIP 416 may provide control signals to the control circuitry 414 based on the voltage input Vin + and/or Vin-, the voltage output Vout, and/or external control signals from an external port (Ext).

The output of the preferred implementation of operational amplifier 400 disclosed herein may be placed in a high impedance tri-state mode by selecting input c of multiplexer 410 and input d of multiplexer 412. A tri-state mode may be used for output signal blanking. Resetting to the common voltage potential may be accomplished by selecting input c of multiplexer 410 and input f of multiplexer 412. Resetting to + V may be accomplished by selecting input a of multiplexer 410 and input d of multiplexer 412. These various multiplexer input combinations may be selected by an external control signal (Ext node) to the control circuit 414, which may also be provided from the CIP 416. It is contemplated and within the scope of this disclosure that the supply common potential may be a negative supply voltage or a power supply common.

The present disclosure has been described in terms of one or more embodiments, and it is to be understood that many equivalents, alternatives, variations, and modifications, in addition to those expressly stated, are possible and are within the scope of the present disclosure. While the disclosure is susceptible to various modifications and alternative forms, specific exemplary embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific exemplary embodiments is not intended to limit the disclosure to the particular forms disclosed herein.