阅读说明：本技术 一种电解质突触晶体管及其制备方法和应用 (Electrolyte synaptic transistor and preparation method and application thereof ) 是由 鲁统部 姚镔玮 陈旭东 于 2021-01-04 设计创作，主要内容包括：本发明公开了一种电解质突触晶体管及其制备方法和应用,包括导电沟道和位于所述导电沟道上的石墨炔层,所述石墨炔层上覆盖有电解质。本发明在沟道和电解质之间设置石墨炔层作为浮栅存储层,电解质作为栅极,可阻隔固电解质中的离子与导电沟道接触,避免了离子在沟道中频繁插入/脱离,从而对沟道的晶格结构进行有效保护,使器件具有很好的循环稳定性。同时,本发明的电解质突触晶体管具有非易失性特性,成功模拟了各种具有代表性的突触特性,且在弯曲测试中表现出优异的稳定性和可靠性。(The invention discloses an electrolyte synapse transistor and a preparation method and application thereof. According to the invention, the graphite alkyne layer is arranged between the channel and the electrolyte to serve as a floating gate storage layer, the electrolyte serves as a grid, ions in the solid electrolyte can be prevented from contacting with the conducting channel, and the ions are prevented from being frequently inserted into or separated from the channel, so that the lattice structure of the channel is effectively protected, and the device has good circulation stability. Meanwhile, the electrolyte synaptic transistor has nonvolatile characteristics, successfully simulates various representative synaptic characteristics, and shows excellent stability and reliability in bending test.)

1. An electrolyte synapse transistor, comprising: the conductive device comprises a conductive channel and a graphite alkyne layer positioned on the conductive channel, wherein an electrolyte is covered on the graphite alkyne layer.

2. The electrolytic synapse transistor of claim 1, wherein: the electrolyte synaptic transistor also comprises a source electrode, a drain electrode and a side gate electrode which are positioned on the conductive channel, and the conductive channel, the source electrode, the drain electrode and the side gate electrode form a plane three-terminal synaptic transistor; the source electrode and the drain electrode are respectively positioned on two sides of the graphite alkyne layer, and the side gate electrode is covered with electrolyte.

3. The electrolytic synapse transistor of claim 1, wherein: the electrolyte is an organic electrolyte, and comprises an organic carrier and lithium salt, wherein the organic carrier is electrically insulated from the lithium salt.

4. The electrolytic synapse transistor of claim 3, wherein: the lithium salt comprises at least one of lithium perchlorate, lithium carbonate and lithium iron phosphate.

5. The electrolytic synapse transistor of claim 3, wherein: the organic carrier comprises at least one of polyethylene oxide and polyetherimide.

6. The electrolytic synapse transistor of claim 1, wherein: the conductive channel is a two-dimensional semiconductor material.

7. The electrolytic synapse transistor of claim 6, wherein: the two-dimensional semiconductor material comprises at least one of molybdenum disulfide, molybdenum selenide, tungsten diselenide, tungsten disulfide, nickel phosphorus trisulfide, nickel phosphorus triselenide and black phosphorus.

8. A method of fabricating an electrolyte synaptic transistor according to any one of claims 2-7, wherein: the method comprises the following steps:

(1) preparing a source electrode, a drain electrode and a side gate electrode on the conductive channel;

(2) manufacturing a graphite alkyne layer on the surfaces of the conductive channels outside the source electrode, the drain electrode and the side gate electrode;

(3) and (3) covering the side gate electrode and the channel region of the sample obtained in the step (2) with an electrolyte.

9. The method of fabricating an electrolytic synapse transistor of claim 8, wherein: in the step (3), the method for covering the electrolyte is to cover the surface of the sample obtained in the step (2) with photoresist, expose the channel region and a part of the side gate electrode by using a photolithography technique, then coat the side gate electrode and the channel region with an ionic liquid, and dry to form a solid electrolyte.

10. Use of an electrolyte synaptic transistor according to any one of claims 1 to 7 in the manufacture of a neuromorphic device and/or a wearable device.

Technical Field

The invention belongs to the technical field of artificial synapses, and particularly relates to an electrolyte synapse transistor and a preparation method and application thereof.

Background

For the last 50 years, transistor dimensions and process innovations have followed moore's law, which is the gold law developed by the integrated circuit industry. In order to improve the performance of the device, a great deal of innovation has been made on the semiconductor process, such as strained silicon, high-K gate dielectric, metal gate, three-terminal field effect transistor structure, etc. These methods of constructing devices are very complex processes. When the size of the device is less than 100nm or less, a large increase in power consumption is caused due to a short channel effect. In order to overcome the problems of failure of Moore's law, large-scale integration and manufacturing cost, the innovation of the device manufacturing process and the integration technology is more and more emphasized by people, and becomes an important front edge of the microelectronic field in the post Moore's era. The lines of development of microelectronic device technology were redefined after 2016. In addition, cmos devices are listed as a key research and development area in the international semiconductor roadmap. Based on the route, by exploring new electronic materials and new devices based on working principles, ultrahigh performance and ultralow power consumption can be realized.

The traditional computer is an integrated circuit taking a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as a core device, lays a foundation for the modern information society, and proves technical innovation in various fields. However, given the physical separation of memory and Central Processing Units (CPUs) in architecture, conventional computers present significant challenges in the processing of large amounts of data, known as the "von neumann" bottleneck. In the era of big data, the bottleneck becomes particularly prominent when the wide-range application of the internet of things is common. The human brain is a system with high parallel computation and self-adaptive learning capability, and in order to solve the bottleneck limit of von Neumann, people put forward an artificial neural network to achieve the purpose of parallel computation and obtain a series of breakthrough achievements. However, the algorithms and related software of the artificial neural network still run on a conventional computer, resulting in problems of limited computing power, low efficiency and the like. Such as AlphaGo implemented by 1200 Central Processing Units (CPUs) and 180 image processors (GPUs), consumes up to several tens of watts.

Neuromorphic computations that mimic the development of the human brain have received attention in recent years because they can process large amounts of unstructured information in parallel in an efficient and energy-efficient manner. In the past few years, various artificial synapse devices, such as two-terminal-structured memristors and multi-terminal-structured neuromorphic transistors, have been used to construct hardware artificial neural networks for neuromorphic computations. Particularly, the ion-gated synaptic transistor for regulating the channel conductance state by using the electrolyte shows good linearity and symmetry in the aspect of weight updating, has extremely low switching voltage and long retention time, and realizes near-ideal identification precision under the condition of ultralow energy consumption. However, these devices are susceptible to degradation after multiple cycles.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art described above. To this end, the present invention proposes an electrolyte synapse transistor with good stability.

The invention also provides a preparation method and application of the electrolyte synaptic transistor.

According to a first aspect of the invention, an electrolyte synapse transistor is provided comprising a conductive channel and a graphitic alkyne layer on said conductive channel, said graphitic alkyne layer being covered with an electrolyte.

According to the first aspect of the present invention, the present invention has at least the following advantageous effects:

in related art synaptic transistors, ions in the electrolyte are directly inserted into the conductive channel, and the ions are frequently inserted/extracted between the electrolyte and the conductive channel, which inevitably destroys the lattice structure of the conductive channel, resulting in irreversible performance degradation of the device after many cycles. According to the invention, the graphite alkyne layer is arranged between the conductive channel and the electrolyte to serve as a floating gate storage layer, the electrolyte serves as a grid electrode, and ions in the solid electrolyte can be prevented from contacting with the conductive channel, so that the ions are prevented from being frequently inserted into or separated from the channel, the lattice structure of the channel is effectively protected, and the device has good stability. Whilst the graphoyne is an sp and sp²The two-dimensional carbon allotrope formed by hybridized carbon atoms has unique advantages on the storage and diffusion of conductive metal ions, particularly lithium ions. Wherein the uniform distribution of sp carbon atoms provides sufficient space for the storage of metal ions, such that the metal ions have a very high storage ratio, in particular such that the storage ratio of lithium ions is up to 1:3 (i.e. LiC)₃) Is commonly used graphite (LiC)₆₎Twice as much. In addition, the large pores (0.542nm) and wider layer spacing (0.365nm) of graphdine allow for low barriers (0.17eV to 0.84eV) for in-plane and out-of-plane diffusion of lithium ions.

In some embodiments of the present invention, the thickness of the conductive channel and the graphdine layer may be adjusted and set according to specific device structure and operating environment requirements.

In some embodiments of the present invention, the thickness of the conductive channel may be set to 1 to 10nm, for example, to about 4 nm; the thickness of the graphoyne layer may be set to 2 to 15nm, for example, to about 7 nm.

In some embodiments of the invention, the electrolyte synaptic transistor further comprises a source electrode, a drain electrode, and a side gate electrode on the conductive channel, source electrode, drain electrode, and side gate electrode comprising a planar three-terminal type synaptic transistor; the source electrode and the drain electrode are respectively positioned on two sides of the graphite alkyne layer, and the side gate electrode is covered with electrolyte.

In some embodiments of the present invention, the source electrode, the drain electrode and the side gate electrode are independently made of common metal electrode materials, including but not limited to Au/Pd, Au/Ti, Au/Cr, Au/Sc, Pt/Ti, Pd. The thickness of the electrode can also be adjusted and set according to the requirements of specific device structures and working environments.

In some embodiments of the invention, the source electrode, the drain electrode and the side gate electrode are all Au/Cr materials, wherein Cr is in contact with molybdenum disulfide and Au is coated on Cr. The thickness of Cr may be set to 1 to 10nm, for example, about 5 nm. The thickness of the Au may be set to 10 to 100nm, for example, about 50 nm.

In some embodiments of the invention, the electrolyte is an organic electrolyte comprising an organic carrier that is electronically insulating and a lithium salt, wherein the lithium salt provides mobile lithium ions.

In some embodiments of the present invention, the ratio of the organic carrier to the lithium salt is not limited. In some preferred embodiments, however, the mass ratio of the organic carrier to the lithium salt is 4-5: 1. In some embodiments, the mass ratio of the organic carrier to the lithium salt is about 3: 1.

In some embodiments of the invention, the lithium salt comprises at least one of lithium perchlorate, lithium carbonate, lithium iron phosphate.

In some embodiments of the invention, the lithium salt comprises lithium perchlorate.

In some embodiments of the invention, the organic carrier is an organic high molecular polymer, such as polyethylene oxide, polyetherimide, or the like.

In some embodiments of the present invention, the conductive channel is a two-dimensional semiconductor material.

In some embodiments of the invention, the two-dimensional semiconductor material comprises at least one of molybdenum disulfide, molybdenum selenide, tungsten diselenide, tungsten disulfide, nickel phosphorous trisulfide, nickel phosphorous triselenide, black phosphorus.

In some embodiments of the invention, the two-dimensional semiconductor material is molybdenum disulfide.

In some embodiments of the invention, the electrolyte synapse transistor further comprises an insulating substrate, the conductive channel being located on the insulating substrate.

In some embodiments of the invention, the insulating substrate comprises PET, SiO₂At least one of/Si, glass and quartz.

In some embodiments of the invention, the insulating substrate is PET. The electrolyte synapse transistor can be made into a flexible device using PET as an insulating substrate.

According to a second aspect of the present invention, a method for preparing an electrolyte synapse transistor is provided, comprising the steps of:

(1) preparing a source electrode, a drain electrode and a side gate electrode on the conductive channel;

(2) manufacturing a graphite alkyne layer on the surfaces of the conductive channels outside the source electrode, the drain electrode and the side gate electrode;

(3) and (3) covering the side gate electrode and the channel region of the sample obtained in the step (2) with an electrolyte.

In some embodiments of the inventionIn the step (3), the step of covering the electrolyte is to cover the surface of the sample obtained in the step (2) with a photoresist, expose the channel region (the channel region refers to the region between the source electrode, the drain electrode and the side gate electrode, in this application, specifically the region on the surface of the graphite alkyne layer) and a part of the side gate electrode by using a photolithography technique, then coat the ion liquid on the side gate electrode and the channel region, and dry to form a solid electrolyte. And opening windows on the channel material and the side gate electrode by using a photoetching technology, so that the organic electrolyte is only contacted with the channel region and the side gate electrode. Because of the insulativity of the photoresist, the source-drain voltage is greatly reduced for Li in the organic electrolyte⁺The effect of migration.

According to a third aspect of the invention, the use of the above-described electrolyte synapse transistor in the manufacture of a neuromorphic device and/or a wearable apparatus is proposed.

Compared with the prior art, the invention has the following beneficial effects:

(1) in the electrolyte synapse transistor, the solid electrolyte is not in direct contact with the conductive channel, so that frequent insertion/separation of ions in the conductive channel is avoided, the lattice structure of the conductive channel is protected, and the electrolyte synapse transistor has good stability.

(2) The programming voltage pulse of the electrolyte synapse transistor is 3V, which is far smaller than the programming voltage used in a three-terminal memory, and the power consumption is lower; and has good on/off characteristics and long retention time; meanwhile, the quantity of lithium ions embedded in the graphdiyne can be accurately regulated and controlled through current pulses, and the electrolyte synaptic transistor shows approximately linear and symmetrical synaptic weight updating characteristics.

(3) The electrolyte synaptic transistor can successfully simulate various representative synaptic characteristics, such as excitatory postsynaptic current and inhibitory postsynaptic current, double-pulse facilitation, spike frequency-dependent synaptic plasticity, spike time-dependent plasticity (such as Hebbian and anti-Hebbian), and the like, and successfully simulate Pavlovian conditioned reflex experiment.

(4) By virtue of excellent bending properties of the graphdine/two-dimensional semiconductor material heterojunction and the organic solid electrolyte film, a flexible synapse transistor device can be prepared on a flexible substrate such as PET (polyethylene terephthalate), and the prepared flexible synapse transistor device shows excellent stability and reliability in a bending test.

Drawings

FIG. 1 is a schematic structural diagram of an electrolyte synapse transistor in accordance with example 1;

FIG. 2 is a schematic side view of the electrolytic synapse transistor of example 1 in the direction S of FIG. 1;

FIG. 3 is a graph of the transmission characteristics of the electrolytic synapse transistor of example 1 at different gate voltage sweep rates;

FIG. 4 is a schematic diagram for explaining the mechanism of the electrolytic synapse transistor of example 1;

FIG. 5 is the excitatory postsynaptic current change triggered by the presynaptic electrical pulse (50ms) of the electrolytic synaptic transistor of example 1;

FIG. 6 shows that the electrolytic synapse transistor of example 1 obtains a plurality of different conductance states under different intensity current pulses;

FIG. 7 is a trace of weight updates for the electrolytic synapse transistor of example 1 at different currents;

FIG. 8 is a result of a bending performance test of the flexible electrolyte synapse transistor of example 2;

FIG. 9 shows the result of synaptic behavior simulation of the electrolyte synaptic transistor of example 1 under the STDP learning rule of Hebbian;

FIG. 10 shows the simulation results of the in-memory calculation of the logical AND of the electrolytic synapse transistor of example 1.

Reference numerals: in FIGS. 1 and 2, 10 represents SiO₂a/Si substrate, 20 for molybdenum disulfide, 30 for drain electrode, 40 for source electrode, 50 for side gate electrode, 60 for graphitic layer, 70 for solid electrolyte.

Detailed Description

The invention will be further explained and explained with reference to specific embodiments and the attached drawings.

Example 1

An electrolyte synapse transistor as shown in FIGS. 1 and 2 in SiO₂the/Si substrate 10 comprises molybdenum disulfide 20 as a conductive channel, and a drain electrode 30, a source electrode 40 and a side gate electrode 50 which are positioned on the molybdenum disulfide 20, so that a plane three-terminal type synapse transistor is formed. The surfaces of the conductive channels outside the drain electrode 30, the source electrode 40 and the side gate electrode 50 are provided with a graphite alkyne layer 60 as a floating gate storage layer. The floating gate memory layer and a part of the side gate electrode 50 are covered with a solid electrolyte 70, and the solid electrolyte 70 is a mixture of polyethylene oxide and lithium perchlorate (mass ratio of 3: 1).

The preparation method of the electrolyte synapse transistor comprises the following steps:

(1) and obtaining a plurality of layers of molybdenum disulfide by a mechanical stripping method, and transferring the molybdenum disulfide onto a PET substrate, wherein the thickness of the molybdenum disulfide is 3.753 nm. And then preparing a source electrode, a drain electrode and a side gate electrode on the molybdenum disulfide by adopting a laser direct writing photoetching method and a thermal evaporation method. The source electrode, the drain electrode and the side gate electrode are all Au/Cr materials, and comprise Cr with the thickness of about 5nm in contact with molybdenum disulfide and Au with the thickness of about 50nm covered on the Cr.

(2) And growing graphite alkyne on the surfaces of the molybdenum disulfide outside the source electrode, the drain electrode and the side gate electrode by using a Van der Waals epitaxial method, wherein the thickness of the graphite alkyne is 6.845 m.

(3) And (3) covering photoresist on the surface of the sample obtained in the step (2), and exposing the channel region and part of the side gate electrode by utilizing a photoetching technology.

(4) And (2) dissolving polyoxyethylene and lithium perchlorate (the mass ratio is 3:1) in 20ml of anhydrous methanol to obtain ionic liquid, dripping the ionic liquid on the channel region and the exposed surface of the side gate electrode, and drying to form a solid electrolyte with the thickness of about 400nm to obtain the electrolyte synaptic transistor.

Example 2

This example is similar to example 1, except that SiO was used₂And replacing the/Si substrate with a PET substrate to finally obtain the flexible electrolyte synapse transistor.

Performance testing

(1) FIG. 3 shows the side gate voltage (V)_g) Device transfer characteristics swept from-3V to 3V and back from 3V to-3V at 100mV/s, the scan sequence being detailed in FIG. 3Is/are as followsAnd (4) sequencing. When V is_gAt 0V, an on/off ratio of 10 is observed²Indicating a non-volatile change in channel conductance.

(2) The above-described counterclockwise hysteresis can be explained by the mechanism shown in fig. 4. Lithium ions in the solid electrolyte are driven to the surface of the Graphyne (GDY) under positive gate voltage and are collected on the surface of the material, and then inserted into the interlayer of the graphyne through the uniformly distributed pores of the graphyne [ FIG. 4(a) ]]. Testing applied gate voltage V_gLess than Li⁺Redox potential of/Li (-3.045V), so that Li is intercalated in the graphate⁺Which can be considered as a positive charge, induces a large number of electrons in the molybdenum disulfide through an Electric Double Layer (EDL) gating effect, thereby increasing the conductivity of the molybdenum disulfide. When the gate voltage becomes zero, lithium ions collected on the surface of the graphdine gradually diffuse back into the electrolyte driven by the concentration gradient. In contrast, Li intercalated in graphatidyne⁺Very stable so that they remain trapped in the graphone after the side gate voltage is removed, rendering the device non-volatile [ FIG. 4(b) ]]. When V is_gLi inserted into graphyne at < 0V⁺Driven by a reverse electric field, the molybdenum disulfide channel is separated from the graphdine, so that the conductivity of the molybdenum disulfide channel is restored to the initial state [ figure 4(c) ]]。

(3) As shown in FIG. 5, the read current V is controlled_dWhen a voltage pulse (1.0V, 50ms) is applied to the side gate electrode, 100mV, the electrolyte synapse transistor gets a forward current Spike (Spike) response, EPSC. After the side gate voltage pulse is removed, the channel current gradually declines from the peak value to the initial state.

(4) The test was performed by current pulse stimulation (0.1pA to 1pA, step 0.1pA) with a read voltage of 0.1V, and a number of different conductance states were obtained, as shown in fig. 6. Since the quantity of lithium ions inserted/removed by current pulse driving can be precisely controlled (Q ═ I _ SG × t), the conductance state change value (Δ G) of the electrolyte synapse transistor is stable, and conditions are provided for forming a linear and symmetrical conductance update track.

(5) The electrolyte synapse transistors were tested at 50ms intervals with 20 positive current pulses (0.1pA, 50ms) and 20 negative current pulses (0.1pA, 50ms) applied in sequence, with the results shown in fig. 7. The electrolyte synapse transistors exhibit nearly perfect linear and symmetric weight update trajectories. During the rise and fall, a sufficiently stable conductance state is obtained (see inset in fig. 7).

(6) The flexible electrolyte synaptic transistor of example 2 was subjected to LTP/LTD tests with different bending radii, and the results are shown in FIG. 8, wherein in FIG. 8(a), the number of pulses is between 0 and 2000 in a flat initial state, and the number of pulses is between 2000 and 4000 in a folded state (the folded state is a state in which the flexible electrolyte synaptic transistor is bent toward the front surface (i.e., the side loaded with the conductive channel, the source electrode, the drain electrode, and other materials) of the flexible electrolyte synaptic transistor, and the bending radius is 2.5mm]The pulse number is 4000 to 6000 stages, and the pulse number is in a curved state (the pulse number is curved toward the back surface of the electrolyte synapse transistor, and the radius of curvature is 2.5 mm). The test results reflect that the electrolyte synaptic transistor exhibits stable and repeatable cycling characteristics, and that the LTP/LTD curves in the bent and folded states also exhibit good linearity and symmetry, as well as a large number of effective conductance states and high conductance ratios (G)_max/G_min). Fig. 8(b) reflects the absence of attenuation in the on/off current state of the device after 1000 consecutive bend cycles.

(7) Under Hebbian's STDP learning rules, the synaptic behavior simulation behavior of the electrolyte synaptic transistors is shown in FIG. 8. Presynaptic spike V_preAnd post-synaptic spike V_postTo the side gate electrode and the drain electrode, respectively. Defining the synaptic weight before STDP learning as the initial weight (W) under the condition that each reading voltage is 0.1V₀) Synaptic weight after STDP training is W_STDPThus, the change in synaptic weight is defined as ξ (W)_STDP-W₀)/W₀X 100%. As shown in FIG. 9(a), the Hebbian learning rule is by applying Δ t_post-pre(the time interval in which the pre-synaptic pulse arrives before the post-synaptic pulse) spaced double triangular pre-and post-synaptic spikes.As shown in FIG. 9(b), when the pre-synaptic pulse arrives before the post-synaptic pulse, i.e., Δ t_post-pre>At 0, the device exhibits LTP synaptic behavior; conversely, when Δ t_post-pre<At 0, the device exhibits LTD synaptic behavior. With | Δ t_post-preThe plasticity of the device gradually disappears as the value of | increases.

(8) FIG. 10 is a simulation of in-memory computational results of logical AND of an electrolyte synapse transistor. The function of the and logic memory is simulated using two signal inputs (1V, 2s) and one modulation input (-1V, 2 s). With IN1 ═ IN2 ═ 0 "(i.e., IN-00), the device output current is below 10^-10A, corresponds to a logical "0". When the input signal is deactivated, the device realizes the storage of-00 logic, and the high resistance state is continuously maintained. IN the case of IN-10 and IN-01, the device also outputs a logic "0" and the high resistance state is not changed after the input signal is removed. On the other hand, IN IN-11 (V)_G1＝V_G21V) the device achieves a higher current output (10) of^-6A) Corresponding to a logical "1".