阅读说明：本技术 用于校正裸片放置误差的自适应布线 (Adaptive routing for correcting die placement errors ) 是由 R·欧隆 M·布尔迪诺夫 E·戈申 R·F·卡米斯开 G·拉威赫 于 2019-10-02 设计创作，主要内容包括：本发明揭示一种方法,其包含接收电子模块的至少部分的布局设计,所述设计至少指定(i)耦合到至少一衬底的电子装置及(ii)连接到所述电子装置且具有经设计布线的电迹线。接收数字输入,所述数字输入表示根据所述布局设计制造但无所述电迹线的至少一部分的实际电子模块的至少部分。基于所述数字输入估计在将所述电子装置耦合到所述衬底时相对于所述布局设计的误差。针对所述电迹线的至少所述部分计算校正所述经估计误差的实际布线。在所述实际电子模块的所述衬底上沿着所述实际布线而非所述经设计布线形成所述电迹线的至少所述部分。(A method includes receiving a layout design of at least a portion of an electronic module, the design specifying at least (i) an electronic device coupled to at least one substrate and (ii) electrical traces connected to the electronic device and having designed wiring. Receiving a digital input representing at least a portion of an actual electronic module manufactured according to the layout design but without at least a portion of the electrical traces. Estimating an error in coupling the electronic device to the substrate relative to the layout design based on the digital input. Calculating an actual routing for at least the portion of the electrical trace that corrects the estimated error. Forming at least the portion of the electrical trace along the actual routing, but not the designed routing, on the substrate of the actual electronic module.)

1. A method, comprising:

receiving a layout design of at least a portion of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate and (ii) electrical traces connected to the electronic device and having designed wiring;

receiving a digital input representing at least a portion of an actual electronic module manufactured according to the layout design but without at least a portion of the electrical traces;

estimating, based on the digital input, an error relative to the layout design when coupling the electronic device to the substrate;

calculating, for at least the portion of the electrical trace, an actual routing that corrects the estimated error; and

forming at least the portion of the electrical trace along the actual routing, but not the designed routing, on the substrate of the actual electronic module.

2. The method of claim 1, wherein calculating the actual route comprises:

defining for the actual electronic module: (i) a first frame surrounding the electronic device and maintaining a first margin around the electronic device; and (ii) a second frame surrounding the first frame and maintaining a second margin around the electronic device that is greater than the first margin; and

calculating the actual routing between the first frame and the second frame.

3. The method of claim 2, wherein defining the second frame comprises setting the second margin based on the estimated error in coupling the electronic device to the substrate.

4. The method of claim 2, wherein receiving the digital input comprises receiving at least one input selected from the list consisting of: (a) an image of the actual electronic module arranged at least within the first frame and the second frame, and (b) a measurement of a width of at least the portion of the electrical trace arranged at least between the first frame and the second frame.

5. The method of claim 2, and comprising, based on the numerical input, disqualifying the actual electronic module when at least a portion of the electronic device or the first frame exceeds the second frame.

6. The method of claim 1, wherein estimating the error comprises estimating one or more error types selected from a list consisting of: (a) a shift of the electronic device from a first position specified in the layout design to a second position received in the digital input, (b) a rotation of the electronic device in the digital input relative to the layout design, and (c) a scaling error between the electronic device and the substrate.

7. The method of claim 1, wherein the designed routing comprises at least one point arranged at a first location on a first edge of the designed routing, and wherein calculating the actual routing comprises estimating a displacement of the point from the first location to a second different location based on the digital input and calculating a first calculated edge on the actual routing based on the second location such that the second location is arranged on the first calculated edge.

8. The method of claim 7, wherein calculating the actual routes comprises checking whether the actual routes violate one or more design rules of the layout design and adjusting the actual routes to comply with the design rules.

9. The method of claim 1, wherein forming the electrical trace comprises generating the electrical trace along the actual wiring using a direct imaging system.

10. The method of claim 1, wherein the substrate comprises a Printed Circuit Board (PCB) and the electronic device comprises an Integrated Circuit (IC) mounted on the PCB.

11. The method of claim 1, wherein the electronic device is coupled to the substrate using an embedded die packaging process.

12. A system, comprising:

a processor configured to:

receiving a layout design of at least a portion of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate and (ii) electrical traces connected to the electronic device and having designed wiring;

receiving a digital input representing at least a portion of an actual electronic module manufactured according to the layout design but without at least a portion of the electrical traces;

estimating, based on the digital input, an error relative to the layout design when coupling the electronic device to the substrate; and

calculating, for at least the portion of the electrical trace, an actual routing that corrects the estimated error; and

a direct imaging subsystem configured to form at least the portion of the electrical trace on the substrate of the actual electronic module along the actual routing, but not the designed routing, based on the actual routing.

13. The system of claim 12, wherein the processor is configured to:

defining for the actual electronic module: (i) a first frame surrounding the electronic device and maintaining a first margin around the electronic device; and (ii) a second frame surrounding the first frame and maintaining a second margin around the electronic device that is greater than the first margin; and

calculating the actual routing between the first frame and the second frame.

14. The system of claim 13, wherein the processor is configured to set the second margin based on the estimated error in coupling the electronic device to the substrate.

15. The system of claim 13, wherein the processor is configured to receive at least one input selected from the list consisting of: (a) an image of the actual electronic module arranged at least within the first frame and the second frame, and (b) a measurement of a width of at least the portion of the electrical trace arranged at least between the first frame and the second frame.

16. The system of claim 13, wherein based on the digital input, the processor is configured to reject the actual electronic module when at least a portion of the electronic device or the first frame exceeds the second frame.

17. The system of claim 12, wherein the processor is configured to estimate one or more error types selected from the list consisting of: (a) a shift of the electronic device from a first position specified in the layout design to a second position received in the digital input, (b) a rotation of the electronic device in the digital input relative to the layout design, and (c) a scaling error between the electronic device and the substrate.

18. The system of claim 12, wherein the designed wiring comprises at least one point arranged at a first location on a first edge of the designed wiring, and wherein the processor is configured to estimate a displacement of the point from the first location to a second different location based on the digital input and to calculate a first calculated edge on the actual wiring based on the second location such that the second location is arranged on the first calculated edge.

19. The system of claim 18, wherein the processor is configured to check whether the actual routing violates one or more design rules of the layout design and to adjust the actual routing to comply with the design rules.

20. The system of claim 12, wherein the direct imaging subsystem is configured to print the electrical traces along the actual routing.

21. The system of claim 12, wherein the substrate comprises a Printed Circuit Board (PCB) and the electronic device comprises an Integrated Circuit (IC) mounted on the PCB.

22. The system of claim 12, wherein the electronic device is coupled to the substrate using an embedded die packaging process.

Technical Field

The present invention relates generally to manufacturing electronic modules and, in particular, to methods and systems for adaptive wiring interconnection of electronic devices on a substrate of an electronic module.

Background

Electronic modules and systems typically include one or more electronic devices electrically connected to a substrate using electrical interconnects. Various techniques for patterning electrical interconnects are known in the art.

For example, U.S. patent 7,508,515 describes a system and method for manufacturing an electrical circuit in which a digital control image is generated by nonuniformly modifying a representation of the circuit so that the circuit pattern recorded on a substrate using the digital control image accurately conforms to the circuit portions that have been formed.

U.S. patent 8,799,845 describes an adaptive patterning method and system for manufacturing panel-based package structures. Misalignment of individual device units in a panel or mesh wafer can be adjusted by measuring the position of each individual device unit and forming a unit specific pattern over each individual device unit.

U.S. patent 9,040,316 describes a semiconductor device and method for adaptive patterning using dynamic via-cut framing (paneled packaging). A panel is formed that includes an encapsulation material disposed around a plurality of semiconductor dies. An actual position of each of a plurality of semiconductor dies within a panel is measured. A conductive redistribution layer (RDL) is formed that includes a first capture pad aligned with an actual position of each of the plurality of semiconductor dies. A plurality of second capture pads are formed that are at least partially disposed over the first capture pads and that are aligned with the package outline of each of the plurality of semiconductor packages. The nominal footprint of the plurality of conductive vias is adjusted to account for misalignment between each semiconductor die and its corresponding package outline.

Disclosure of Invention

Embodiments of the invention described herein provide a method that includes receiving a layout design of at least a portion of an electronic module, the design specifying at least (i) an electronic device coupled to at least one substrate and (ii) electrical traces connected to the electronic device and having designed wiring. Receiving a digital input representing at least a portion of an actual electronic module manufactured according to the layout design but without at least a portion of the electrical traces. Estimating an error in coupling the electronic device to the substrate relative to the layout design based on the digital input. Calculating an actual routing for at least the portion of the electrical trace that corrects the estimated error. Forming at least the portion of the electrical trace along the actual routing, but not the designed routing, on the substrate of the actual electronic module.

In some embodiments, calculating the actual wiring includes defining, for the actual electronic module: (i) a first frame surrounding the electronic device and maintaining a first margin around the electronic device; and (ii) a second frame surrounding the first frame and maintaining a second margin around the electronic device that is greater than the first margin. Calculating the actual routing between the first frame and the second frame. In other embodiments, defining the second frame includes setting the second margin based on the estimated error in coupling the electronic device to the substrate. In yet other embodiments, receiving the digital input comprises receiving at least one input selected from the list consisting of: (a) an image of the actual electronic module arranged at least within the first frame and the second frame, and (b) a measurement of a width of at least the portion of the electrical trace arranged at least between the first frame and the second frame.

In an embodiment, the method includes disqualifying the actual electronic module when at least a portion of the electronic device or the first frame exceeds the second frame based on the digital input. In another embodiment, estimating the error includes estimating one or more error types selected from the list consisting of: (a) a shift of the electronic device from a first position specified in the layout design to a second position received in the digital input, (b) a rotation of the electronic device in the digital input relative to the layout design, and (c) a scaling error between the electronic device and the substrate. In yet another embodiment, the designed routing includes at least one point arranged at a first location on a first edge of the designed routing, and calculating the actual routing includes estimating a displacement of the point from the first location to a second different location based on the digital input and calculating a first calculated edge on the actual routing based on the second location such that the second location is arranged on the first calculated edge.

In some embodiments, calculating the actual routes includes checking whether the actual routes violate one or more design rules of the layout design and adjusting the actual routes to comply with the design rules. In other embodiments, forming the electrical trace includes generating the electrical trace along the actual routing using a direct imaging system.

In an embodiment, the substrate comprises a Printed Circuit Board (PCB) and the electronic device comprises an Integrated Circuit (IC) mounted on the PCB. In another embodiment, the electronic device is coupled to the substrate using an embedded die packaging process.

There is additionally provided, in accordance with an embodiment of the present invention, a system, including a processor and a direct imaging subsystem. The processor is configured to: (a) receiving a layout design of at least a portion of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate and (ii) electrical traces connected to the electronic device and having designed wiring; (b) receiving a digital input representing at least a portion of an actual electronic module manufactured according to the layout design but without at least a portion of the electrical traces; (c) estimating, based on the digital input, an error relative to the layout design when coupling the electronic device to the substrate; and (d) calculating, for at least the portion of the electrical trace, an actual routing that corrects the estimated error. The direct imaging subsystem is configured to form at least the portion of the electrical trace on the substrate of the actual electronic module along the actual routing, but not the designed routing, based on the actual routing.

The invention will be more fully understood from the following detailed description of embodiments of the invention taken together with the drawings, in which:

drawings

FIG. 1 is a schematic illustration of a Direct Imaging (DI) system for printing conductors on a substrate, according to an embodiment of the present invention;

FIG. 2A is a schematic illustration of a layout design of an electronic module according to an embodiment of the invention;

FIG. 2B is a schematic illustration of a layout for correcting errors in coupling an electronic device to a substrate, according to an embodiment of the invention;

FIG. 3 is a flow diagram schematically illustrating a method for correcting an estimated error in coupling an electronic device to a substrate, in accordance with an embodiment of the invention;

FIG. 4 is a schematic illustration of a layout design of a section of an electronic module according to an embodiment of the invention;

FIG. 5 is a schematic, illustrative diagram of a process sequence for calculating actual routing of an electrical trace that corrects for an estimated error in coupling an electronic device to a substrate, in accordance with an embodiment of the invention;

FIG. 6 is a schematic illustration of a sequence of processes for generating a transformation matrix between a layout design of a given electronic module and an image of an actually generated component of the given electronic module, in accordance with an embodiment of the present invention; and

FIG. 7 is a schematic illustration of a layout for correcting errors between two electronic devices electrically coupled via a substrate, according to an embodiment of the invention.

Detailed Description

SUMMARY

Generating an electronic module typically includes coupling at least one electronic device to a substrate, such as by picking the electronic device from a diced wafer as a die and placing the die on the substrate. Electronic devices are typically connected to other components on the substrate using electrical traces.

In some cases, errors occur in the placement of the die, which can cause misalignment between the electronic device and the electrical traces on the substrate, resulting in poor functionality or disqualification of the electronic module.

Embodiments of the invention described below provide systems and methods for estimating and correcting placement errors of electronic devices by adaptively routing electrical traces on a substrate.

In some embodiments, a system includes a processor configured to receive a layout design of at least a portion of an electronic module. The received layout design includes at least an electronic device coupled to the substrate and an electrical trace connected to the electronic device and having designed routing.

In some embodiments, the processor further receives digital inputs (e.g., images and measurements) of at least a portion of an actual electronic module manufactured according to the layout design but without at least a section of the one or more electrical traces. In some embodiments, the processor is configured to estimate an error in a position of the electronic device on the substrate relative to the layout design based on the digital input. The processor is further configured to calculate, for at least the section of one or more electrical traces, an actual routing that corrects for the estimated error.

In some embodiments, based on the layout design and the specified error, the processor is configured to compute an inner frame and an outer frame that enclose the electronic device. An inner frame coaxially surrounds the electronic device, e.g., with a predefined margin, and an outer frame surrounds the inner frame and has a margin equal to or greater than the specified error. The margin between the inner frame and the outer frame is also referred to herein as the "correction zone".

In some embodiments, the processor is configured to select one or more points along a given edge of the designed route of the segment. For each selected point, the processor is configured to find a point located at a minimum distance (referred to herein as a designed width) from the selected point along an opposite edge of the section facing the given edge.

In some embodiments, based on the digital input, the processor is configured to calculate the calculated routes for the sections within the correction region by transforming at least selected points of the designed routes to comply with the digital input. The processor further calculates a width for each of the selected points by finding a corresponding point located at opposite edges of the segment that is a minimum distance from the respective selected point.

In some embodiments, the processor is configured to check whether the calculated routes comply with the design rules of the section, e.g., by making a comparison between corresponding designed and calculated widths at one or more of the selected points, and, when needed, calculate the actual routes by adjusting the calculated routes to comply with the design rules.

In some embodiments, the system further comprises a direct imaging subsystem configured to generate at least the section of the electrical trace along actual routing, rather than designed routing, on a substrate of an actual electronic module based on the actual routing.

The disclosed techniques improve the quality of electronic modules integrated in, for example, a PCB or embedded die package by adjusting the routing between the device and the substrate in order to compensate for variations in the pick and place process of the electronic module. Furthermore, the disclosed techniques improve the production efficiency of such electronic modules by improving production yield and by enabling higher densities of electronic modules produced over a given area (real estate) of the substrate.

Description of the System

Fig. 1 is a schematic illustration of a Direct Imaging (DI) system 100 for printing a pattern on a substrate 106, in accordance with an embodiment of the present invention.

In some embodiments, system 100 includes a housing 101 mounted on an optical support (not shown). The frame 101 includes a substrate support surface 104 configured to hold a substrate 106 for printing a pattern thereon by the system 100. In some embodiments, the substrate 106 may comprise any substrate suitable for computerized direct writing to be performed thereon and the patterning defines objects on one or more surfaces of the substrate 106, typically by exposing a photoresist overlying the respective surface to a laser. In other embodiments, patterning may define objects on one or more surfaces of the substrate 106 by exposing any other suitable photosensitive material overlying the respective surface to a laser. In some embodiments, the system 100 is configured to apply a direct write process to a substrate in order to print a design of a plurality of objects thereon.

In the context of the present invention, the term object refers to a feature of any cell (e.g., electronic module) that can be patterned by computerized direct writing on the substrate 106, each cell being generally spaced apart from other adjacent cells positioned on the substrate 106. In some embodiments, system 100 is configured to process various types of modules, such as, but not limited to, electronic circuits configured to electrically connect with one or more devices mounted on a Printed Circuit Board (PCB) and one or more devices, such as Integrated Circuit (IC) devices, packaged as an embedded die in any suitable substrate. The embedded die package may include, for example, fan-in and/or fan-out packages for various types of devices (e.g., processors, controllers, memory devices), various types of one or more sensors, and various types of one or more light sources.

In some embodiments, the substrate 106 may include: a panel comprising at least one of woven fiberglass, polyimide, epoxy compound, or any other type of rigid or flexible polymer; or a wafer made of a semiconductor material (e.g., silicone-germanium, or compound semiconductor), glass, plastic mold, or any other suitable material. Further, the substrate 106 may be a flexible substrate that is bonded to a rigid support layer (e.g., glass) during production and subsequently removed therefrom after the production process is completed.

In some embodiments, the system 100 comprises a bridge 112 arranged for linear motion relative to the substrate support surface 104 along an axis parallel to a first axis 114 defined relative to the enclosure 101. In other embodiments (not shown), the bridge may be stationary and the support surface along with the substrate placed thereon configured to move, or both the bridge and the support surface move relative to each other.

In some embodiments, system 100 includes at least one read/write assembly mounted along bridge 112. In the example of FIG. 1, a single read/write assembly 116 is arranged for selectable positioning relative to the bridge 112 along a second axis 118 that is orthogonal to the first axis 114. This arrangement enables multiple sequential parallel scans to be performed over the substrate 106, each scan producing multiple objects 120.

In other embodiments, the system 100 may include a plurality of read/write assemblies 116 that may be arranged in a side-by-side configuration along the second axis 118 on the bridge 112. This configuration enables multiple scans to be carried out by respective assemblies 116 simultaneously or partially simultaneously over substrate 106, each scan producing multiple objects 120.

In some embodiments, the objects 120 are generally, but not necessarily, similar to each other and may be arranged front-to-back in a direction parallel to the first axis 114 and side-by-side parallel to the second axis 118, as illustrated in fig. 1. Alternatively, the objects 120 may be arranged in any other suitable pattern (e.g., in a non-linear repeating or non-repeating pattern). In some embodiments, the electronic module 200 includes a device 202, such as an Integrated Circuit (IC) or a memory device or any other suitable electronic device.

In some embodiments, the system 100 includes an operating console (also referred to herein as a control assembly 124) that includes a computer 126 (which includes various devices, such as one or more processors and one or more memory devices (not shown)) and a user interface 128. The computer 126 further includes software modules configured to control the operation of the read/write assembly 116, the bridge 112, and other components of the system 100.

In the context of the present invention, and in the claims, the term "processor of the computer 126" is hereinafter simply referred to as "processor" for brevity.

In some embodiments, control assembly 124 further comprises a database of write instructions 130, the database of write instructions 130 comprising computer-aided design (CAD) instructions for writing objects 120 on at least one surface of substrate 106 according to embodiments of the present invention.

In some embodiments, at least one read/write assembly 116 includes an Automated Optical Imaging (AOI) subsystem 132 configured to capture an optical image 134 of the substrate 106 received by a processor of the computer 126. Such optical images 134 may include optical images of one or more suitable features of the object 120 (e.g., having unique shapes) and/or any suitable fiducial 135 on the substrate 106 that is typically used for registration and/or calibration of the system 100. In some embodiments, AOI subsystem 132 is further configured to measure various dimensions of features of an electronic module and, for example, distances between neighboring features.

In some embodiments, the read/write assembly 116 further comprises a direct imaging subsystem, such as a Laser Direct Imaging (LDI) subsystem 136, which comprises an optical scanning assembly configured to enable laser writing onto the substrate 106 to produce the object 120 in response to direct write data 138 received from the processor of the computer 126. It should be noted that although both the AOI subsystem 132 and the LDI subsystem 136 are referred to herein as types of imaging subsystems, the imaging performed by each subsystem has mutually different properties. The AOI subsystem 132 performs optical imaging of the substrate 106 to acquire optical images thereof, at least for the purposes of measurement, inspection, registration, and calibration of the system 100 prior to performing direct writing on the substrate 106. In contrast, the LDI subsystem 136 performs direct writing on the substrate 106 by laser imaging a pattern onto the substrate 106. In the context of the present invention, and in the claims, the term "LDI subsystem" is hereinafter simply referred to as "LDI" or "DI" for brevity.

In some embodiments, the LDI 136 may comprise a laser scanner of the type described in U.S. Pat. No. 8,531,751, assigned to the same assignee as the present invention. Other examples of direct imaging systems suitable for use with the present invention include the direct imaging system model number DW-3000 available from Screen Semiconductor (SCREEN Semiconductor) of Tokyo, Japan and the maskless aligner system model number MLA150 available from Heidelberg Instruments of Heidelberg, Germany.

In an embodiment, the AOI subsystem 132 is configured to be used as a registration testing subsystem for improving the direct imaging process of the LDI subsystem 136.

In some embodiments, the processor of the computer 126 is configured to receive a computer-aided design (CAD) file comprising circuit design data for direct writing on the substrate 106 from the database 130, the CAD file comprising CAD data for a plurality of objects 120 to be produced on the substrate 106.

In some embodiments, the processor of the computer 126 is configured to control the read/write assembly 116 to direct one or more laser beams for writing data directly on the substrate 106 in a plurality of parallel scans based on CAD data. Multiple parallel scans may be performed sequentially by a single resettable read/write assembly as illustrated in FIG. 1, or may be performed simultaneously or partially simultaneously using multiple read/write assemblies.

In some embodiments, the control assembly 124, which is also referred to as an Automatic Direct Write Machine Configuration (ADWMC) unit, is configured to receive a CAD file containing circuit design data for direct writing on at least one surface of the substrate 106. The control assembly 124 is further configured to automatically configure a direct write machine including at least one read/write assembly 116 to directly write direct write data on the substrate 106 based on CAD data in a plurality of scans.

In an embodiment, the processor of the computer 126 automatically configures the direct write data to cause the plurality of objects 120 to be written in a side-by-side manner in each of the plurality of scans so as to be within the scan width such that no objects are written in the plurality of scans, thereby avoiding the need to stitch the direct write data between adjacent scans.

In some embodiments, the read/write assembly 116 is controlled by the control assembly 124 to generally produce multiple objects 120 on the substrate 106 in multiple scan passes, with seams of adjacent scan passes not being positioned within the objects, thereby avoiding the need to stitch direct write data between adjacent scans. It should be noted that the seams are arranged to be between objects 120 and not overlying within objects 120.

In some embodiments, due to the inherent limitations of the maximum scan length provided by the LDI 136, multiple scan passes are typically required in order to scan the full width of the substrate 106. Such multiple scan passes may be performed sequentially using a single resettable scan head or at least partially simultaneously by multiple scan heads operating simultaneously. This limitation of scan length is constrained by, among other factors, the critical ratio that must be maintained between the required size of the focused laser beam to perform direct writing on the substrate surface and the scan length of the scan lens of the LDI 136.

In some embodiments, the substrate 106 is not limited to being a single layer substrate on which only a single layer of the object 120 is patterned. Rather, system 100 can be employed in an additive fashion to selectively modify a substrate layer by layer to produce a three-dimensional structure. Thus, the object 120 may be formed from multiple layers that may be sequentially written by the read/write assembly 116 in registration over one another.

Generally speaking, the computer 126 comprises a general purpose computer programmed in software to carry out the functions described herein. The software may be downloaded to the computer in electronic form, over a network, for example, or it may alternatively or additionally be provided and/or stored on non-transitory tangible media, such as magnetic, optical, or electronic memory.

Fig. 2A is a schematic explanatory diagram of a layout design of an electronic module 200 according to an embodiment of the present invention. The electronic module 200 may replace, for example, the electronic module of object 120 of fig. 1 above. In some embodiments, the electronic module 200 includes the device 202 depicted in fig. 1 above.

In an embodiment, the device 202 is coupled to a substrate 255, which substrate 255 can replace, for example, the substrate 106 of FIG. 1 above. In this embodiment, the device 202 and the substrate 255 may be coupled to each other using any suitable configuration. For example, the device 202 may be mounted on a substrate 255 comprising a PCB. In another example, the device 202 may be embedded in the substrate 255 using any suitable embedded die packaging technique, such as fan-in (e.g., in a semiconductor substrate) or fan-out (e.g., in a plastic mold substrate). In some embodiments, the substrate 255 includes electrical traces 222 connected to the device 202, each electrical trace 222 having designed routing between, for example, a pad 204 of the device 202 and a connector 206 (also referred to herein as a connection pad) of the substrate 255.

In some embodiments, the processor of the computer 126 is configured to calculate a frame 210 in the electronic module 200 that surrounds the device 202 and has a predefined margin (referred to herein as region 233) from the edge of the device 202. It should be noted that the frame 210 follows the size, position, and orientation of the device 202. For example, if the device 202 is rotated at a given angle of rotation relative to the designed layout, the frame 210 is also rotated at the same angle.

The processor is further configured to calculate a frame 220 in the electronic module 200, surrounding the frame 210, with another margin therebetween (referred to herein as the region 211 or the correction region). The method for calculating the size of the framework 220 and the width of the region 211 is described in detail in fig. 2B below. It should be noted that the frames 210 and 220 are virtual frames arranged by the processor on the design of the electronic module 200. In an embodiment, the correction zone between frames 210 and 220 is used to correct placement errors of device 202 on substrate 255, as will be described in detail below in FIG. 2B.

In some embodiments, each trace 222 of the electronic module 200 includes three segments. The inner section (also referred to herein as section 218) is arranged between the pad 204 and the frame 210. The outer section (also referred to herein as section 216) is arranged between frame 22 and connector 206, and the intermediate section (also referred to herein as section 244) is arranged between frame 210 and frame 220 and connected between sections 216 and 218.

Estimating die-to-substrate coupling errors and calculating routing to correct estimated errors

Fig. 2B is a schematic illustration of an electronics module 260, according to an embodiment of the invention. Module 260 may replace, for example, module 200 of fig. 2A above. During the manufacture of the module 260, the device 202 is cut from a substrate (e.g., a silicon wafer) as a die, and the device 202 is separated from adjacent dies using tape and tape or any other suitable technique.

Subsequently, a pick-and-place system (not shown) picks up the device 202 from the tape and couples the device 202 to a predefined location on the substrate 255. The pick-and-place system may have process variations that may cause errors in the coupling process of the device 202 to the substrate 255. For example, the pick-and-place system may place the device 202 on the substrate 255 at an offset relative to the predefined location of the designed layout shown in fig. 2A, for example, above. This offset error is also referred to herein as "translation" or "shift.

The coupling process may have other errors, such as rotational errors caused by undesired rotation of the device 202 relative to the orientation specified in the designed layout shown in fig. 2A, for example, above. Furthermore, thermal cycling during fabrication may cause different ratios between the size and/or area of the device 202 and the substrate 255 relative to the layout design shown in fig. 2A above. For example, the substrate 255 may include a polymer having a Coefficient of Thermal Expansion (CTE) greater than the CTE of the device 202, which is typically made of silicone. This CTE difference may result in, for example, the different ratios described above, also referred to herein as a scaling error between the device 202 and the substrate 255.

As depicted in fig. 1 above, the substrate may include a plurality of objects 120, thus a plurality (e.g., more than a thousand) of electronic modules 260 (each including at least a device 202). In an exemplary manufacturing process of electronic modules 260, more than one thousand devices 202 are coupled to substrate 255 and a suitable measurement system (e.g., registration test system or AOI subsystem 132) captures images of multiple electronic modules 260 (e.g., sampling five electronic modules) across substrate 255.

In some embodiments, the processor is configured to extract from the database 130 only the area and location of the entire frame 210 similar to the entire electronic module 206 (rather than the entire area of the substrate) and save this information in the memory of the computer 126. In these embodiments, the processor reduces the load on the memory and communication resources of the computer 126, which also enables improved speed and reliability of operation of the LDI subsystem 136.

In some embodiments, the processor is configured to receive digital input from the registration testing system and/or from AOI subsystem 132, such as a set of images and/or a set of measurements acquired from each sampled electronics module 260 (e.g., size, orientation, and registration between the designed features and the actually generated features of electronics module 260). It should be noted that the digital input includes at least a portion of the generated electronic module 260 (also referred to herein as the actual electronic module 260) that is manufactured according to the layout design shown in fig. 2A, for example, above, but without at least a portion of the electrical trace 222 (e.g., the section 244).

In some embodiments, the processor is configured to estimate an error in the coupling of the device to the substrate 255 relative to the layout design (e.g., shown in fig. 2A above) based on the images and measurements of the digital input. It should be noted that the estimated error typically includes a combination of the shift, rotation, and scaling errors described above.

In alternative embodiments, the estimated error may comprise only one of the aforementioned errors, or an additional error, or a combination of any two or more errors estimated based on digital input received from the registration testing system or from any other imaging and/or measurement system.

In some embodiments, the processor is configured to set the width of the region 211 (i.e., the margin between the frames 210 and 220) based on the maximum placement error of the device 202 on the substrate 255. The maximum error is typically a combination of the shift and rotation and scaling errors described above. In an embodiment, the processor applies a factor (e.g., 5) to the maximum error for setting the width of region 211. For example, for a device 202 having a size of 1mm (e.g., length and width), the specified displacement error is 30 μm, the specified rotation error is 10 milliradians (mrad) (resulting in up to 10 μm displacement due to rotation), and the specified scaling error is 1% (resulting in an additional 10 μm error due to scaling error of at least one of the device 202 and the substrate 255). In this example, the combined maximum error sums are up to 50 μm, thus, the selected width of region 211 is set to 250 μm.

In other embodiments, the processor may apply any other suitable calculation for setting the width of the region 211. For example, the factor applied to the maximum error may be greater than 1 but less than 5. An exemplary factor of 1.5 reduces the footprint of frame 220 by reducing the width of region 211 from 250 μm to 75 μm. This factor allows a greater number of electronic modules 260 to be incorporated on the substrate 255, but can reduce production yield if the total error exceeds a specified value of 50 μm (e.g., when the total error adds up to 80 μm). In this example, at least a portion of the devices 202 of a respective electronic module 260 may exceed the area of the frame 220 and, as a result, the processor of the computer 126 will disqualify such a respective electronic module 260.

In alternative embodiments, the processor may use only one error (e.g., a shift error), or a combination of selected two of the foregoing errors (e.g., a shift error and a rotation error), or another error of another measurement, such as provided by AOI subsystem 132, or a combination thereof, or any other suitable method in the calculation of the width of region 211.

Additionally or alternatively, in case the estimated error in a given electronic module exceeds a specified value, the processor may issue an alert to disqualify the respective given electronic module. In an embodiment, AOI subsystem 132 is further configured to detect defects in, for example, a particular electronic module 260, such that even if the estimated error described above is within specification in the particular electronic module, the processor may disqualify the particular electronic module due to the defect.

In some embodiments, the processor is configured to calculate, for at least section 244 of electrical trace 222, an actual routing that corrects the estimated error described above. As shown in fig. 2B, sections 218 and 216 of trace 222 are held relative to pad 204 of device 202, for example, as in the designed layout shown in fig. 2A above, so that the actual routing of section 244 compensates for errors by connecting between the ends of sections 218 and 216 positioned on frames 210 and 220, respectively.

It should be noted that although the sections 218 are held at the same position and orientation relative to the respective pads 204, in practice, the pads 204 are displaced due to the errors described above. In an embodiment, the processor is configured to calculate the actual wiring for each section 218 using the same method used to calculate the actual wiring for sections 244.

In other words, the actual routing of the sections 218 is different than the designed routing of the sections 218 in order to maintain the designed position and orientation of each section 218 relative to the respective pad 204 (which is shifted within the displacement of the device 202). The actual routing of section 244 is different than the designed routing of section 244 in order to compensate for relative displacement between the actual routing and the designed routing of section 218.

Subsequently, based on the calculated actual routing, the LDI subsystem 136 prints all of the sections of the traces 222 (e.g., sections 216, 244, and 218) as described above.

The method and layout of fig. 2B is simplified for clarity and is shown by way of example in order to illustrate certain problems addressed by embodiments of the present invention and to demonstrate the application of these embodiments in enhancing the performance of any DI system, such as DI system 100.

However, embodiments of the present invention are in no way limited to this particular kind of exemplary DI system and/or method and/or arrangement, and the principles described herein may be similarly applied to any other kind of system, method and arrangement.

In alternative embodiments, the processor may apply any other suitable method for correcting estimated errors in the coupling of the device 202 to the substrate 255. For example, an inkjet system is used instead of the DI system 100, or any other suitable type of additive manufacturing technology (e.g., metal printer), or any CAM station rewiring solution, or any other suitable method for correcting estimated errors in the coupling between the device 202 and the substrate 255.

FIG. 3 is a flow diagram schematically illustrating a method for correcting an estimated error in coupling a device 202 to a substrate 255, in accordance with an embodiment of the invention. The method begins with a processor receiving a design for a panel disposed on a substrate 255, such as from a database 130, at a design receiving step 300. The processor is further configured to define regions of interest and respective sizes of each region of interest based on input from a user of the system 100 and/or based on one or more files of the database 130. For example, the user input may include the location of each electronic module (e.g., electronic module 200), the size of the device 202, and the specified errors of shifting, rotating, and scaling as described above.

At a panel learning step 302 (also referred to herein as an "offline step" or "preprocessing step"), the processor determines points of interest in the design layout, for example, along trace 222, and classifies points in close proximity to each point of interest. In some embodiments, the processor is configured to calculate the designed width of the trace 222 based on an offline step, as will be described in detail in fig. 5 below.

Indeed, the panel learning step 302 may be carried out at a later stage (e.g., after receiving digital input from the registration testing system, for example), but the preprocessing of step 202 improves the speed and efficiency of the system 100.

At a digital input receiving step 304, the processor receives digital input (e.g., images and/or measurements taken at a plurality of locations across the substrate 255) from the registration test system (or from any other suitable system, such as AOI subsystem 132) of at least a portion of an actual electronic module (e.g., electronic module 260) that was manufactured according to the layout design shown in fig. 2A above, but without at least the section 244 of the electrical trace 222. As described in fig. 2B above, the processor is configured to estimate, based on the digital input, a combined error (e.g., shifted, rotated, and scaled) relative to the layout design (e.g., of the electronic module 200) caused in coupling the device 202 to the substrate 255. It should be noted that steps 300 and 302 are considered offline steps, and all other operations performed by the processor after receiving a digital input are considered online steps. The offline and online steps are depicted in more detail in fig. 4-6 below.

At transform step 306, the processor transforms the preprocessed data of section 244 and, optionally, other elements of electronic module 206 (mentioned earlier at step 302) in order to form a calculated wiring that complies with the digital input received at step 304. In other words, the processor transforms the designed pattern of features of interest of the electrical traces 222 so as to comply with the actual position of the device 202 relative to the designed layout of the substrate 255. The computed transformation is detailed in fig. 5 below.

At a verification step 308, the processor applies a set of design rules for the electronic module (e.g., minimum width of traces 222, minimum distance between adjacent features of the electronic module, allowed shape of the feature of interest, and other design rules) to the calculated routes obtained at step 306 above. In some embodiments, the processor may use software for checking design rules, and/or may interface with any suitable commercially available design rule checking station (not shown).

In some embodiments, after applying the design rules, the processor may identify one or more electronic modules that violate (i.e., may not comply with) the design rules. In other words, in the respective electronic module, the calculated routing of section 244 will not be able to correct the error estimated at step 304, or the correction may fail to comply with design rules. In these embodiments, the processor is configured to disqualify (also referred to herein as "retirement") these electronic modules in order to focus the time of utilization of the LDI subsystem 136 on electronic modules that comply with the design rules.

In other embodiments, the processor is configured to mark these electronic modules for corrective process steps that may be carried out at a subsequent stage of the process. The markers may be physical markers that are electronic (e.g., using a file with the coordinates of the respective electronic module or modules) and/or using any suitable technique. As mentioned above, the processor may calculate new routing for section 244 and/or another portion of electrical traces 222 and may send one or more instruction files to LDI subsystem 136 for correcting calculated errors in traces 222.

At an adjustment step 310, the processor adjusts the calculated routes based on the design rules and calculates actual routes for at least the section 244 (and optionally for other elements of the electronic module) that correct the estimated errors and also comply with the design rules of the electronic module. In some embodiments, after obtaining the actual routing, the processor sends one or more instruction files for applying the actual routing to section 244 of trace 222 to LDI subsystem 136 (or to any other suitable type of patterning system), thereby terminating the online step of the method.

In an example embodiment, the designed width of electrical trace 222 along sections 216, 218, and 244 is 10 μm based on the design rules at a given point. After the transformation step 306, the calculated width of at least one section 244 is 8 μm, resulting in an error of 2 μm, such that the processor must increase the width of the section 244. In this embodiment, the processor shifts each of the two edges of the section 244 by half the error (e.g., 1 μm) in a direction away from the center of the section 244 at a given point, thereby increasing the width of the section 244 from 8 μm to 10 μm.

In another example embodiment, the calculated width of the trace 222 at a given location is 14 μm, while the designed width of the trace at the given location is 10 μm, such that the processor must reduce the width of the trace by 4 μm. In this embodiment, the processor shifts each of the two edges of trace 222 toward the center by 2 μm at a given location.

In other embodiments, the processor may apply an asymmetric adjustment between two edges in order to comply with other design rules, such as a minimum distance between two adjacent lines. In an example where the section 244 has a calculated width of 8 μm (while the specified width in the design rule is 10 μm), the processor may, for example, shift one edge up to 0.5 μm away from the center of the section 244 and shift the other edge up to 1.5 μm in order to compensate for the 2 μm difference between the calculated width and the design rule. In yet another embodiment, the processor may only shift one edge by 2 μm, and will not move the other edges.

In other embodiments, the processor is configured to apply any other suitable adjustments to the spaces between the lines and/or strip lines and/or to the trenches and/or to other features and patterns of the object 120.

At the patterning step 312, the LDI subsystem 136 executes one or more script file patterns in order to form at least the segments 244 on the substrate 255 based on the actual routing. It should be noted that the LDI subsystem 136 prints sections 244 along actual routing rather than designed routing in order to compensate for placement errors of the device 202 and comply with design rules. The patterning step 312 ends the method of fig. 3.

Fig. 4 is a schematic explanatory diagram of a layout design of a middle section of the electronic module 200 according to an embodiment of the present invention. The layout design of FIG. 4 details the method described above for estimating placement errors of the device 202 on the substrate 255 relative to the layout design of the electronic module 200.

In some embodiments, "p" represents a point disposed on an edge of trace 222. Point p is positioned in section 244 at d from frame 220_outAt a distance and d from the frame 210_inAt a distance. In some embodiments, the processor calculates a parameter α that provides the proximity of point p to frames 210 and 220. The calculation of α is performed using equation (1):

the value of α has a range between 0 and 1. If point p is arranged at point 402, then d_inEqual to 0, so the parameter α is equal to 0. If point p is arranged at point 404, do_utEqual to 0 and therefore the parameter α is equal to 1.

In some embodiments, the processor is configured to calculate (prior to applying the design rules) the calculated routes of the sections 244 by transforming the location of the point of interest (e.g., point p) to a calculated location (referred to herein as "pcalc"). The calculation of pcalc is carried out using equation (2):

(2)p_calc＝α*p+(1-α)*T(p)

where T (p) is a transformation function, e.g., a transformation matrix. It should be noted that equation (2) applies the transformation matrix based on the proximity of point p to frames 210 and 220. Thus, if α equals 1, pcalc equals p, which means a transformation without point p. If α equals 0, then pcalc equals T (p), which means a complete transformation at point p. The transformation of a point of interest, such as point p, is shown schematically in fig. 5 below. As shown in fig. 2B, section 244 may have a linear shape, for example, disposed between the ends of sections 218 and 216 positioned on frames 210 and 220, respectively. Thus, the position of pcalc depends on α, which represents the distance of point p from frames 210 and 220.

FIG. 5 is a schematic illustration of a process sequence for calculating the actual wiring of section 244, according to an embodiment of the invention.

Reference is now made to the offline section of FIG. 5. In some embodiments, the processor receives from the database 130 designed wiring 502 that may replace the middle section of the designed section 244 arranged on the substrate 255, such as fig. 2A above. As described at panel learning step 302, the processor identifies points of interest in the design layout, such as points pdesign, p1, and p2 shown on preprocessed route 504 (which is a preprocessed version of designed route 502).

In some embodiments, the processor further identifies a minimum distance between, for example, a point pdesign located on the left edge 506 of the preprocessed wiring 504 and a closest point (referred to herein as qdesign) located on the right edge 508 of the preprocessed wiring 504 in order to calculate a designed width of the preprocessed wiring 504 (also referred to herein as "Wdesign" shown in the preprocessed wiring 504).

It should be noted that the offline steps are carried out on the design of the electronic module, but apply to all electronic modules having the same design and coupled to a respective substrate (e.g., substrate 255).

Reference is now made to the online section of FIG. 5. The online section includes a copy of the preprocessed wiring 504 that is computed by the processor in an offline step. As described above in step 304 of fig. 3, the processor receives a digital input from the registration test system for each actual electronic module (e.g., electronic module 260) that was manufactured according to the layout design of electronic module 200 but without at least the middle section of the electrical trace.

It should be noted that the following online steps are carried out for each electronic module due to different estimated errors when coupling the device to the respective substrate.

In some embodiments, the processor is configured to estimate the combined errors of shifting, rotating, and scaling relative to the layout design caused in the process of placing the device 202 on the substrate 255 based on the digital input. Based on the estimated error, the processor computes α and t (p) for each point p, and based on the computed α and t (p), the processor transforms the preprocessed data of the wiring 504 so as to form computed wiring 510 that complies with the received digital input.

In the example of fig. 5, point p1calc may correspond to a point on the middle section that is in close proximity to the intersection between the end of section 216 and frame 220 of fig. 2B above, and point p2calc may correspond to a point on the middle section that is in close proximity to the intersection between the end of section 218 and frame 210 of fig. 2B above.

As shown in fig. 2B, most of the error occurs at the edge of the device 202, and near the intersection between the end of the section 216 and the frame 220, little error is observed. Thus, point p1calc is located in close proximity to p 1. In other words, the displacement distance in the transformation of point p1 to point p1calc is almost zero.

As shown in the calculated route 510, point p2 is located closest to the device 202 on the calculated route 510, therefore, the transformation of point p2 to point p2calc includes a large displacement. Similarly, in this example, the transformation of point pdesign to pcalc includes a displacement that is greater than the transformation of point p1 to p1calc and less than the transformation of point p2 to p2 calc.

In some embodiments, the processor receives one or more polygons representing the pattern of the middle section from the transform, and searches for a point qcalc located at a minimum distance from point pcalc along the edge 508 of the respective polygon. The distance between points pcalc and qcalc is referred to herein as the calculated width, also referred to as Wcalc shown on calculated wiring 510.

The processor applies the same method to other points, such as points p1calc and p2calc, in order to generate respective points q1calc and q2calc at respective minimum distances Wcalc1 and Wcalc2, thereby calculating a complete pattern of calculated routes 510. It should be noted that at least two of the calculated widths (e.g., from among Wcalc, Wcalc1, and Wcalc 2) may be different from one another.

In some embodiments, the processor applies a set of design rules for the electronic module to the calculated routes 510 in order to verify compliance with the design rules and, if necessary, adjust the pattern of the calculated routes 510. In the example of FIG. 5, the processor checks whether the width of the calculated routes 510 complies with the specified width of the design rule. After learning the designed widths along the route 504 and applying these widths to the calculated route 510, the processor is configured to determine the direction of correction by using, for example, equation (3):

where "dir" is a unit vector showing the direction of correction from pcalc to the corresponding qcalc on edge 508 in the slope of a Cartesian (Cartesian) coordinate system.

In some embodiments, the processor is further configured to calculate the amount of correction using, for example, equation (4):

where X is the calculated amount of correction along the vector "dir" and | pcalc-qcalc | represents the absolute value of the calculated width (shown as Wcalc in FIG. 5).

It should be noted that the difference between the designed width and the calculated width is divided by 2 because the points on the two edges (i.e., edges 506 and 508) are shifted when calculating X. In other embodiments, the processor may calculate X by moving only one point (e.g., by setting the point on 506 to an anchor and moving only the point on 508, or vice versa). In these embodiments, divide by 2 will be omitted from equation (4).

The processor then applies equations (3) and (4) to a plurality of selected points (e.g., points p1calc and p2calc) along the calculated route 510, and generates the actual route 520 by verifying or adjusting at least some points of the calculated route 510.

In the example of FIG. 5, the processor settings correspond to the actual locations of pcalc and qcalc, respectively, referred to herein as pact and qact. The actual position is set to an actual width (also referred to herein as Wact as shown in actual wiring 520), where Wact complies with the design rules of the respective electronic module.

The processor also verifies or adjusts additional pairs of points (e.g., for p1act and q1act and for p2act and q2act) in order to generate the actual wiring 520.

The process sequences and methods described above are provided by way of example, and in alternative embodiments, other suitable methods may also be used. For example, interpolation or extrapolation between pre-computed exact solutions of specific shifts and rotations is performed, or traces are transformed along a warped grid based on actual positions of the die, or optimization of trace paths is performed under design rules.

FIG. 6 is a schematic illustration of a sequence of processes for generating a transformation matrix between a layout design 600 of a given electronic module and an image 620 representing the digital input of the actual generating components of the given electronic module, according to an embodiment of the invention. In some embodiments, the process sequence described herein includes a detailed description of a portion of the transformation steps generally described above at step 306 of fig. 3.

In some embodiments, the processor receives a layout design 600 from the database 130, the layout design 600 including a panel 602 having four registration marks 604 and two electronic modules 606 and 608 each having four registration marks 610 and 612, respectively. In other embodiments, the faceplate 602 and each of the electronic modules 606 and 608 may have any other suitable number of registration marks that may be different from each other. Further, electronic modules 606 and 608 may have different configurations from one another, e.g., different numbers and types of devices and/or different patterns of electrical traces.

In other embodiments, layout design 600 may have a single electronic module that includes two dies instead of electronic modules 606 and 608. The following description applies to these embodiments by using the term "die" instead of the term "electronic module".

In some embodiments, the processor receives an image 620 of the digital input from the registration testing system and/or from the AOI subsystem 132, the image 620 including a panel 622 corresponding to the panel 602 of the layout design 600. Panel 622 includes four registration marks 624 corresponding to registration marks 604, and two electronics modules 626 and 628 each having four registration marks 630 and 632, respectively. Electronic modules 626 and 628 correspond to electronic modules 606 and 608, respectively, and registration marks 630 and 632 correspond to registration marks 610 and 612, respectively, of layout design 600.

In some embodiments, the processor calculates a transformation matrix based on the aforementioned features of the layout design 600 and the image 620 in order to generate calculated routes for the intermediate sections (and optionally additional features of the respective electronic modules).

In some embodiments, the processor applies the initial transformation matrix "B" to registration mark 610 by matching between registration marks 610 and 630 in the coordinate system of electronics module 606. Similarly, the processor applies the initial transformation matrix "C" to the registration mark 612 by matching between the registration marks 612 and 632 in the coordinate system of the electronic module 608.

In some embodiments, the processor applies transformation matrix "a" to registration mark 624 of panel 622 of image 620 by matching between registration mark 624 and the location of registration mark 604 of panel 602 in the coordinate system of panel 622.

In some embodiments, the processor applies transformation matrix "a" to adjust the initial transformation matrices "B" and "C" resulting in a transformed transformation composition "AB" for generating a transformation of a point of interest for electronic module 606 and a transformed transformation composition "AC" for generating a transformation of a point of interest for electronic module 608.

FIG. 7 is a schematic illustration of a layout 700 for correcting errors between electronic devices 702 and 712 electrically coupled via a substrate 777, according to an embodiment of the invention. Substrate 777 may replace, for example, substrate 255 and each of devices 702 and 712 may replace, for example, device 202 of fig. 2B above. It should be noted that devices 702 and 712 may be similar to each other or may be different from each other.

In some embodiments, layout 700 includes a layout of at least portions of an electronic module that includes two devices instead of one as shown, for example, in fig. 2A above.

In some embodiments, layout 700 includes electrical traces 708 connected between pads 704 of device 702 and connectors 706 of substrate 777. Similarly, electrical traces 718 are disposed between the pads 714 of the device 712 and the connector 716 of the substrate 777. In some embodiments, layout 700 further includes electrical traces 710 connected between pads 704 of device 702 and pads 714 of device 712. The electrical traces 708, 710, and 718 are generally similar, but may alternatively differ from one another, for example, in length and/or width and/or material composition. For example, electrical trace 710 may be different from electrical trace 708.

As described, such as in fig. 2B above, one or more pick-and-place systems pick up the devices 702 and 712 from one or more respective tapes and couple the devices 702 and 712 to predefined respective locations on the substrate 777. The placement error of the coupling of devices 702 and 712 to substrate 777 is generally similar to the placement error described in the coupling of device 202 to substrate 255 in fig. 2B. Also, the close proximity between the devices 702 and 712 may increase (e.g., double) the magnitude of the error to be corrected by routing the electrical traces 710.

In some embodiments, the processor typically applies the same methods described above in order to estimate the error and calculate the actual wiring, but may apply a different set of allowed errors to, for example, electrical trace 708 and electrical trace 710.

In other embodiments, the processor may apply a different set of transformation matrices and/or design rules for calculating the actual routing to, for example, electrical traces 708 and 710.

In an alternative embodiment, the processor may calculate similar or alternative wiring for electrically connecting to each other directly at least some of pads 704 and 714, for example, rather than via substrate 777. In such embodiments, direct routing may be performed using the LDI process performed by the LDI subsystem 136 or any suitable manufacturing process (e.g., wire bonding).

In the example of electrical traces 710, the processor may divide each electrical trace 710 into three sections: a first section between pad 704 and physical edge 703 of device 702; a second section between the pad 714 and the physical edge 713 of the device 712; and a third section, also referred to as section 720, connected between the first section and the second section.

In some embodiments and according to the methodology described above, the processor can adjust the actual pattern of sections of electrical traces 710 between the pads (e.g., pads 704 and 714) and zone 720 in order to maintain the designed routing of these sections relative to the respective pads. The processor may calculate actual routes that correct estimated errors caused by combined errors in the placement of devices 702 and 712 relative to the layout design within region 720. Subsequently, the processor may send one or more execution files comprising at least the calculated actual routes to the LDI subsystem 136 in order to generate the actual routes for the electrical traces 710.

It should be noted that in practice, the processor calculates the actual wiring for all sections of each electrical trace 710. As described above in fig. 2B, the processor calculates the actual routing of the traces 710 that connect to the sections between the zone 720 and the pads (e.g., pads 704 and 714) so that the relative positions and orientations of these sections with respect to the respective pads 704 and 714 are maintained as in the design layout. In other words, pads 704 and 714 are displaced relative to the original design, so the segments coupled to these pads are displaced accordingly so as to firmly connect with each of pads 704 and 714.

Although the embodiments described herein primarily address the manufacture of electronic modules based on PCB and/or embedded die programs, the methods and systems described herein may also be used in other applications, such as in displays or other electronic circuits.

It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. The documents incorporated by reference into this patent application should be considered an integral part of the application except to the extent that any term is defined in such incorporated documents in a manner that conflicts with the definition explicitly or implicitly made in this specification, the definition in this specification should only be considered.