阅读说明：本技术 横向扩散金属-氧化物半导体晶体管及其形成方法 (Laterally diffused metal-oxide semiconductor transistor and forming method thereof ) 是由 S·R·梅霍特拉 B·格罗特 L·拉蒂克 于 2020-11-20 设计创作，主要内容包括：本公开涉及横向扩散金属-氧化物半导体晶体管及其形成方法。一种晶体管包括在半导体衬底中形成的沟槽,其中所述沟槽具有第一侧壁和第二侧壁。栅极区包括填充于所述沟槽中的导电材料。具有第一导电类型的漂移区邻近所述第二侧壁形成于所述半导体衬底中。漏极区形成于所述漂移区中并且与所述第二侧壁间隔开第一距离。电介质层形成于所述半导体衬底的顶表面处,覆盖所述栅极区和所述第二侧壁与所述漏极区之间的所述漂移区。场板形成于所述电介质层上方并且借助于所述电介质层与所述导电材料和所述漂移区隔离。(The present disclosure relates to laterally diffused metal-oxide-semiconductor transistors and methods of forming the same. A transistor includes a trench formed in a semiconductor substrate, wherein the trench has a first sidewall and a second sidewall. The gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent the second sidewall. A drain region is formed in the drift region and is spaced apart from the second sidewall by a first distance. A dielectric layer is formed at a top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and is isolated from the conductive material and the drift region by the dielectric layer.)

1. A transistor, comprising:

a trench formed in a semiconductor substrate, the trench having a first sidewall and a second sidewall;

a gate region including a conductive material filled in the trench;

a drift region formed in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type;

a drain region formed in the drift region, the drain region being spaced apart from the second sidewall by a first distance;

a dielectric layer formed at a top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region; and

a field plate formed over the dielectric layer, the field plate being isolated from the conductive material and the drift region by means of the dielectric layer.

2. The transistor of claim 1, in which a first edge of the field plate overlaps a portion of the gate region and a second edge of the field plate extends a second distance above the drift region, the second distance being less than the first distance.

3. The transistor of claim 1, further comprising a gate dielectric disposed at sidewalls and bottom of the trench, the gate dielectric isolating the conductive material from the semiconductor substrate.

4. The transistor of claim 1, further comprising a source region formed in the semiconductor substrate adjacent the first sidewall, a portion of the dielectric layer overlapping the source region.

5. A method, comprising:

etching a trench in a semiconductor substrate, the trench having a first sidewall and a second sidewall;

filling the trench with a conductive material to form a gate region;

forming a drift region in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type;

forming a drain region in the drift region, the drain region being spaced apart from the second sidewall by a first distance;

patterning a dielectric layer at a top surface of the semiconductor substrate to cover the gate region and the drift region between the second sidewall and the drain region; and

forming a field plate over the dielectric layer, the field plate being isolated from the conductive material and the drift region by means of the dielectric layer.

6. The method of claim 5, wherein forming the field plate comprises:

forming a vertical portion having a bottom surface in contact with a top surface of the dielectric layer and a top surface extending through an inter-layer dielectric (ILD); and

forming a horizontal portion in contact with the top surface of the vertical portion, the horizontal portion being spaced apart from the dielectric layer by the ILD.

7. The method of claim 5, further comprising forming a gate dielectric at sidewalls and bottom of the trench prior to filling the trench with the conductive material, the gate dielectric isolating the conductive material from the semiconductor substrate.

8. The method of claim 5, further comprising forming a source region in the semiconductor substrate adjacent the first sidewall, a portion of the dielectric layer overlapping the source region.

9. A transistor, comprising:

a trench formed in a semiconductor substrate, the trench having a first sidewall and a second sidewall;

a gate region including a conductive material filled in the trench;

a gate dielectric disposed at sidewalls and bottom of the trench, the gate dielectric isolating the conductive material from the semiconductor substrate;

a drift region formed in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type;

a drain region formed in the drift region, the drain region being spaced apart from the second sidewall by a first distance;

a body region formed in the semiconductor substrate adjacent the first sidewall, the body region having a second conductivity type;

a dielectric layer formed at a top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region; and

a field plate formed over the dielectric layer, the field plate being isolated from the conductive material and the drift region by means of the dielectric layer.

10. The transistor of claim 9, in which a first edge of the field plate overlaps a portion of the gate region and a second edge of the field plate extends a second distance above the drift region, the second distance being less than the first distance.

Technical Field

The present disclosure relates generally to semiconductor devices and, more particularly, to laterally diffused metal-oxide semiconductor (LDMOS) transistors and methods of forming the same.

Background

Conventional semiconductor devices and semiconductor device manufacturing processes are being developed. For example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used in a variety of different applications and electronic products-from sewing machines to washing machines, from automobiles to cell phones, and so forth. As process technologies advance, these semiconductor devices are expected to improve performance while reducing size and cost. However, there are challenges in balancing size, cost, and performance.

Disclosure of Invention

In general, there is provided a transistor comprising: a trench formed in a semiconductor substrate, the trench having a first sidewall and a second sidewall; a gate region including a conductive material filled in the trench; a drift region formed in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type; a drain region formed in the drift region, the drain region being spaced apart from the second sidewall by a first distance; a dielectric layer formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region; and a field plate formed over the dielectric layer, the field plate being isolated from the conductive material and the drift region by means of the dielectric layer. A first edge of the field plate may overlap a portion of the gate region, and a second edge of the field plate may extend a second distance above the drift region, the second distance being less than the first distance. The field plate may include a horizontal portion spaced apart from the dielectric layer by an interlayer dielectric (ILD), and a vertical portion contacting the horizontal portion near the first edge and extending from a bottom surface of the horizontal portion to a top surface of the dielectric layer. The transistor can additionally include a gate dielectric disposed at sidewalls and bottom of the trench, the gate dielectric isolating the conductive material from the semiconductor substrate. The conductive material may be formed of a polysilicon material and the field plate may be formed of a metallic material. The transistor may additionally include a source region formed in the semiconductor substrate adjacent the first sidewall, a portion of the dielectric layer overlapping the source region. The transistor may additionally include a body region of the second conductivity type formed in the semiconductor substrate adjacent the first sidewall, the source region being formed in the body region. The transistor may additionally include a salicide layer formed at a top surface of the drain and source regions, and wherein the dielectric layer is formed of a nitride material and is configured to act as a mask for the salicide layer. The transistor may additionally comprise a source terminal in contact with the source region, the source terminal being connected to the field plate by means of a metal layer.

In another embodiment, a method is provided, comprising: etching a trench in a semiconductor substrate, the trench having a first sidewall and a second sidewall; filling the trench with a conductive material to form a gate region; forming a drift region in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type; forming a drain region in the drift region, the drain region being spaced apart from the second sidewall by a first distance; patterning a dielectric layer at a top surface of the semiconductor substrate to cover the gate region and the drift region between the second sidewall and the drain region; and forming a field plate over the dielectric layer, the field plate being isolated from the conductive material and the drift region by means of the dielectric layer. A first edge of the field plate may overlap a portion of the gate region, and a second edge of the field plate may extend a second distance above the drift region, the second distance being less than the first distance. The conductive material may be formed of a polysilicon material and the field plate may be formed of a metallic material. Forming the field plate may include: forming a vertical portion having a bottom surface in contact with a top surface of the dielectric layer and a top surface extending through an inter-layer dielectric (ILD); and forming a horizontal portion in contact with a top surface of the vertical portion, the horizontal portion being spaced apart from the dielectric layer by the ILD. The method may additionally include forming a gate dielectric at sidewalls and bottom of the trench prior to filling the trench with the conductive material, the gate dielectric isolating the conductive material from the semiconductor substrate. The method may additionally include forming a source region adjacent the first sidewall in the semiconductor substrate, a portion of the dielectric layer overlapping the source region. The method may additionally include forming a body region of the second conductivity type in the semiconductor substrate adjacent the first sidewall, the source region being formed in the body region. The method may additionally include forming a gate terminal in contact with the gate region and connecting the gate terminal to the field plate by way of the metal layer.

In yet another embodiment, a transistor is provided, comprising: a trench formed in a semiconductor substrate, the trench having a first sidewall and a second sidewall; a gate region including a conductive material filled in the trench; a gate dielectric disposed at sidewalls and bottom of the trench, the gate dielectric isolating the conductive material from the semiconductor substrate; a drift region formed in the semiconductor substrate adjacent the second sidewall, the drift region having a first conductivity type; a drain region formed in the drift region, the drain region being spaced apart from the second sidewall by a first distance; a body region formed in the semiconductor substrate adjacent the first sidewall, the body region having a second conductivity type; a dielectric layer formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region; and a field plate formed over the dielectric layer, the field plate being isolated from the conductive material and the drift region by the dielectric layer. A first edge of the field plate may overlap a portion of the gate region, and a second edge of the field plate may extend a second distance above the drift region, the second distance being less than the first distance. The transistor may further comprise a source region of the first conductivity type formed in the body region adjacent the first sidewall, a portion of the dielectric layer overlapping the source region.

Drawings

The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

Fig. 1-7 illustrate, in simplified cross-sectional views, various stages of fabrication of an example laterally diffused metal-oxide semiconductor (LDMOS) transistor in accordance with an embodiment.

Fig. 8 and 9 show an exemplary LDMOS transistor at a manufacturing stage according to an embodiment in a simplified plan view.

Detailed Description

In recent years, there has been an increasing demand for smart power technologies for automotive, industrial and consumer applications, which integrate digital, analog and high voltage power transistors on a single chip, aiming to reduce manufacturing costs. In semiconductor manufacturing, silicon area is at a premium. One example of the technological improvements that occur in the trench-based transistors described herein is: silicon area affects the desirable improved on resistance area (RonA) value of the reduced power transistor.

In general, a trench-based laterally diffused metal-oxide semiconductor (LDMOS) transistor is provided. The trench formed in the semiconductor substrate is filled with a conductive material to form a gate region. A gate dielectric is formed lining the trench, isolating the gate region from the substrate. A source region is formed adjacent to the trench at the surface of the semiconductor substrate. The drain region is formed at the surface of the semiconductor substrate spaced apart from the trench by a predetermined distance. A dielectric layer is formed over the gate region and spans a predetermined distance over the drift region between the trench and the drain region. The field plate is formed over a portion of the dielectric layer. The dimensions of the field plate and the dielectric layer are selected to achieve a higher breakdown voltage and improved RonA.

Fig. 1-7 illustrate, in simplified cross-sectional views, various stages of fabrication of an example laterally diffused metal-oxide semiconductor (LDMOS) transistor 100 formed in accordance with an embodiment.

Fig. 1 shows an exemplary LDMOS transistor 100 in a manufacturing stage according to an embodiment in a simplified cross-sectional view. At this stage, the transistor 100 includes a silicon-based substrate 102, a patterned hard mask 116 formed over the substrate 102, a trench 104 formed in the substrate 102, and a gate dielectric 106 formed at the sidewalls and bottom of the trench 104. In this embodiment, the substrate 102 is formed as a P-type doped silicon substrate having a P-type conductivity type. The substrate 102 may be formed as a P-type doped silicon substrate with an N-type epitaxial layer. For example, the substrate 102 may alternatively be formed from other suitable silicon-based substrates, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, combinations thereof, and the like.

In this embodiment, an oxide layer 112 is formed on the upper substrate 102, and a nitride layer 114 is formed on the oxide layer 112. The nitride/oxide layers are patterned together to form a hard mask 116. In other embodiments, other suitable materials and combinations thereof may be used to form the hard mask 116. In this embodiment, the trench 104 includes a first sidewall 108, a second sidewall 110, and a bottom surface. For example, an etching technique such as Reactive Ion Etching (RIE) may be employed to form the trench 104. In this embodiment, a gate dielectric 106 is formed on the exposed surfaces of the trench 104, substantially lining the sidewalls 108 and 110 and bottom surface of the trench 104. The gate dielectric 106 may be formed of any suitable gate dielectric material, such as silicon dioxide. The gate dielectric 106 may be formed as a grown layer, a deposited layer, or a combination thereof.

Fig. 2 shows an example LDMOS transistor 100 in a subsequent stage of fabrication in accordance with an embodiment in a simplified cross-sectional view. At this stage, a conductive material is deposited to substantially fill the trenches 104 and form the gate regions 202. A planarization operation is performed to planarize the conductive material with the 114 layers. In this embodiment, the planarization operation may include a Chemical Mechanical Planarization (CMP) process. In other embodiments, the planarization operation may include a wet etch process. A subsequent etching operation may be performed to substantially level the conductive material with the top surface of the substrate to form the gate region 202. For example, the gate region 202 may be formed of a suitable conductive material, such as a polysilicon material or a metal material. In this embodiment, the gate region 202 is configured and arranged to serve as the gate electrode of the exemplary LDMOS transistor 100. In other embodiments, the gate region 202 may be formed of other conductive materials.

Fig. 3 shows an exemplary LDMOS transistor 100 in a subsequent manufacturing stage according to an embodiment in a simplified cross-sectional view. At this stage, a planar top surface 306 of the substrate 102 is formed, and the body region 302 and the drift region 304 are formed.

In the embodiment depicted in fig. 3, the hard mask 116 at the top surface of the substrate 102 is removed, forming a planar top surface 306. In this embodiment, the gate region 202 and the planar top surface 306 are substantially planar. In other embodiments, the gate region 202 may be slightly recessed or slightly protruding from the planar top surface 306. The gate dielectric 106 remaining in the trench serves to isolate the gate region 202 from the substrate 102.

In this embodiment, body region 302 is formed adjacent to sidewall 108 as a P-type well dopant implant region in substrate 102. The body region 302 may be characterized as a P- (minus) body region. Drift region 304 is formed adjacent to sidewall 110 as an N-type well dopant implant region in substrate 102. The drift region 304 may be characterized as an N- (minus) drift region. In some embodiments, the drift region 304 may be formed from an N-type epitaxial layer of the substrate 102.

Fig. 4 shows an example LDMOS transistor 100 in a subsequent stage of fabrication in accordance with an embodiment in a simplified cross-sectional view. At this stage, a dielectric layer 402 is formed at the top surface of the substrate 102. A dielectric layer 402 formed at the top surface of the substrate 102 is deposited and patterned to cover the gate region 202 and portions of the body region 302 and the drift region 304. In this embodiment, the dielectric layer 402 may be formed of a dielectric material (e.g., silicon nitride) suitable for acting as a self-aligned mask when forming subsequent process structures (e.g., source/drain regions, self-aligned silicide layers). The dimensions (e.g., thickness, width, length) of the dielectric layer 402 may be selected for optimal reduced surface field (RESURF).

Fig. 5 shows an example LDMOS transistor 100 in a subsequent stage of fabrication in accordance with an embodiment in a simplified cross-sectional view. At this stage, source region 502 and drain region 504 are formed, and body connection region 506 is formed. After forming the body region 302 and the drift region 304, N-type dopants are implanted to form a source region 502 and a drain region 504, respectively. Source region 502 and drain region 504 may be characterized as N + (plus) source/drain regions, respectively. Source regions 502 are formed adjacent sidewalls 108 and P-type dopants are implanted to form body connection regions 506, allowing electrical connection to body regions 302. The body connection region 506 may be characterized as a P + (plus) body connection region. In this embodiment, body contact region 506 abuts source region 502. A drain region 504 is formed spaced a lateral distance 508 from the sidewall 110. As the lateral distance 508 increases, the corresponding breakdown voltage increases. In this embodiment, for example, the lateral distance 508 between the sidewall 110 and the drain region 504 may be in the range of 0.5-10.0 microns. In some embodiments, the lateral distance 508 may be less than 0.5 microns or greater than 10.0 microns.

Fig. 6 shows an example LDMOS transistor 100 in a subsequent stage of fabrication in accordance with an embodiment in a simplified cross-sectional view. At this stage, self-aligned silicide regions 602 are formed at the top surfaces of the source and drain regions 502 and 504 and the body connection regions 506. A thin film layer of metal (e.g., titanium, platinum, tungsten) is deposited and reacted with the exposed top surfaces of the source and drain regions 502 and 504 and the body connection region 506 to form a salicide region 602. The salicide regions are used to form highly conductive contact regions at the top surfaces of the source and drain regions 502 and 504 and the body connection region 506. In this embodiment, the term salicide as used herein may also refer to self-aligned silicide.

Fig. 7 shows an example LDMOS transistor 100 in a subsequent stage of fabrication in accordance with an embodiment in a simplified cross-sectional view. At this stage, the exemplary LDMOS transistor 100 includes a contact 702, 708, an electrode terminal 710, 714, and a horizontal field plate 716. In this embodiment, the horizontal field plates 716 and contacts 708 together form a pseudo-L-shaped field plate as depicted in fig. 7.

In this embodiment, an inter-layer dielectric (ILD) region 720 is formed over the dielectric layer 402 and the salicide region 602. ILD region 720 may be formed from a series of deposited oxide layers, such as Tetraethylorthosilicate (TEOS). For example, a first oxide layer of the ILD region 720 may be deposited, patterned, and etched to expose portions of the gate region 202, the salicide region 602, and the dielectric layer 402. After patterning and etching the first oxide layer, contacts 702-708 are formed. For example, contacts 702 and 708 may be formed from any suitable conductive material such as copper, gold, silver, aluminum, nickel, tungsten, and alloys thereof. Contacts 702-706 provide conductive connections to source region 502 and body contact region 506, gate region 202, and drain region 504, respectively. The contacts 708 are formed such that the bottom surfaces of the contacts 708 abut the top surface of the dielectric layer 402. In this embodiment, the contact 708 acts as a vertical field plate portion having a first edge 718, the first edge 718 overlapping a portion of the gate region 202 at the sidewall 110.

After forming the contacts 702 and 708, a conductive layer is deposited, patterned, and etched to form electrode tips 710 and 714 and horizontal field plates 716. The electrode tip 710 and 714 and the horizontal field plate 716 may be formed of any suitable conductive material, such as copper, gold, silver, aluminum, nickel, tungsten, and alloys thereof. In this embodiment, a source electrode terminal 710 is connected to the source region 502 and the body connection region 506 by means of a contact 702 and a salicide region 602, a gate electrode terminal 712 is connected to the gate region 202 by means of a contact 704, and a drain electrode terminal 714 is connected to the drain region 504 by means of a contact 706 and a salicide region 602.

The horizontal field plates 716 are directly connected to the contacts 708, forming pseudo-L-shaped field plates. A portion of the horizontal field plate 716 overlaps the underlying drift region 304 between the gate region 202 and the drain region 504 by an overlap distance 726. The overlap distance 726 may be selected for optimal RESURF. In this embodiment, for example, the overlap distance 726 may be in the range of 40% to 60% of the lateral distance 508. In some embodiments, the overlap distance 726 may be less than 40% of the lateral distance 508 or greater than 60% of the lateral distance 508. In this embodiment, the field plate is electrically isolated from the substrate by means of a dielectric layer 402. In some embodiments, the field plate may be connected to the source electrode terminal 710 or the gate electrode terminal 712 by means of a metal interconnect layer, for example.

In the embodiment depicted in fig. 7, the electrode end 710 and 714 and the horizontal field plate 716 are formed from the same conductive layer. In other embodiments, the electrode end 710 and 714 and the horizontal field plate 716 may be formed from different conductive layers. After forming the electrode end 710-714 and the horizontal field plates 716, a subsequent oxide layer (e.g., TEOS) of the ILD region 720 may be deposited to cover the exposed surfaces of the electrode end 710-714, the horizontal field plates 716, and the first oxide layer.

Fig. 8 shows an exemplary LDMOS transistor 100 in a manufacturing stage according to an embodiment in a simplified plan view. In the embodiment depicted in fig. 8, the LDMOS transistor 100 is formed as an oval shaped transistor having a source region 802, a drain region 804, a gate region 806, and a dielectric layer 808, corresponding to the source region 502, the drain region 504, the gate region 202, and the dielectric layer 402 of fig. 7, respectively. Dielectric layer 808 is shown as a transparent region that allows underlying details to be visible. In this embodiment, the source region 802 is surrounded by a gate region 806. The drain region 804 is formed separately from the gate region 806, and the drain region 804 surrounds the gate region 806 with a lateral distance 508 as depicted in fig. 7. A dielectric layer 808 is formed covering the gate region 806, portions of the source region 802 and the drain region 804, and a drift region (not shown) between the gate region 806 and the drain region 804. Dashed outline areas 810 and 812 depict openings in dielectric layer 808. For example, the example contacts 814 provide connections to the source, drain, and gate regions 802 and 806. Features such as electrode tips and field plates are not shown.

Fig. 9 shows an exemplary LDMOS transistor 100 in a manufacturing stage according to an embodiment in a simplified plan view. In the embodiment depicted in fig. 9, the LDMOS transistor 100 of fig. 8 is shown with dielectric layer 808 being an opaque (shaded) region, thereby preventing the underlying details from being visible. In this embodiment, source region portion 902 is visible through opening 812 of dielectric layer 808, and gate region 904 is visible through opening 810 of dielectric layer 808.

It should be appreciated so far that a trench-based LDMOS transistor is provided. The trench formed in the semiconductor substrate is filled with a conductive material to form a gate region. A gate dielectric is formed lining the trench, isolating the gate region from the substrate. A source region is formed adjacent to the trench at the surface of the semiconductor substrate. The drain region is formed at the surface of the semiconductor substrate spaced apart from the trench by a predetermined distance. A dielectric layer is formed over the gate region and spans a predetermined distance over the drift region between the trench and the drain region. The field plate is formed over a portion of the dielectric layer. The dimensions of the field plate and the dielectric layer are selected to achieve a higher breakdown voltage and improved RonA.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. It is not intended that any of the benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments be construed as a critical, required, or essential feature or element of any or all the claims.

Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles.

Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other priority of such elements.