阅读说明：本技术 一种阻变存储器的故障测试方法 (Fault testing method of resistive random access memory ) 是由 蒋海军 杨建国 刘琦 于 2021-01-06 设计创作，主要内容包括：本发明涉及新型存储芯片RRAM测试技术领域,具体涉及一种阻变存储器的故障测试方法,该方法首先扫描所有的存储单元,检测出所有的故障存储单元,并标记为一级故障类型,然后依次扫描一级故障类型里的故障存储单元,标记为二级故障类型,最后输出所有存储单元故障类型一览表。本发明可以检测出阻变存储器存储单元的主要故障类型,且检测时间短,检测故障类型准确可靠,降低了阻变存储器检测故障的错判率,提高了阻变存储器的故障测试效率。(The invention relates to the technical field of novel memory chip RRAM testing, in particular to a fault testing method of a resistive random access memory. The method can detect the main fault type of the memory unit of the resistive random access memory, has short detection time and accurate and reliable fault type detection, reduces the misjudgment rate of the detection fault of the resistive random access memory, and improves the fault testing efficiency of the resistive random access memory.)

1. A fault testing method of a resistive random access memory is characterized by comprising the following steps:

s1: scanning all memory cells of the resistive random access memory, detecting all fault memory cells, and marking a primary fault type as a self fault type or a coupling fault type;

s2: scanning a fault storage unit with a primary fault type as a self fault type, and marking the fault storage unit as a secondary self fault type;

s3: scanning a fault storage unit with a primary fault type as a coupling fault type, and marking as a secondary coupling fault type;

s4: and outputting a list of the fault types of all the memory cells, namely outputting the fault type of each fault memory cell in the marked resistive random access memory.

2. The method for testing the fault of the resistive random access memory according to claim 1, wherein the step S1 specifically includes: writing all the memory cells into BIT1, repeating the execution for 2 times or more than 2 times, writing BIT0 after selecting the first memory cell, and reading the resistance values of all the memory cells in the row of the selected memory cell; respectively judging whether the resistance values of the selected memory cell and other memory cells are BIT0, and if not, respectively marking the primary fault type as a self fault type and a coupling fault type; performing reciprocating operation to finish all storage units;

writing all the memory cells into BIT0, repeatedly executing for 2 times or more, selecting the first memory cell, writing into BIT1, reading the resistance values of all the memory cells in the row of the selected memory cell, and repeatedly reading the selected memory cell for 2 times;

respectively judging whether the resistance values of the selected memory cell and other memory cells are BIT1, and if not, marking the primary fault type as a self fault type and a coupling fault type; performing reciprocating operation to finish all storage units;

the resistance value of the resistive random access memory unit corresponding to the BIT0 is in a low resistance state, the resistance value of the resistive random access memory unit corresponding to the BIT1 is in a high resistance state, and the memory unit of the resistive random access memory is selected through a decoder circuit.

3. The method for testing the fault of the resistive random access memory according to claim 2, wherein the second-level self fault types of the step S2 include a fixed fault type SA0, SA1, a state transition fault type TF0, TF1, and a read value fault type R1D.

4. The method for testing the fault of the resistive random access memory according to claim 3, wherein the step S2 specifically comprises: writing all fault memory cells with the primary fault type as the self fault type into BIT1, selecting the 1 st memory cell in the memory cells, writing BIT0 into the selected memory cell in a write pulse period which is more than or equal to 2 times, reading the resistance value of the selected memory cell, if the resistance value of the selected memory cell is BIT1, marking the fault type as fixed fault type SA1, otherwise marking the fault type as state transition fault type TF 0; performing reciprocating operation, and executing all fault storage units with the primary fault types as the self fault types; writing all fault memory cells with the primary fault type as the self fault type into BIT0, selecting the 1 st memory cell of the memory cell, writing BIT1 into the selected memory cell, repeatedly reading the resistance value of the selected memory cell for 2 times, and marking the fault type as a read value fault type R1D if the resistance values of the memory cells read for the previous 2 times are BIT1 and BIT0 respectively; when the BIT1 is written into the selected memory cell in the write pulse period which is more than or equal to 2 times, the resistance value of the selected memory cell is read, if the resistance value of the selected memory cell is BIT0, the fault type is marked as a fixed fault type SA0, and if not, the fault type is marked as a state transition fault type TF 1; and performing reciprocating operation to execute all fault storage units with the primary fault types as the self fault types.

5. The fault testing method of the resistive random access memory according to claim 2, wherein the secondary coupling fault types of the step S3 include a state coupling fault SCF0, an SCF1, and a jump coupling fault JCF0, a JCF 1.

6. The method for testing the fault of the resistive random access memory according to claim 5, wherein the step S3 specifically comprises: writing all the memory cells into BIT1, selecting the 1 st memory cell in the fault memory cells of which the primary fault type is the self fault type, writing the first memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF1 if the resistance value is BIT1, otherwise writing the selected memory cell into BIT1, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF0 if the resistance value is BIT0, otherwise writing the selected memory cell into BIT0, writing the rest memory cells into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a jump coupling fault JCF1 if the resistance value is BIT1, otherwise writing the rest memory cells into BIT0, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, and if the resistance value is BIT1, marking the fault type as a jump coupling fault JCF 1; performing reciprocating operation to finish all storage units;

writing all the memory cells into BIT0, selecting the 1 st memory cell in the fault memory cells with the primary fault type of the self fault type, writing BIT1, writing the rest memory cells in the row of the selected memory cell into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF0 if the resistance value is BIT0, otherwise writing BIT0 in the selected memory cell, writing the rest memory cells into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF1 if the resistance value is BIT1, otherwise writing BIT1 in the selected memory cell, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a jump coupling fault JCF0 if the resistance value is BIT0, otherwise writing the rest memory cells into BIT1, writing BIT0 in the rest memory cells, reading and judging the resistance value of the selected memory cell, and if the resistance value is BIT0, marking the fault type as a jump coupling fault JCF 0; and performing reciprocating operation to finish all the storage units.

7. The method for testing the fault of the resistive random access memory according to claim 1, wherein the step S4 specifically comprises: and outputting a list of fault types of each fault storage unit in the marked resistive random access memory.

Technical Field

The invention relates to the technical field of RRAM testing of novel memory chips, in particular to a fault testing method of a resistive random access memory.

Background

The resistive random access memory as a novel memory has the characteristics of high storage density, low power consumption, high reading and writing speed and long data retention time, and has great application prospect and research value. The fault testing method based on the resistive random access memory is also the focus of current research work, and the fault types of the memory unit of the resistive random access memory mainly comprise self memory faults and coupling memory faults. Along with the increase of the number of the resistive random access memory units, the time of the fault test of the resistive random access memory is multiplied, and the research and development efficiency and the production efficiency of the resistive random access memory are seriously influenced.

Disclosure of Invention

In order to solve the technical problems in the prior art, the invention designs a fault testing method of a resistive random access memory, and the specific technical scheme is as follows.

A fault testing method of a resistive random access memory comprises the following steps:

s1: scanning all memory cells of the resistive random access memory, detecting all fault memory cells, and marking a primary fault type as a self fault type or a coupling fault type;

s2: scanning a fault storage unit with a primary fault type as a self fault type, and marking the fault storage unit as a secondary self fault type;

s3: scanning a fault storage unit with a primary fault type as a coupling fault type, and marking as a secondary coupling fault type;

s4: and outputting a list of the fault types of all the memory cells, namely outputting the fault type of each fault memory cell in the marked resistive random access memory.

Further, the step S1 specifically includes: writing all the memory cells into BIT1, repeating the execution for 2 times or more than 2 times, writing BIT0 after selecting the first memory cell, and reading the resistance values of all the memory cells in the row of the selected memory cell; respectively judging whether the resistance values of the selected memory cell and other memory cells are BIT0, and if not, respectively marking the primary fault type as a self fault type and a coupling fault type; performing reciprocating operation to finish all storage units;

writing all the memory cells into BIT0, repeatedly executing for 2 times or more, selecting the first memory cell, writing into BIT1, reading the resistance values of all the memory cells in the row of the selected memory cell, and repeatedly reading the selected memory cell for 2 times;

respectively judging whether the resistance values of the selected memory cell and other memory cells are BIT1, and if not, marking the primary fault type as a self fault type and a coupling fault type; performing reciprocating operation to finish all storage units;

the resistance value of the resistive random access memory unit corresponding to the BIT0 is in a low resistance state, the resistance value of the resistive random access memory unit corresponding to the BIT1 is in a high resistance state, and the memory unit of the resistive random access memory is selected through a decoder circuit.

Further, the secondary self-fault types of step S2 include fixed fault types SA0 and SA1, state transition fault types TF0 and TF1, and read value fault type R1D.

Further, the step S2 specifically includes: writing all fault memory cells with the primary fault type as the self fault type into BIT1, selecting the 1 st memory cell in the memory cells, writing BIT0 into the selected memory cell in a write pulse period which is more than or equal to 2 times, reading the resistance value of the selected memory cell, if the resistance value of the selected memory cell is BIT1, marking the fault type as fixed fault type SA1, otherwise marking the fault type as state transition fault type TF 0; performing reciprocating operation, and executing all fault storage units with the primary fault types as the self fault types; writing all fault memory cells with the primary fault type as the self fault type into BIT0, selecting the 1 st memory cell of the memory cell, writing BIT1 into the selected memory cell, repeatedly reading the resistance value of the selected memory cell for 2 times, and marking the fault type as a read value fault type R1D if the resistance values of the memory cells read for the previous 2 times are BIT1 and BIT0 respectively; when the BIT1 is written into the selected memory cell in the write pulse period which is more than or equal to 2 times, the resistance value of the selected memory cell is read, if the resistance value of the selected memory cell is BIT0, the fault type is marked as a fixed fault type SA0, and if not, the fault type is marked as a state transition fault type TF 1; and performing reciprocating operation to execute all fault storage units with the primary fault types as the self fault types.

Further, the secondary coupling fault types of the step S3 include a state coupling fault SCF0, an SCF1, and a jump coupling fault JCF0, a JCF 1.

Further, the step S3 specifically includes: writing all the memory cells into BIT1, selecting the 1 st memory cell in the fault memory cells of which the primary fault type is the self fault type, writing the first memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF1 if the resistance value is BIT1, otherwise writing the selected memory cell into BIT1, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF0 if the resistance value is BIT0, otherwise writing the selected memory cell into BIT0, writing the rest memory cells into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a jump coupling fault JCF1 if the resistance value is BIT1, otherwise writing the rest memory cells into BIT0, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, and if the resistance value is BIT1, marking the fault type as a jump coupling fault JCF 1; performing reciprocating operation to finish all storage units;

writing all the memory cells into BIT0, selecting the 1 st memory cell in the fault memory cells with the primary fault type of the self fault type, writing BIT1, writing the rest memory cells in the row of the selected memory cell into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF0 if the resistance value is BIT0, otherwise writing BIT0 in the selected memory cell, writing the rest memory cells into BIT0, reading and judging the resistance value of the selected memory cell, marking the fault type as a state coupling fault SCF1 if the resistance value is BIT1, otherwise writing BIT1 in the selected memory cell, writing the rest memory cells into BIT1, reading and judging the resistance value of the selected memory cell, marking the fault type as a jump coupling fault JCF0 if the resistance value is BIT0, otherwise writing the rest memory cells into BIT1, writing BIT0 in the rest memory cells, reading and judging the resistance value of the selected memory cell, and if the resistance value is BIT0, marking the fault type as a jump coupling fault JCF 0; and performing reciprocating operation to finish all the storage units.

Further, the step S4 is specifically: and outputting a list of fault types of each fault storage unit in the marked resistive random access memory.

The invention has the following beneficial effects: the method can detect the main fault type of the resistive random access memory storage unit, has short detection time and accurate and reliable fault type detection, reduces the misjudgment rate of the resistive random access memory detection fault and improves the fault testing efficiency of the resistive random access memory.

Drawings

FIG. 1 is a schematic test flow diagram of the present invention;

FIG. 2 is a flowchart illustrating step S1 of the present invention;

FIG. 3 is a flowchart illustrating step S2 of the present invention;

fig. 4 is a flowchart illustrating step S3 according to the present invention.

Detailed Description

In order to make the objects, technical solutions and technical effects of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.

As shown in fig. 1 to 4, a method for testing a fault of a resistive random access memory includes the following steps:

s1: and scanning all memory cells of the resistive random access memory, detecting all fault memory cells, and marking the first-stage fault type as a self fault type or a coupling fault type.

Specifically, in order to reduce the time for detecting the fault of the resistive random access memory, all normal memory cells are filtered out first, and the method specifically comprises the following steps:

s101: writing all the memory cells into BIT1, and repeating for 2 times or more;

s102: selecting a first storage unit in all the storage units;

s103: writing BIT0 into the selected memory cell and reading the resistance of all memory cells in the row of the selected memory cell;

s104: judging whether the resistance value of the selected memory cell is BIT0, if not BIT0, marking the primary fault type as the self fault type; reading the resistance value of the selected memory cell, judging whether the resistance value range of BIT0 belongs to the memory cell, and marking the fault type of the memory cell as the self fault type below the first-level fault type if the resistance value range does not belong to the resistance value range;

s105: judging whether the resistance values of other memory cells are BIT0, if not, marking the primary fault type as a coupling fault type; reading the resistance values of other memory cells in the row of the selected memory cell, judging whether the resistance value range of BIT0 belongs to the other memory cells, and if the resistance value range does not belong to the other memory cells, marking that the fault type of the memory cell belongs to the coupling fault type below the first-level fault type;

s106: repeating the steps S102-S105, and executing all the storage units;

s107: writing all the memory cells into BIT0, and repeating for 2 times or more;

s108: selecting a first storage unit in all the storage units;

s109: writing BIT1 into the selected memory cell, reading the resistance values of all memory cells in the row of the selected memory cell, and repeatedly reading the selected memory cell for 2 times;

s110: judging whether the resistance value of the selected memory cell is BIT1, if not BIT1, marking the primary fault type as the self fault type; reading the resistance value of the selected memory cell, judging whether the resistance value range of BIT1 belongs to the memory cell, and marking the fault type of the memory cell as the self fault type below the first-level fault type if the resistance value range does not belong to the resistance value range;

s111: judging whether the resistance values of other memory cells are BIT1, if not, marking the primary fault type as a coupling fault type; reading the resistance value of the selected memory cell, judging whether the resistance value range of BIT1 belongs to the memory cell, and if the resistance value range does not belong to the resistance value range, marking the fault type of the memory cell as the coupling fault type below the first-level fault type;

s112: and repeating the steps S108 to S111, and finishing all the storage units.

The resistance value of the resistive random access memory unit corresponding to the BIT0 is in a low resistance state, the resistance value of the resistive random access memory unit corresponding to the BIT1 is in a high resistance state, and the memory unit of the resistive random access memory is selected through the decoder circuit.

S2: and scanning the fault storage unit with the primary fault type as the self fault type, and marking the fault storage unit as the secondary self fault type.

The second-level self fault types comprise fixed fault types SA0 and SA1, state transition fault types TF0 and TF1, and a read value fault type R1D. Specifically, in order to detect which self fault type the fault type of the fault storage unit is, the method specifically includes the following steps:

s201: writing all fault storage units with the primary fault types as the self fault types into BIT 1;

s202: selecting the 1 st storage unit in the storage units with all the primary fault types as the self fault types;

s203: writing BIT0 into the selected memory cell in a write pulse period which is more than or equal to 2 times, and reading the resistance value of the selected memory cell;

s204: if the resistance value of the selected memory cell is BIT1, marking the fault type as a fixed fault type SA1, otherwise marking the fault type as a state transition fault type TF 0;

s205: repeating the steps S202-204, and executing all fault storage units with the primary fault type as the self fault type;

s206: writing all fault storage units with the primary fault types as the self fault types into BIT 0;

s207: selecting 1 st storage unit of storage units with all primary fault types as self fault types;

s208: writing BIT1 into the selected memory cell and repeatedly reading the resistance value of the selected memory cell for 2 times;

s209: if the resistance values of the memory cells read in the previous 2 times are BIT1 and BIT0 respectively, marking the fault type as a read value fault type R1D;

s210: writing BIT1 into the selected memory cell in a write pulse period which is more than or equal to 2 times, and reading the resistance value of the selected memory cell;

s211: if the resistance value of the selected memory cell is BIT0, marking the fault type as a fixed fault type SA0, otherwise marking the fault type as a state transition fault type TF 1;

s212: and repeating the steps S207-211, and executing all fault storage units with the primary fault type as the self fault type.

S3: and scanning the fault storage unit with the primary fault type as the coupling fault type, and marking the fault storage unit as the secondary coupling fault type.

The secondary coupling fault types comprise state coupling faults SCF0 and SCF1, and jump coupling faults JCF0 and JCF 1. Specifically, in order to detect which coupling fault type the fault type of the faulty storage unit is, the method specifically includes the following steps:

s301: write all memory cells to BIT 1;

s302: selecting 1 st storage unit in the fault storage units with all the primary fault types as the self fault types;

s303: writing the selected memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT1, and reading and judging the resistance value of the selected memory cell;

s304: if the resistance value is BIT1, marking the fault type as state coupling fault SCF 1;

s305: otherwise, writing the selected memory cell into BIT1, writing the rest memory cells in the row of the selected memory cell into BIT1, and reading and judging the resistance value of the selected memory cell;

s306: if the resistance value is BIT0, marking the fault type as state coupling fault SCF 0;

s307: otherwise, writing the selected memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT0, and reading and judging the resistance value of the selected memory cell;

s308: if the resistance value is BIT1, marking the fault type as jump coupling fault JCF 1;

s309: otherwise, writing the selected memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT1, and reading and judging the resistance value of the selected memory cell;

s310: if the resistance value is BIT1, marking the fault type as jump coupling fault JCF 1;

s311: repeating the steps S302-S310, and finishing all the storage units;

s312: write all memory cells to BIT 0;

s313: selecting 1 st storage unit in the fault storage units with all the primary fault types as the self fault types;

s314: writing the selected memory cell into BIT1, writing the rest memory cells in the row of the selected memory cell into BIT0, and reading and judging the resistance value of the selected memory cell;

s315: if the resistance value is BIT0, marking the fault type as state coupling fault SCF 0;

s316: otherwise, writing the selected memory cell into BIT0, writing the rest memory cells in the row of the selected memory cell into BIT0, and reading and judging the resistance value of the selected memory cell;

s317: if the resistance value is BIT1, marking the fault type as state coupling fault SCF 1;

s318: otherwise, writing the selected memory cell into BIT1, writing the rest memory cells in the row of the selected memory cell into BIT1, and reading and judging the resistance value of the selected memory cell;

s319: if the resistance value is BIT0, marking the fault type as jump coupling fault JCF 0;

s320: otherwise, writing the selected memory cell into BIT1, writing the rest memory cells in the row of the selected memory cell into BIT0, and reading and judging the resistance value of the selected memory cell;

s321: if the resistance value is BIT0, marking the fault type as jump coupling fault JCF 0;

s322: and repeating the steps S313 to S321 to finish all the memory units.

S4: and outputting a list of all the memory cell fault types, and outputting a part of fault types marking each fault memory cell in the resistive random access memory after the test is finished so as to provide the resistive random access memory for a resistive random access designer to analyze and count the fault conditions.

The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.