阅读说明：本技术 一种时钟产生电路及方法、模拟数字转换器和存储介质 (Clock generation circuit and method, analog-digital converter and storage medium ) 是由 付凯 于 2020-05-26 设计创作，主要内容包括：本发明涉及一种时钟产生电路,包括多路时钟信号发生器,每路时钟信号发生器包括：PMOS管,其连接到基准时钟信号,并且受第一选择信号控制而通断；第一NMOS管,其经由时钟连线连接到所述PMOS管,并且受第二选择信号控制而通断,其中根据所述时钟连线引出该路的时钟信号；以及第二NMOS管,其一端连接到所述第一NMOS管另一端接地,并且受所述基准时钟信号控制而通断。(The invention relates to a clock generating circuit, comprising a plurality of clock signal generators, each clock signal generator comprises: the PMOS tube is connected to the reference clock signal and is switched on and off under the control of the first selection signal; the first NMOS tube is connected to the PMOS tube through a clock connecting line and is controlled by a second selection signal to be switched on and off, and the clock signal of the first NMOS tube is led out according to the clock connecting line; and one end of the second NMOS tube is connected to the other end of the first NMOS tube and is grounded, and the second NMOS tube is controlled by the reference clock signal to be switched on and off.)

1. A clock generation circuit, comprising a plurality of clock signal generators, each clock signal generator comprising:

the PMOS tube is connected to the reference clock signal and is switched on and off under the control of the first selection signal;

the first NMOS tube is connected to the PMOS tube through a clock connecting line and is controlled by a second selection signal to be switched on and off, and the clock signal of the first NMOS tube is led out according to the clock connecting line; and

and one end of the second NMOS tube is connected to the other end of the first NMOS tube and is grounded, and the second NMOS tube is controlled by the reference clock signal to be switched on and off.

2. The clock generation circuit of claim 1, wherein:

the first selection signal is connected to the G pole of the PMOS tube, the second selection signal is connected to the G pole of the first NMOS tube, and the reference clock signal is connected to the G pole of the second NMOS tube; and

the reference clock signal is connected to the S pole of the PMOS tube, the D pole of the PMOS tube is connected to the D pole of the first NMOS tube through the clock connecting line, the S pole of the first NMOS tube is connected to the D pole of the second NMOS tube, and the S pole of the second NMOS tube is grounded.

3. The clock generation circuit according to claim 1 or 2, further comprising a buffer circuit, wherein the reference clock signal is connected to the PMOS transistor via the buffer circuit.

4. The clock generation circuit of claim 3, wherein the clock signal of the channel is determined in time sequence from a position in the reference clock signal of a falling edge of the first selection signal and a rising edge of the second selection signal.

5. The clock generation circuit of claim 4, wherein a falling edge of the first selection signal and a rising edge of the second selection signal are temporally located in different periods of the reference clock signal.

6. The clock generation circuit of claim 5, wherein the pulse width of the first selection signal and the pulse width of the second selection signal are close to the pulse width of the reference clock signal.

7. An analog-to-digital converter, characterized in that it comprises a clock generation circuit according to any one of claims 1-6.

8. A clock generation circuit, comprising a multi-way clock signal generator, a selection signal generator, wherein:

the selection signal generator is configured to generate a first selection signal and a second selection signal for each path;

each clock signal generator comprises:

a PMOS tube which is connected to a reference clock signal and is switched on and off under the control of the first selection signal;

the first NMOS tube is connected to the PMOS tube through a clock connecting line and is controlled by the second selection signal to be switched on and off, and the clock signal of the first NMOS tube is led out according to the clock connecting line; and

and one end of the second NMOS tube is connected to the other end of the first NMOS tube and is grounded, and the second NMOS tube is controlled by the reference clock signal to be switched on and off.

9. A method of clock generation, said method generating a plurality of clock signals, each clock signal generated by:

controlling the on-off of a PMOS tube through a first selection signal, wherein one end of the PMOS tube is connected to a reference clock signal;

controlling the on-off of a first NMOS tube through a second selection signal, wherein the first NMOS tube is connected to the PMOS tube through a clock connecting wire;

controlling the on-off of a second NMOS tube through the reference clock signal, wherein one end of the second NMOS tube is connected to the other end of the first NMOS tube, and the other end of the second NMOS tube is grounded; and

and leading out the clock signal of the path according to the clock connecting line.

10. The method of claim 9, wherein the clock signal of the way is determined in time sequence from a position in the reference clock signal of a falling edge of the first select signal and a rising edge of the second select signal.

11. The method of claim 10, wherein a falling edge of the first selection signal and a rising edge of the second selection signal are temporally located in different periods of the reference clock signal.

12. The method of claim 11, wherein a pulse width of the first selection signal and a pulse width of the second selection signal are close to a pulse width of the reference clock signal.

13. A computer-readable storage medium having instructions stored therein, which when executed by a processor, cause the processor to perform the method of any one of claims 9-12.

Technical Field

The present invention relates to a clock generation circuit, a clock generation method, an analog-to-digital converter, and a computer-readable storage medium, and more particularly, to a mechanism for accurately generating a clock signal.

Background

The clock circuit is the basis for normal operation of digital circuits and the like, and the accuracy of the clock signal directly influences the stability of subsequent processing. Particularly, for a clock dividing circuit, clock division capable of obtaining a stable and accurate phase is desirable. However, since the electrical characteristics of the frequency-dividing circuits are determined by the devices constituting the respective frequency-dividing circuits, it is difficult to ensure the identity of all the devices. Especially in the case of signals processed through multiple devices, the accumulated error will significantly affect the phase of the clock division.

Disclosure of Invention

In view of the above-mentioned problems, the present application aims to provide a mechanism capable of sharing components of a clock generation circuit to the maximum extent, specifically:

according to an aspect of the present invention, there is provided a clock generation circuit including multiple clock signal generators, each clock signal generator including: the PMOS tube is connected to the reference clock signal and is switched on and off under the control of the first selection signal; the first NMOS tube is connected to the PMOS tube through a clock connecting line and is controlled by a second selection signal to be switched on and off, and the clock signal of the first NMOS tube is led out according to the clock connecting line; and one end of the second NMOS tube is connected to the other end of the first NMOS tube and is grounded, and the second NMOS tube is controlled by the reference clock signal to be switched on and off.

In some embodiments of the present application, optionally, the first selection signal is connected to the G pole of the PMOS transistor, the second selection signal is connected to the G pole of the first NMOS transistor, and the reference clock signal is connected to the G pole of the second NMOS transistor; and the reference clock signal is connected to the S pole of the PMOS tube, the D pole of the PMOS tube is connected to the D pole of the first NMOS tube through the clock connecting line, the S pole of the first NMOS tube is connected to the D pole of the second NMOS tube, and the S pole of the second NMOS tube is grounded.

In some embodiments of the present application, optionally, the clock generation circuit further includes a buffer circuit, and the reference clock signal is connected to the PMOS transistor via the buffer circuit.

In some embodiments of the present application, optionally, the clock signal of the channel is determined according to a position in the reference clock signal in a timing manner of a falling edge of the first selection signal and a rising edge of the second selection signal.

In some embodiments of the present application, optionally, a falling edge of the first selection signal and a rising edge of the second selection signal are located in different periods of the reference clock signal in terms of time sequence.

In some embodiments of the present application, optionally, a pulse width of the first selection signal and a pulse width of the second selection signal are close to a pulse width of the reference clock signal.

In some embodiments of the present application, optionally, the clock generation circuit comprises a four-way clock signal generator.

According to an aspect of the present invention, there is provided an analog-to-digital converter comprising any one of the clock generation circuits as described above.

According to an aspect of the present invention, there is provided a clock generation circuit including a multipath clock signal generator, a selection signal generator, wherein: the selection signal generator is configured to generate a first selection signal and a second selection signal for each path; each clock signal generator comprises: a PMOS tube which is connected to a reference clock signal and is switched on and off under the control of the first selection signal; the first NMOS tube is connected to the PMOS tube through a clock connecting line and is controlled by the second selection signal to be switched on and off, and the clock signal of the first NMOS tube is led out according to the clock connecting line; and one end of the second NMOS tube is connected to the other end of the first NMOS tube and is grounded, and the second NMOS tube is controlled by the reference clock signal to be switched on and off.

According to an aspect of the present invention, there is provided a clock generating method for generating a plurality of clock signals, each clock signal being generated by: controlling the on-off of a PMOS tube through a first selection signal, wherein one end of the PMOS tube is connected to a reference clock signal; controlling the on-off of a first NMOS tube through a second selection signal, wherein the first NMOS tube is connected to the PMOS tube through a clock connecting wire; controlling the on-off of a second NMOS tube through the reference clock signal, wherein one end of the second NMOS tube is connected to the other end of the first NMOS tube, and the other end of the second NMOS tube is grounded; and leading out the clock signal of the path according to the clock connecting line.

In some embodiments of the present application, optionally, the clock signal of the channel is determined according to a position in the reference clock signal in a timing manner of a falling edge of the first selection signal and a rising edge of the second selection signal.

In some embodiments of the present application, optionally, a falling edge of the first selection signal and a rising edge of the second selection signal are located in different periods of the reference clock signal in terms of time sequence.

In some embodiments of the present application, optionally, a pulse width of the first selection signal and a pulse width of the second selection signal are close to a pulse width of the reference clock signal.

In some embodiments of the present application, optionally, the method generates four clock signals.

According to another aspect of the present invention, there is provided a computer-readable storage medium having stored therein instructions which, when executed by a processor, cause the processor to perform any one of the methods of updating a file as described above.

Drawings

The above and other objects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like or similar elements are designated by like reference numerals.

FIG. 1 shows a clock generation circuit according to one embodiment of the invention.

Fig. 2 shows a clock generation circuit according to an embodiment of the invention.

Fig. 3 shows a clock generation circuit according to an embodiment of the invention.

FIG. 4 illustrates an example timing diagram of a clock generation circuit according to one embodiment of this disclosure.

Fig. 5 shows an analog-to-digital converter according to the prior art.

Fig. 6 shows an analog-to-digital converter according to the prior art.

Fig. 7 shows a timing diagram of an analog-to-digital converter according to the prior art.

Fig. 8 shows a clock generation circuit according to the prior art.

Fig. 9 illustrates a clock generation method according to an embodiment of the present invention.

Detailed Description

For the purposes of brevity and explanation, the principles of the present invention are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equally applicable to all types of clock generation circuits, clock generation methods, analog-to-digital converters, and computer-readable storage media, and that these same or similar principles may be implemented therein, with any such variations not departing from the true spirit and scope of the present patent application.

Analog-to-digital converters (ADCs) are a type of device that converts an analog signal to a digital signal. Fig. 5 shows an analog-to-digital converter according to the prior art, which is a typical pipeline structure analog-to-digital converter. Compared with analog-digital converters with other structures, the analog-digital converter with the pipeline structure has the greatest advantages of good balance in the aspects of precision, speed, power consumption and the like, and is high in precision, high in conversion speed, low in power consumption and small in chip area, so that the analog-digital converter with the pipeline structure is more and more widely applied to the high-speed and high-precision fields of wireless communication, digital video and the like. The analog-to-digital converter 50 shown in FIG. 5 includes multiple stages of pipeline-502, 504, … …, 506, and 508, each stage of pipeline being controlled by a clock signal CK (or CK). The input signal VIN is passed through the pipeline 502 to produce the Most Significant Bit (MSB), … …, and through the pipeline 508 to produce the Least Significant Bit (LSB). If each stage of pipeline can generate data of m bits, n stages of cascade connection can generate data of m × n bits.

On the other hand, in order to increase the speed of the analog-digital converter, a time interleaving method is also commonly used in the art. Fig. 6 shows an analog-to-digital converter according to the prior art, the analog-to-digital converter 60 comprising a plurality of channels 601, … …, 60N, each of which may be constituted, for example, by the analog-to-digital converter 50 shown in fig. 5, the individual channels being subject to their sampling clock CK_i(i = 1, … …, N) to determine whether to turn on. The channels 601, … …, 60N produce the channel-converted digital signal D₁-D_NThe multiplexer MUX combines these signals into D_outAnd (6) outputting. As shown in the figure, adoptSample clock CK_i(i = 1, … …, N) may be generated, for example, using a PLL phase-locked loop or DLL phase-locked loop circuit. Assuming that the sampling rate of each channel is F, the total sampling rate after N-way interleaving is F = F × N.

FIG. 7 shows a possible timing diagram, CK, of the analog-to-digital converter 60 shown in FIG. 6_i(i = 1, … …, N) is a sampling clock of each channel, and ideally, the phase difference of the sampling clocks of two adjacent channels is 2 pi/N. Since the characteristics of the elements of each channel are not completely identical, there is a phase difference (time skew) between the actual clock and the ideal clock, which generates harmonics on the output spectrum of the adc 60, the harmonic energy being proportional to the product of the phase difference and the input frequency. Therefore, for a time-interleaved analog-to-digital converter of a high sampling rate, it is necessary to make the phase difference of the clock generation circuit as small as possible.

Fig. 8 shows a clock generation circuit according to the prior art, and the clock generation circuit 80 is composed of three D flip-flops 801, 802, and 803, and the connection relationship is shown in the figure. The clock generating circuit 80 is inputted with a clock signal CKIN which four divided clocks (CKD _0, CKD _90, CKD _180, and CKD _ 270) can be generated, wherein the clocks CKD _0, CKD _90, CKD _180, and CKD _270 are 90 ° out of phase. As described above, since the characteristics are not completely uniform between the elements of the respective channels, there is a phase difference between the actual clock and the ideal clock. For example, during the manufacturing process of the chip, due to the existence of non-ideal factors, a large mismatch (mismatch) exists among the D flip-flops 801, 802 and 803, which may cause a large phase difference between the generated four-way clock and the ideal clock.

According to an aspect of the present invention, there is provided a clock generation circuit 10 as shown in fig. 1. The clock generation circuit 10 includes multiple clock signal generators (e.g., 101, … …, 10N), wherein each clock signal generator includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor, and so on. For example, the clock signal generator 101 (1 st path) includes a PMOS transistor 1011, a first NMOS transistor 1012, and a second NMOS transistor 1013.

As shown, the PMOS transistor 1011 in the 1 st channel is connected to the reference clock signal and is turned on/off by the first selection signal, that is, the first selection signal can control the turning on/off of the PMOS transistor 1011, so as to selectively allow the signal to pass through the PMOS transistor 1011. The first NMOS transistor 1012 is connected to the PMOS transistor through a clock line and is turned on/off by a second selection signal, i.e., the second selection signal can control the turning on/off of the first NMOS transistor 1012, so as to selectively allow the signal to pass through the first NMOS transistor 1012. Wherein the clock signal generated by the path can be pulled out according to the clock connection. In some examples of the invention, the clock line may be a pin of the PMOS transistor 1011 or the first NMOS transistor 1012, which is abstracted as a "clock line" since it carries a clock signal to be output. In other examples of the invention, the clock connection may be a connection that actually exists to effect electrical coupling. The signals from the clock wires are used as the clock signals output by the circuit, and the clock signal combination generated by each clock signal generator can be used for the analog-digital converter and the like as described above. In some examples, the devices receiving the respective clock signals may operate triggered by edges or levels of the clock signals, and in particular may operate triggered by rising edges of the clock signals, for example.

With continued reference to fig. 1, one end of the second NMOS 1013 of the 1 st way is connected to the first NMOS 1012, and the other end of the second NMOS 1013 may be grounded. The second NMOS tube 1013 is turned on and off by the reference clock signal, that is, the reference clock signal can control the turning on and off of the second NMOS tube 1013, so that the signal can be selectively allowed to pass through the second NMOS tube 1013.

As can be seen from the above, the reference clock signal not only serves as the input of the PMOS transistor 1011, but also controls the on/off of the second NMOS transistor 1013. The first selection signal, the second selection signal and the reference clock signal are operated according to a predetermined format to control the PMOS 1011, the first NMOS 1012 and the second NMOS 1013, thereby generating a 1 st path clock signal of a predetermined format. Similarly, we can also generate the 2 nd, 3 rd, … … th, N-way clock signals in a given form, and the phase difference between these signals can be 2 pi/N for example. Because the PMOS tubes of each path can be triggered by low level, the edge (for example, rising edge) of each path of clock signal can be only affected by the on-off of the PMOS tube and the reference clock signal by designing the control signal of each MOS tube. On the other hand, since the reference clock signal is common to the respective channels, in practice, the edge (e.g., rising edge) of each channel clock signal is affected only by the switching of the PMOS transistor. In addition, the PMOS transistor can be guaranteed to be in a correct on-off state at the edge of the reference clock signal, i.e., the edge (e.g., rising edge) of each clock signal can be guaranteed to always depend on the edge of the reference clock signal. Thus, even though there may be manufacturing variations among the PMOS transistors, the clock signals may ensure edge (e.g., rising edge) accuracy in timing, which may ensure clock accuracy for subsequent devices such as those triggered by clock edges.

In some embodiments of the present application, the pin connections of the PMOS transistor, the first NMOS transistor, and the second NMOS transistor may be arranged in a usual manner. For example, a first selection signal may be connected to the G pole of a PMOS transistor, a second selection signal may be connected to the G pole of a first NMOS transistor, and a reference clock signal may be connected to the G pole of a second NMOS transistor. The reference clock signal is connected to the S pole of the PMOS tube, the D pole of the PMOS tube is connected to the D pole of the first NMOS tube through a clock connection line, the S pole of the first NMOS tube is connected to the D pole of the second NMOS tube, and the S pole of the second NMOS tube is grounded. As such, in some examples of the invention, when the first selection signal is low, the PMOS transistor is turned on; when the second selection signal is at a high level, the first NMOS tube is conducted; when the reference clock signal is at a high level, the second NMOS transistor is turned on.

In some embodiments of the present application, the clock generation circuit further includes a buffer circuit, and the reference clock signal is connected to the PMOS transistor via the buffer circuit. A buffer circuit in the context of the present invention may implement a certain delay of the input signal, e.g. may delay by one clock cycle. The provision time for analyzing the reference clock signal can be provided by introducing a buffer circuit. As shown in fig. 2, the clock generation circuit 20 includes a buffer circuit 202, in addition to the same components as those in the example shown in fig. 1, the reference clock signal is connected to the PMOS transistor of each channel via the buffer circuit 202, and the second NMOS transistor of each channel may be directly driven by the reference clock signal. As shown, in some examples of the invention, the buffer circuit 202 may be composed of a cascade of two inverters.

In some embodiments of the present application, the clock signal of the way is determined in time sequence relative to a position in the reference clock signal according to a falling edge of the first selection signal and a rising edge of the second selection signal. FIG. 4 illustrates an example timing diagram of a clock generation circuit according to one embodiment of this disclosure. Wherein CKIN is a reference clock signal and CKD is the reference clock signal processed by the buffer circuit (which differs from CKIN by one clock cycle). CKSEL _ P1 represents a first select signal supplied to the PMOS transistor of way 1, CKSEL _ N1 represents a second select signal supplied to the first NMOS transistor of way 1, and so on. In FIG. 4, the control signals of the 4 clock generation circuits are shown, and CKS1-CKS4 are the clock signals generated by the 4 clock generation circuits. As illustrated in fig. 4, the falling edge position of the low level segment of CKS1 substantially corresponds to the rising edge of the reference clock signal CKIN (time t 2), because CKIN will remain high after the rising edge, and thus the second NMOS transistor of path 1 will be turned on; in addition, since CKSEL _ N1 is at high level at time t1-t3, the first NMOS transistor of the 1 st channel will also be turned on. Returning to fig. 1 or fig. 2, the first clock signal is pulled down to the same potential as GND. Thereafter, the first NMOS transistor or the second NMOS transistor is turned off, which will not affect the voltage level on the clock line, i.e., CKS1 will remain low. However, when CKSEL _ P1 goes low, the PMOS transistor is turned on, and if CKD goes high, CKS1 also transitions. As shown, CKS1 transitions from low to high at time t 5. It can be seen that the rising edge position of CKS1 is only related to the conduction of the PMOS transistor of the 1 st channel and CKD, and so on, the rising edge position of CKS2 is only related to the conduction of the PMOS transistor of the 2 nd channel and CKD, the rising edge position of CKS3 is only related to the conduction of the PMOS transistor of the 3 rd channel and CKD, and the rising edge position of CKS4 is only related to the conduction of the PMOS transistor of the 4 th channel and CKD. Since the CKD signal is maintained in a stable period, the rising edge positions of CKS1, CKS2, CKS3 and CKS4 are actually related to the conduction time of the PMOS transistors of the 1 st, 2 nd, 3 th and 4 th paths. For example, the rising edge of CKS3 shown in FIG. 4 (in the circle) is only relevant to the low level position of CKSEL _ P3 (in the circle). In other words, the rising edge positions of CKS1, CKS2, CKS3 and CKS4 are only related to the electrical characteristics of the PMOS transistors of the 1 st, 2 nd, 3 rd and 4 th paths.

In some embodiments of the present application, a falling edge of the first selection signal and a rising edge of the second selection signal are temporally located in different periods of the reference clock signal. As shown in fig. 4, in order to make the clock pulse segments output by CKS1 and the like occupy one period of the reference clock signal, the falling edge of the first selection signal and the rising edge of the second selection signal are located in adjacent periods of the reference clock signal in time sequence (specifically, for example, at low potential of adjacent periods of CKIN shown in the figure). Setting in this manner may cause CKSEL _ N1 to be high at one rising edge of the clock and CKSEL _ P1 to be high at the next rising edge. Of course, if the output clock is to have another shape, the positions of the falling edge of the first selection signal and the rising edge of the second selection signal of each channel relative to the reference clock signal may be further adjusted as needed (for example, the two are separated by about two reference clock cycles).

In some embodiments of the present application, the pulse width of the first selection signal and the pulse width of the second selection signal are close to the pulse width of the reference clock signal. The pulse width of the reference clock signal referred to in the context of this document refers to the half period of the reference clock signal (duty cycle 50%). This setting is for the convenience of setting the positional relationship of the first selection signal, the second selection signal, and the reference clock signal in terms of timing. Of course, it is also possible that the pulse width of the first selection signal and the pulse width of the second selection signal are slightly smaller than the reference clock signal, but a smaller pulse width would be disadvantageous for capturing the edges of the reference clock signal. Generally, a select signal larger than the pulse width of the reference clock signal may not be used, which may cause a malfunction in the circuit logic.

In some embodiments of the present application, the clock generation circuit includes a four-way clock signal generator. Fig. 3 shows a clock generation circuit 30 according to one embodiment of the present invention, which includes clock signal generators 301, 302, 303, and 304 to generate the 1 st, 2 nd, 3 th, and 4 th clock signals, respectively. Similarly, the embodiment corresponding to fig. 4 is also described with a clock generation circuit including a four-way clock signal generator.

According to an aspect of the present invention, there is provided an analog-to-digital converter comprising a clock generation circuit as any one of the above. For example, clock signal CK in the example described in FIG. 6 of the present application₁-CK_NThe clock generation circuit may be any one of the clock generation circuits described above, and accordingly, the clock generation circuit includes N clock signal generators.

According to an aspect of the present invention, a clock generation circuit is provided, which includes a multi-path clock signal generator and a selection signal generator. The selection signal generator is configured to generate a first selection signal and a second selection signal for each channel, and the signals are used for supplying the MOS tubes according to a preset form so as to control the MOS tubes to work in the preset form.

Each clock signal generator comprises a PMOS tube, a first NMOS tube and a second NMOS tube. The PMOS tube is connected to a reference clock signal and is switched on and off under the control of a first selection signal, namely, the first selection signal can control the switching on and off of the PMOS tube so as to selectively allow signals to pass through the PMOS tube. The first NMOS transistor is connected to the PMOS transistor through a clock line and is controlled by a second selection signal to be switched on and off. That is, the second selection signal can control the on/off of the first NMOS transistor, so as to selectively allow the signal to pass through the first NMOS transistor. Wherein the clock signal of the path is derived from the clock connection. In some examples of the invention, the clock wire may be a pin of a PMOS transistor or a first NMOS transistor, which is abstracted as a "clock wire" because it carries a clock signal to be output. In other examples of the invention, the clock connection may be a connection that actually exists to effect electrical coupling. The signals from the clock wires are used as the clock signals output by the circuit, and the clock signal combination generated by each clock signal generator can be used for the analog-digital converter and the like as described above. In some examples, the devices receiving the respective clock signals may operate triggered by edges or levels of the clock signals, and in particular may operate triggered by rising edges of the clock signals, for example.

One end of the second NMOS tube is connected to the first NMOS tube, and the other end of the second NMOS tube is grounded and is controlled by the reference clock signal to be switched on and off, namely, the reference clock signal can control the switching on and off of the second NMOS tube, so that the signal can be selectively allowed to pass through the second NMOS tube.

As can be seen from the above, the reference clock signal not only serves as the input of the PMOS transistor, but also controls the on-off of the second NMOS transistor. The first selection signal, the second selection signal and the reference clock signal work according to a set form, so that the PMOS tube, the first NMOS tube and the second NMOS tube are controlled, and a 1 st path clock signal of the set form is generated. Similarly, we can also generate the 2 nd, 3 rd, … … th, N-way clock signals in a given form, and the phase difference between these signals can be 2 pi/N for example. Because the PMOS tubes of each path can be triggered by low level, the edge (for example, rising edge) of each path of clock signal can be only affected by the on-off of the PMOS tube and the reference clock signal by designing the control signal of each MOS tube. On the other hand, since the reference clock signal is common to the respective channels, in practice, the edge (e.g., rising edge) of each channel clock signal is affected only by the switching of the PMOS transistor. In addition, the PMOS transistor can be guaranteed to be in a correct on-off state at the edge of the reference clock signal, i.e., the edge (e.g., rising edge) of each clock signal can be guaranteed to always depend on the edge of the reference clock signal. Thus, even though there may be manufacturing variations among the PMOS transistors, the clock signals may ensure edge (e.g., rising edge) accuracy in timing, which may ensure clock accuracy for subsequent devices such as those triggered by clock edges.

According to an aspect of the present invention, a clock generation method is provided. The clock generation method in the context of the present invention may generate multiple clock signals, as shown in fig. 9, each of which is generated by the following steps.

In step 901, the PMOS transistor can be turned on or off by the first selection signal, that is, the first selection signal can control the PMOS transistor to turn on or off, so as to selectively allow the signal to pass through the PMOS transistor. Wherein, one end of the PMOS tube is connected to the reference clock signal. In step 902, the second selection signal may control the first NMOS transistor to be turned on or off, that is, the second selection signal may control the first NMOS transistor to be turned on or off, so as to selectively allow a signal to pass through the first NMOS transistor. The first NMOS transistor is connected to the PMOS transistor through a clock line. In step 903, the on/off of the second NMOS transistor may be controlled by the reference clock signal, that is, the on/off of the second NMOS transistor may be controlled by the reference clock signal, so that the signal may be selectively allowed to pass through the second NMOS transistor. One end of the second NMOS tube is connected to the first NMOS tube, and the other end of the second NMOS tube is grounded. In step 904, the clock signal for the way is pulled according to the clock connection.

In some examples of the present invention, the generation of each clock signal is based on the PMOS transistor, the first NMOS transistor and the second NMOS transistor described above, and the connection manner of the PMOS transistor, the first NMOS transistor and the second NMOS transistor for generating each clock signal may be performed, for example, as shown in fig. 1. In some examples of the invention, the clock wire may be a pin of a PMOS transistor or a first NMOS transistor, which is abstracted as a "clock wire" because it carries a clock signal to be output. In other examples of the invention, the clock connection may be a connection that actually exists to effect electrical coupling. The signals from the clock wires are used as the clock signals output by the circuit, and the clock signal combination generated by each clock signal generator can be used for the analog-digital converter and the like as described above. In some examples, the devices receiving the respective clock signals may operate triggered by edges or levels of the clock signals, and in particular may operate triggered by rising edges of the clock signals, for example.

As can be seen from the above, the reference clock signal not only serves as the input of the PMOS transistor, but also controls the on-off of the second NMOS transistor. The first selection signal, the second selection signal and the reference clock signal work according to a set form, so that the PMOS tube, the first NMOS tube and the second NMOS tube are controlled, and a 1 st path clock signal of the set form is generated. Similarly, we can also generate the 2 nd, 3 rd, … … th, N-way clock signals in a given form, and the phase difference between these signals can be 2 pi/N for example. Because the PMOS tubes of each path can be triggered by low level, the edge (for example, rising edge) of each path of clock signal can be only affected by the on-off of the PMOS tube and the reference clock signal by designing the control signal of each MOS tube. On the other hand, since the reference clock signal is common to the respective channels, in practice, the edge (e.g., rising edge) of each channel clock signal is affected only by the switching of the PMOS transistor. In addition, the PMOS transistor can be guaranteed to be in a correct on-off state at the edge of the reference clock signal, i.e., the edge (e.g., rising edge) of each clock signal can be guaranteed to always depend on the edge of the reference clock signal. Thus, even though there may be manufacturing variations among the PMOS transistors, the clock signals may ensure edge (e.g., rising edge) accuracy in timing, which may ensure clock accuracy for subsequent devices such as those triggered by clock edges.

In some embodiments of the present application, the clock signal of the way is determined in time sequence relative to a position in the reference clock signal according to a falling edge of the first selection signal and a rising edge of the second selection signal. For example, FIG. 4 illustrates an example timing diagram of a clock generation circuit in accordance with one embodiment of the present invention. Wherein CKIN is a reference clock signal and CKD is the reference clock signal processed by the buffer circuit (which differs from CKIN by one clock cycle). CKSEL _ P1 represents a first select signal supplied to the PMOS transistor of way 1, CKSEL _ N1 represents a second select signal supplied to the first NMOS transistor of way 1, and so on. In FIG. 4, the control signals of the 4 clock generation circuits are shown, and CKS1-CKS4 are the clock signals generated by the 4 clock generation circuits. As illustrated in fig. 4, the falling edge position of the low level segment of CKS1 substantially corresponds to the rising edge of the reference clock signal CKIN (time t 2), because CKIN will remain high after the rising edge, and thus the second NMOS transistor of path 1 will be turned on; in addition, since CKSEL _ N1 is at high level at time t1-t3, the first NMOS transistor of the 1 st channel will also be turned on. Returning to fig. 1 or fig. 2, the first clock signal is pulled down to the same potential as GND. Thereafter, the first NMOS transistor or the second NMOS transistor is turned off, which will not affect the voltage level on the clock line, i.e., CKS1 will remain low. However, when CKSEL _ P1 goes low, the PMOS transistor is turned on, and if CKD goes high, CKS1 also transitions. As shown, CKS1 transitions from low to high at time t 5. It can be seen that the rising edge position of CKS1 is only related to the conduction of the PMOS transistor of the 1 st channel and CKD, and so on, the rising edge position of CKS2 is only related to the conduction of the PMOS transistor of the 2 nd channel and CKD, the rising edge position of CKS3 is only related to the conduction of the PMOS transistor of the 3 rd channel and CKD, and the rising edge position of CKS4 is only related to the conduction of the PMOS transistor of the 4 th channel and CKD. Since the CKD signal is maintained in a stable period, the rising edge positions of CKS1, CKS2, CKS3 and CKS4 are actually related to the conduction time of the PMOS transistors of the 1 st, 2 nd, 3 th and 4 th paths. For example, the rising edge of CKS3 shown in FIG. 4 (in the circle) is only relevant to the low level position of CKSEL _ P3 (in the circle). In other words, the rising edge positions of CKS1, CKS2, CKS3 and CKS4 are only related to the electrical characteristics of the PMOS transistors of the 1 st, 2 nd, 3 rd and 4 th paths.

In some embodiments of the present application, a falling edge of the first selection signal and a rising edge of the second selection signal are temporally located in different periods of the reference clock signal. As shown in fig. 4, in order to make the clock pulse segments output by CKS1 and the like occupy one period of the reference clock signal, the falling edge of the first selection signal and the rising edge of the second selection signal are located in adjacent periods of the reference clock signal in time sequence (specifically, for example, at low potential of adjacent periods of CKIN shown in the figure). Setting in this manner may cause CKSEL _ N1 to be high at one rising edge of the clock and CKSEL _ P1 to be high at the next rising edge. Of course, if the output clock is to have another shape, the positions of the falling edge of the first selection signal and the rising edge of the second selection signal of each channel relative to the reference clock signal may be further adjusted as needed (for example, the two are separated by about two reference clock cycles).

In some embodiments of the present application, the pulse width of the first selection signal and the pulse width of the second selection signal are close to the pulse width of the reference clock signal. The pulse width of the reference clock signal referred to in the context of this document refers to the half period of the reference clock signal (duty cycle 50%). This setting is for the convenience of setting the positional relationship of the first selection signal, the second selection signal, and the reference clock signal in terms of timing. Of course, it is also possible that the pulse width of the first selection signal and the pulse width of the second selection signal are slightly smaller than the reference clock signal, but a smaller pulse width would be disadvantageous for capturing the edges of the reference clock signal. Generally, a select signal larger than the pulse width of the reference clock signal may not be used, which may cause a malfunction in the circuit logic.

In some embodiments of the present application, a method generates four clock signals. Fig. 3 shows a clock generation circuit 30 according to one embodiment of the present invention, which includes clock signal generators 301, 302, 303, and 304 to generate the 1 st, 2 nd, 3 th, and 4 th clock signals, respectively. Similarly, the embodiment corresponding to fig. 4 is also described with a clock generation circuit including a four-way clock signal generator.

According to another aspect of the present invention, there is provided a computer readable storage medium having instructions stored therein, wherein the instructions, when executed by a processor, cause the processor to perform any of the methods as described above. Computer-readable media, as referred to herein, includes all types of computer storage media, which can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, computer-readable media may comprise RAM, ROM, E2PROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other transitory or non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Disk (disk) and disc (disc), as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

In summary, the present invention provides a clock signal generation mechanism, which can share components in a circuit to a large extent to reduce the phase difference between a clock signal and an ideal clock signal, thereby improving the accuracy of the clock. It should be noted that some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.

The above examples mainly illustrate the clock generation circuit, the clock generation method, the analog-to-digital converter, and the computer-readable storage medium of the present invention. Although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.