阅读说明：本技术 半导体装置及制造方法 (Semiconductor device and method of manufacturing the same ) 是由 小幡智幸 于 2020-02-20 设计创作，主要内容包括：提供一种半导体装置,所述半导体装置具备含氧的半导体基板,半导体基板的深度方向上的氧浓度分布在相对于半导体基板的深度方向上的中央靠近上表面的一侧具有氧浓度比半导体基板的下表面的氧浓度高的高氧浓度部。高氧浓度部可以在氧浓度分布中具有浓度峰。半导体基板的深度方向上的晶体缺陷的密度分布可以在半导体基板的上表面侧具有上表面侧密度峰,上表面侧密度峰可以配置于氧浓度为浓度峰的峰值的50％以上的深度范围。(Provided is a semiconductor device provided with a semiconductor substrate containing oxygen, wherein the oxygen concentration distribution in the depth direction of the semiconductor substrate has a high oxygen concentration portion, which has an oxygen concentration higher than the oxygen concentration of the lower surface of the semiconductor substrate, on the side closer to the upper surface than the center in the depth direction of the semiconductor substrate. The high oxygen concentration portion may have a concentration peak in the oxygen concentration distribution. The density distribution of crystal defects in the depth direction of the semiconductor substrate may have an upper surface side density peak on the upper surface side of the semiconductor substrate, and the upper surface side density peak may be arranged in a depth range in which the oxygen concentration is 50% or more of the peak value of the density peak.)

1. A semiconductor device comprising a semiconductor substrate containing oxygen,

the oxygen concentration distribution in the depth direction of the semiconductor substrate has a high oxygen concentration portion having an oxygen concentration higher than that of the lower surface of the semiconductor substrate on a side closer to the upper surface with respect to the center in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1,

the high oxygen concentration portion has a concentration peak in the oxygen concentration distribution.

3. The semiconductor device according to claim 2,

the oxygen concentration decreases from the concentration peak toward the lower surface of the semiconductor substrate until decreasing to the same concentration as the oxygen concentration of the lower surface of the semiconductor substrate.

4. The semiconductor device according to claim 2 or 3,

a density distribution of crystal defects in a depth direction of the semiconductor substrate has an upper surface side density peak on an upper surface side of the semiconductor substrate,

the upper surface side density peak is disposed in a depth range in which the oxygen concentration is 50% or more of a peak value of the concentration peak.

5. The semiconductor device according to claim 4,

the upper surface side density peak is disposed in a depth range in which the oxygen concentration is 80% or more of a peak value of the concentration peak.

6. The semiconductor device according to claim 4,

in the oxygen concentration distribution, a depth range in which the oxygen concentration is 50% or more of a peak value of the concentration peak is 10 μm or more.

7. The semiconductor device according to any one of claims 4 to 6,

the concentration peak is disposed between the upper surface side density peak and the upper surface of the semiconductor substrate.

8. The semiconductor device according to any one of claims 2 to 7,

the peak value of the concentration peak is 1.5 times or more as large as the minimum value of the oxygen concentration in the oxygen concentration distribution.

9. The semiconductor device according to claim 8,

the peak value of the concentration peak is 5 times or more as large as the minimum value of the oxygen concentration in the oxygen concentration distribution.

10. The semiconductor device according to any one of claims 4 to 9,

the distance between the concentration peak in the oxygen concentration distribution and the upper surface of the semiconductor substrate is 5 [ mu ] m or more and 20 [ mu ] m or less.

11. The semiconductor device according to any one of claims 1 to 10,

the semiconductor device further includes:

a gate conductive part disposed on an upper surface of the semiconductor substrate; and

a gate insulating film that insulates the gate conductive portion from the semiconductor substrate.

12. The semiconductor device according to any one of claims 1 to 11,

the semiconductor device further includes:

a cathode region of a first conductivity type provided in contact with a lower surface of the semiconductor substrate; and

an anode region of a second conductivity type disposed in contact with an upper surface of the semiconductor substrate.

13. A method for manufacturing a semiconductor device having a semiconductor substrate containing oxygen,

the manufacturing method comprises:

an annealing step of annealing an initial substrate so that a solid solubility limit concentration of oxygen for the initial substrate is higher than a current oxygen concentration of the initial substrate; and

and a thinning step of thinning the initial substrate from a lower surface side of the initial substrate to form the semiconductor substrate.

14. The manufacturing method according to claim 13, further comprising,

a preparation step of preparing an MCZ substrate as the initial substrate.

15. The manufacturing method according to claim 13, further comprising,

a preparation step of preparing an FZ substrate as the initial substrate.

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same.

Background

Conventionally, semiconductor devices in which semiconductor elements such as transistors and diodes are formed on a semiconductor substrate have been known (see, for example, patent documents 1 to 4).

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2010-165772

Patent document 2: japanese patent laid-open publication No. 2012 and 238904

Patent document 3: japanese patent laid-open publication No. 2018-137454

Patent document 4: japanese laid-open patent publication (Kokai) No. 2015-198166

Disclosure of Invention

Technical problem

Depending on the concentration of oxygen contained in the semiconductor substrate, the characteristics of the semiconductor device may vary.

Technical scheme

In order to solve the above problem, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate containing oxygen. The oxygen concentration distribution in the depth direction of the semiconductor substrate may have a high oxygen concentration portion having an oxygen concentration higher than that of the lower surface of the semiconductor substrate on a side closer to the upper surface with respect to the center in the depth direction of the semiconductor substrate.

The high oxygen concentration portion may have a concentration peak in the oxygen concentration distribution.

The oxygen concentration may decrease from the concentration peak toward the lower surface of the semiconductor substrate until decreasing to the same concentration as the oxygen concentration of the lower surface of the semiconductor substrate.

The density distribution of the crystal defects in the depth direction of the semiconductor substrate may have an upper surface side density peak on the upper surface side of the semiconductor substrate. The upper surface side density peak may be disposed in a depth range in which the oxygen concentration is 50% or more of the peak value of the density peak. The upper surface side density peak may be arranged in a depth range in which the oxygen concentration is 80% or more of the peak value of the density peak.

In the oxygen concentration distribution, the depth range in which the oxygen concentration is 50% or more of the peak value of the concentration peak may be 10 μm or more.

The concentration peak may be disposed between the upper surface side density peak and the upper surface of the semiconductor substrate.

The peak value of the concentration peak may be 1.5 times or more with respect to the minimum value of the oxygen concentration in the oxygen concentration distribution. The peak value of the concentration peak may be 5 times or more with respect to the minimum value of the oxygen concentration in the oxygen concentration distribution.

The distance between the concentration peak in the oxygen concentration distribution and the upper surface of the semiconductor substrate may be 5 μm or more and 20 μm or less.

The semiconductor device may include: a gate conductive part disposed on an upper surface of the semiconductor substrate; and a gate insulating film that insulates the gate conductive portion from the semiconductor substrate.

The semiconductor device may include: a cathode region of a first conductivity type provided in contact with a lower surface of the semiconductor substrate; and an anode region of a second conductivity type disposed in contact with an upper surface of the semiconductor substrate.

In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a semiconductor substrate containing oxygen. The manufacturing method may include an annealing step of annealing the initial substrate so that a solid solubility limit concentration of oxygen with respect to the initial substrate is higher than a current oxygen concentration of the initial substrate. The manufacturing method may include a thinning step of thinning the starting substrate from the lower surface side of the starting substrate to form the semiconductor substrate.

The manufacturing method may include a preparation step of preparing the MCZ substrate as an initial substrate. The manufacturing method may include a preparation step of preparing the FZ substrate as an initial substrate.

The summary of the invention does not list all necessary features of the present invention. Moreover, sub-combinations of these feature sets can also be inventions.

Drawings

Fig. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to an embodiment of the present invention.

Fig. 2 shows an example of the oxygen concentration distribution in the depth direction of the semiconductor substrate 10.

Fig. 3 shows another example of the oxygen concentration distribution in the depth direction of the semiconductor substrate 10.

Fig. 4 is a diagram illustrating a part of the steps in the method for manufacturing the semiconductor device 100.

Fig. 5 is a plan view showing an example of the semiconductor device 100 according to the embodiment of the present invention.

Fig. 6 is an enlarged view of the area a in fig. 5.

Fig. 7 is a view showing an example of a section b-b in fig. 6.

Fig. 8 is a view showing another example of the section b-b in fig. 6.

Fig. 9 shows an example of the oxygen concentration distribution and the crystal defect density distribution in the J-J section of fig. 8.

Fig. 10 is a graph showing the relationship between the oxygen concentration and the forward voltage Vf in the case where the semiconductor substrate having a substantially uniform oxygen concentration distribution in the depth direction is formed with the upper surface side lifetime controlled region 92 as shown in fig. 8.

Fig. 11 is a graph comparing characteristics of the semiconductor device 100 manufactured using two semiconductor substrates 10 having different initial concentrations of oxygen.

Fig. 12 is a diagram showing another example of the semiconductor device 100.

Description of the symbols

10: semiconductor substrate, 11: well region, 12: emission area, 14: base region, 15: contact zone, 16: accumulation zone, 18: drift region, 20: buffer, 21: upper surface, 22: collector region, 23: lower surface, 24: collector electrode, 29: straight line portion, 30: dummy groove portion, 31: front end portion, 32: dummy insulating film, 34: dummy conductive portion, 38: interlayer insulating film, 39: straight line portion, 40: gate trench portion, 41: front end portion, 42: gate insulating film, 44: gate conductive portion, 52: emitter electrode, 54: contact hole, 60, 61: mesa portion, 70: transistor portion, 80: diode portion, 81: extension zone, 82: cathode region, 90: edge termination structure, 92: upper surface side lifetime control region, 93: lower surface side lifetime control region, 100: semiconductor device, 102: end edge, 112: gate pad, 120: active portion, 130: outer peripheral gate wiring, 131: active-side gate wiring, 141: upper surface-side electrode, 142: lower surface-side electrode, 143: high oxygen concentration portion, 144: concentration peak, 145: lower surface side slope, 146: upper surface side slope, 147: flat region, 154: upper surface side density peak, 155: lower surface side slope, 156: upper surface side slope

Detailed Description

The present invention will be described below with reference to embodiments thereof, but the following embodiments do not limit the invention according to the claims. In addition, all combinations of the features described in the embodiments are not necessarily essential to the solution of the invention.

In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "up", and the other side is referred to as "down". One of the two main surfaces of a substrate, a layer, or another member is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "up" and "down" are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

In this specification, technical matters will be described using orthogonal coordinate axes of X, Y, and Z axes. The orthogonal coordinate axes are only for specifying the relative positions of the constituent elements, and are not limited to specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. The + Z-axis direction and the-Z-axis direction are opposite directions to each other. When the positive and negative are not described and the Z-axis direction is described, the positive and negative are referred to as directions parallel to the + Z axis and the-Z axis. In this specification, a case of viewing from the + Z axis direction is sometimes referred to as a plan view.

In the present specification, the term "identical" or "equal" may include a case where an error due to a manufacturing variation or the like is included. The error is, for example, within 10%.

In this specification, the conductive type of the impurity-doped region doped with an impurity is referred to as P-type or N-type. However, the conductivity type of each doped region may be of opposite polarity. In the present specification, the term "P + type" or "N + type" means a doping concentration higher than that of P type or N type, and the term "P" or "N" means a doping concentration lower than that of P type or N type. In the present specification, the term "P + + type" or "N + + type" means that the doping concentration is higher than the doping concentration of P + type or N + type.

In this specification, the doping concentration refers to the concentration of an impurity which is activated as a donor or an acceptor. In this specification, the difference in the concentration between the donor and the acceptor may be referred to as the doping concentration. This concentration difference can be measured by a voltage-capacitance method (CV method). Further, the carrier concentration measured by diffusion resistance measurement (SR) may be set as the doping concentration. Further, in the case where the doping concentration profile has a peak, the peak may be taken as the doping concentration in the region. When the doping concentration in a region where a donor or an acceptor is present is substantially uniform, the average value of the doping concentrations may be set as the doping concentration in the region. In this specification, the concentration of the dopant refers to the respective concentrations of the donor and the acceptor.

Fig. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 of this example is a silicon substrate.

The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are 2 main surfaces facing each other. In fig. 1, a direction connecting the upper surface 21 and the lower surface 23 (i.e., a depth direction of the semiconductor substrate 10) is defined as a Z-axis direction. Further, 2 orthogonal axes parallel to the upper surface 21 and the lower surface 23 are set as X-axis and Y-axis. Although semiconductor elements such as transistors and diodes are formed on the semiconductor substrate 10, they are omitted in fig. 1.

The semiconductor device 100 may include an upper surface electrode 141 and a lower surface electrode 142. The upper surface side electrode 141 is a metal electrode disposed above the upper surface 21. The lower surface side electrode 142 is a metal electrode disposed below the lower surface 23. The upper surface-side electrode 141 and the lower surface-side electrode 142 may be provided in contact with the semiconductor substrate 10, or an interlayer insulating film may be provided between the upper surface-side electrode 141 and the lower surface-side electrode 142. The interlayer insulating film is omitted in fig. 1.

The semiconductor substrate 10 contains oxygen. Oxygen may be contained throughout the semiconductor substrate 10. The characteristics of the semiconductor device 100 vary depending on the concentration of oxygen contained in the semiconductor substrate 10.

For example, a defect level for adjusting the lifetime of carriers may be formed in the semiconductor substrate 10. The defect level can be formed by irradiating the semiconductor substrate 10 with particles such as helium ions or hydrogen ions (e.g., protons), electron beams, or the like. When particles such as helium ions are irradiated, voids (V) are generated in the semiconductor substrate 10, and VO defects are generated by the bonding of oxygen to the voids. The recombination of the carriers with VO defects and the like reduces the lifetime of the carriers. Since the density of VO defects depends on the oxygen concentration in the semiconductor substrate 10, even when helium ions or the like are irradiated under the same conditions, if the oxygen concentration in the semiconductor substrate 10 varies, characteristics such as the lifetime of carriers vary.

The semiconductor substrate 10 is a chip obtained by cutting a wafer from an ingot formed by a method such as the MCZ (magnetic field applied Czochralski) method or the FZ (Floating Zone) method, and singulating the wafer. The semiconductor substrate 10 contains oxygen which is intentionally or unintentionally introduced during the manufacturing process. However, due to variations in manufacturing conditions and the like, variations in oxygen concentration included in the semiconductor substrate 10 occur.

In this example, the substrate in a wafer or chip state is annealed at a predetermined annealing temperature and for a predetermined annealing time. During annealing, the surface of the substrate is exposed to an oxygen-containing atmosphere or an oxide film is formed thereon. The annealing time is a long time to the extent that oxygen at a concentration of the solid solubility limit corresponding to the annealing temperature is introduced into the substrate. The annealing time may be 1 hour or more, 2 hours or more, or 10 hours or more. The solid solubility limit of oxygen means the limit concentration of oxygen that can be dissolved in the substrate, and varies depending on the annealing temperature.

By annealing for a certain or more annealing time, oxygen is introduced at a concentration substantially equal to the solid solubility limit at least in the vicinity of the surface of the substrate. Therefore, by controlling the annealing temperature so as to have a solid solubility limit corresponding to a desired oxygen concentration, the oxygen concentration of the semiconductor substrate 10 can be controlled. Further, since the annealing temperature can be relatively easily controlled, the variation in oxygen concentration between the substrates can also be reduced.

Fig. 2 shows an example of the oxygen concentration distribution in the depth direction of the semiconductor substrate 10. The vertical axis in fig. 2 is a logarithmic axis showing the oxygen concentration per unit volume, and the horizontal axis is a linear axis showing the depth position in the semiconductor substrate 10. Fig. 2 is an oxygen concentration distribution at the K-K section in fig. 1. In fig. 2, the oxygen concentration of the semiconductor substrate 10 before the annealing treatment is set as the initial concentration Ob. The initial concentration Ob corresponds to the oxygen concentration of the substrate in the wafer state.

By the annealing treatment, oxygen is introduced into the semiconductor substrate 10 from the upper surface 21. The annealing temperature is a temperature at which the solid solubility limit is higher than the initial concentration Ob. Since oxygen diffuses from the upper surface 21 into the semiconductor substrate 10, the oxygen concentration becomes smaller as the distance from the upper surface 21 increases.

Oxygen is similarly introduced from the lower surface 23 of the semiconductor substrate 10, but the semiconductor substrate 10 of the present example is annealed and then the semiconductor substrate 10 is polished from the lower surface 23 side to adjust the thickness of the semiconductor substrate 10. In this example, the polishing was performed in a range larger than the depth range in which oxygen was introduced from the lower surface 23 side. Therefore, in the oxygen concentration distribution shown in fig. 2, the closer to the lower surface 23, the lower the oxygen concentration becomes.

The oxygen concentration distribution in the semiconductor substrate 10 is on the side closer to the upper surface 21 than the center Dc in the depth direction of the semiconductor substrate 10, and has a high oxygen concentration portion 143 having an oxygen concentration higher than the oxygen concentration of the lower surface 23 of the semiconductor substrate 10. In the example of fig. 2, the oxygen concentration of the lower surface 23 of the semiconductor substrate 10 is O23. As described above, by performing the annealing treatment at the annealing temperature at which the solid solubility limit is greater than the initial concentration Ob, oxygen is introduced at a concentration corresponding to the solid solubility limit within a predetermined distance from the upper surface 21 of the semiconductor substrate 10, and the oxygen concentration decreases as it goes away from the upper surface 21. Therefore, a high oxygen concentration portion 143 having an oxygen concentration higher than that of the lower surface 23 is formed on the upper surface 21 side of the semiconductor substrate 10. With such a configuration, the oxygen concentration of the semiconductor substrate 10 can be controlled with high accuracy by the annealing temperature.

The high oxygen concentration portion 143 may have a concentration peak 144 in the oxygen concentration distribution. The concentration peak 144 is a point at which the oxygen concentration becomes maximum in the oxygen concentration distribution. In this example, the oxygen concentration at the concentration peak 144 is Omax. The oxygen concentration Omax may coincide with a solid solubility limit determined by the annealing temperature.

In the process of ending the annealing treatment and returning the temperature of the semiconductor substrate 10 to room temperature, oxygen in the vicinity of the upper surface 21 of the semiconductor substrate 10 may be released to the outside of the semiconductor substrate 10. Thereby, the concentration peak 144 is generated in the oxygen concentration distribution in the semiconductor substrate 10 of this example. The oxygen concentration profile has: an upper surface-side slope 146 between concentration peak 144 and upper surface 21; and a lower surface side slope 145 between the concentration peak 144 and the lower surface 23. Each slope is a region where the oxygen concentration decreases with distance from the concentration peak 144.

The oxygen concentration distribution in the depth direction of the semiconductor substrate 10 may decrease from the concentration peak 144 toward the lower surface 23 of the semiconductor substrate 10 until decreasing to the same concentration as the oxygen concentration O23 of the lower surface 23 of the semiconductor substrate 10. The oxygen concentration of the lower surface side slope 145 of this example continuously decreases from the concentration peak 144 to the lower surface 23. The inclination of the lower surface side slope 145 may be gentler than the inclination of the upper surface side slope 146. This makes it possible to smooth the change in the oxygen concentration over a wide area of the semiconductor substrate 10.

The oxygen concentration on the upper surface 21 of the semiconductor substrate 10 was set to O21. The oxygen concentration of the upper surface side slope 146 in this example continuously decreases from the oxygen concentration Omax of the concentration peak 144 to the oxygen concentration O21 of the upper surface 21. The oxygen concentration O21 may be higher than the initial concentration Ob. The oxygen concentration O21 may be lower than the oxygen concentration O23 or higher than the oxygen concentration O23. The oxygen concentration O21 may coincide with the minimum value Omin of the oxygen concentration in the semiconductor substrate 10.

The distance in the depth direction between concentration peak 144 and upper surface 21 may be 5 μm or more and 20 μm or less. The depth position of the concentration peak 144 can be controlled by the annealing temperature and annealing time. The depth position of the concentration peak 144 may be 1/4 or less of the thickness of the semiconductor substrate 10 in the depth direction, 1/5 or less of the thickness of the semiconductor substrate 10 in the depth direction, or 1/10 or less of the thickness of the semiconductor substrate 10 in the depth direction. Concentration peaks 144 may be disposed throughout a range of depths. That is, in the oxygen concentration distribution, the region that becomes the oxygen concentration Omax may be provided over a predetermined depth range.

Fig. 3 shows another example of the oxygen concentration distribution in the depth direction of the semiconductor substrate 10. In the oxygen concentration distribution in this example, the oxygen concentration decreases from the concentration peak 144 toward the lower surface 23 of the semiconductor substrate 10 until the oxygen concentration decreases to the same concentration as the oxygen concentration O23 of the lower surface 23 of the semiconductor substrate 10. The oxygen concentration distribution has a flat region 147 having an oxygen concentration equal to O23 over a predetermined depth range from the lower surface 23. The flat region 147 may be disposed in a region on the lower surface 23 side of the semiconductor substrate 10 (i.e., a region from the central position Dc to the lower surface 23) or may be disposed in a region extending to the upper surface 21 side (i.e., a region from the central position Dc to the upper surface 21).

Depending on the annealing conditions, there are regions inside the substrate where oxygen from the upper surface 21 has not diffused. The oxygen concentration in this region is approximately equal to the initial concentration Ob. By polishing the lower surface 23 side so as to leave this region, the semiconductor substrate 10 having the oxygen concentration distribution as shown in fig. 3 can be formed.

In the example of fig. 2 and 3, the lower surface side slope 145 may be provided throughout the region from the upper surface 21 side to the lower surface 23 side. The length of the lower surface side slope 145 in the depth direction may be 1/5 or more of the thickness of the semiconductor substrate 10 in the depth direction, 1/4 or more of the thickness of the semiconductor substrate 10 in the depth direction, 1/3 or more of the thickness of the semiconductor substrate 10 in the depth direction, or 1/2 or more of the thickness of the semiconductor substrate 10 in the depth direction. The length of the lower surface side slope 145 in the depth direction may be 20 μm or more, 30 μm or more, 40 μm or more, or 50 μm or more. The length of the lower surface side slope 145 in the depth direction may be 2 times or more the length of the upper surface side slope 146 in the depth direction, 4 times or more the length of the upper surface side slope 146 in the depth direction, or 10 times or more the length of the upper surface side slope 146 in the depth direction.

Fig. 4 is a diagram illustrating a part of the steps in the method for manufacturing the semiconductor device 100. In the manufacturing method of this example, an initial substrate is prepared in the preparation step S400. The starting substrate may be an MCZ substrate formed by an MCZ method, an FZ substrate formed by an FZ method, or a substrate formed by another method. As described above, the initial substrate is in a wafer or chip state. The oxygen concentration of the initial substrate is the initial concentration Ob.

Next, in an annealing step S401, the initial substrate is annealed. In the annealing step S401, the starting substrate is annealed in an oxygen-containing atmosphere or in a state where a natural oxide film is formed on the surface. In the annealing step S401, the initial substrate is annealed at a predetermined annealing temperature and annealing time so that the solid solubility limit concentration of oxygen with respect to the initial substrate is higher than the current oxygen concentration of the initial substrate. The current oxygen concentration refers to the initial concentration Ob before the annealing treatment. After annealing, the oxygen concentration distribution on the upper surface side of the starting substrate is the same as the distribution shown in fig. 2 or 3. The oxygen concentration distribution on the lower surface side of the initial substrate is the same as the distribution obtained by replacing the horizontal axis in fig. 2 or 3 with a depth position with respect to the lower surface.

The solid solubility limit of oxygen relative to the silicon substrate is 2X 10 at an annealing temperature of 1000 deg.C¹⁷/cm³About 5X 10 at an annealing temperature of 1150 deg.C¹⁷/cm³Left and right. In the annealing step S401, an annealing temperature having a solid solubility limit larger than the initial oxygen concentration is set in accordance with the initial oxygen concentration of the initial substrate and the material of the initial substrate.

Next, in the upper surface side structure forming step S402, the structure on the upper surface side of the semiconductor device 100 is formed. The structure on the upper surface side includes an electrode and an insulating film disposed above the upper surface 21 of the semiconductor substrate 10, and a doped region and the like formed inside the semiconductor substrate 10. The doped region is a region implanted with a dopant. For example, when the semiconductor device 100 is a transistor, the structure on the upper surface 21 side includes: an emitter electrode, an interlayer insulating film, a gate conductive portion, a gate insulating film, an N-type emitter region, a P-type base region, and the like. Note that the annealing step S401 may be performed during the upper surface side structure forming step S402. The annealing step S401 may be performed before the upper surface of the initial substrate forms the emitter electrode. Further, the annealing step S401 may be a common step with or different from other annealing steps for activating, for example, a dopant.

Next, in the thinning step S403, the initial substrate is thinned from the lower surface side thereof, and the semiconductor substrate 10 is formed. In the thinning step S403, the initial substrate may be thinned using CMP or the like. Thereby, the oxygen concentration distribution of the semiconductor substrate 10 becomes the distribution shown in fig. 2 or 3.

Next, in a lower surface side structure forming step S404, a structure of the lower surface side of the semiconductor device 100 is formed. The structure of the lower surface side includes: an electrode disposed below the lower surface 23 of the semiconductor substrate 10, a doped region formed inside the semiconductor substrate 10, and the like. In the case where the semiconductor device 100 is a transistor, for example, a P-type collector region or the like is included in the structure on the lower surface 23 side.

Through such a process, the semiconductor device 100 having the oxygen concentration profile shown in fig. 2 or 3 can be manufactured. The oxygen concentration on the upper surface 21 side of the semiconductor substrate 10 can be controlled relatively accurately by the annealing temperature. On the other hand, the influence of the initial concentration Ob increases in the oxygen concentration on the lower surface 23 side of the semiconductor substrate 10, and therefore, the variation in the oxygen concentration tends to increase as compared with the upper surface 21 side. By forming a structure including a channel of a transistor or the like on the upper surface 21 side of the semiconductor substrate 10, variations in characteristics of the semiconductor device 100 can be further reduced.

The condition in the annealing step S401 may be set so that the concentration peak value Omax of the concentration peak 144 is 1.5 times or more the minimum value Omin of the oxygen concentration in the oxygen concentration distribution in the depth direction of the semiconductor substrate 10. The concentration peak Omax and the solid solubility limit corresponding to the annealing temperature are approximately equal. The minimum value Omin of the oxygen concentration is equal to or greater than the initial concentration Ob. Therefore, by setting the concentration peak value Omax to 1.5 times or more the minimum value Omin, the initial substrate can be annealed at a solid solubility limit sufficiently higher than the initial concentration Ob. This can reduce variations in the oxygen concentration in the semiconductor substrate 10. When a plurality of semiconductor devices 100 are manufactured, annealing conditions may be set to a solid solubility limit of 1.5 times the maximum initial concentration Ob value among the initial concentrations Ob of the plurality of initial substrates. Annealing treatment is performed on each of the initial substrates under a set common annealing condition. This can reduce the variation in the oxygen concentration of each substrate while suppressing the influence of the variation in the initial concentration Ob.

The concentration peak value Omax may be 5 times or more the minimum value Omin, or may be 10 times or more the minimum value Omin. This can further reduce variations in the oxygen concentration in the semiconductor substrate 10.

Fig. 5 is a plan view showing an example of the semiconductor device 100 according to the embodiment of the present invention. Fig. 5 shows positions where the respective members are projected on the upper surface of the semiconductor substrate 10. In fig. 5, only a part of the components of the semiconductor device 100 is shown, and a part of the components is omitted.

The semiconductor substrate 10 has an edge 102 in a plan view. In the present specification, the case simply referred to as a plan view refers to a case of being viewed from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of end edges 102 facing each other in a plan view. In fig. 5, the X-axis and the Y-axis are parallel to a certain end edge 102. The Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region in which a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. An emitter electrode is provided above the active portion 120, but is omitted in fig. 5.

The active portion 120 includes a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as an FWD. In fig. 5, a region where transistor portion 70 is arranged is denoted by symbol "I", and a region where diode portion 80 is arranged is denoted by symbol "F". Transistor portion 70 and diode portion 80 are arranged in a predetermined arrangement direction (X-axis direction in fig. 5). The transistor portions 70 and the diode portions 80 may be arranged alternately in the X-axis direction. In this specification, a direction perpendicular to the arrangement direction in a plan view may be referred to as an extending direction (Y-axis direction in fig. 5). The transistor portion 70 and the diode portion 80 may have long sides in the extending direction, respectively. That is, the length of the transistor portion 70 in the Y axis direction is larger than the width in the X axis direction. Likewise, the diode portion 80 has a length in the Y-axis direction larger than a width in the X-axis direction. The longitudinal direction of the transistor portion 70 and the diode portion 80 may be the same as or different from the longitudinal direction of a groove portion described later.

The diode portion 80 has an N + -type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, a region where the cathode region is provided is referred to as a diode portion 80. That is, the diode portion 80 is a region overlapping with the cathode region in a plan view. A P + -type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region. In this specification, the diode portion 80 may include an extension region 81 extending the diode portion 80 in the Y-axis direction to a gate wiring described later. A collector region is provided on the lower surface of the extension region 81.

The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may have an anode pad, a cathode pad, and a current detection pad in addition to the gate pad 112. Each pad is disposed near the edge 102. The vicinity of the edge 102 refers to a region between the edge 102 and the emitter electrode when viewed from above. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit by a wire or the like.

A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 120. The semiconductor device 100 includes a gate wiring connecting the gate pad 112 and the gate groove portion. In fig. 5, gate wirings are hatched diagonally.

The gate wiring of this example includes an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is disposed between the active portion 120 and the edge 102 of the semiconductor substrate 10 in a plan view. The outer peripheral gate line 130 of this example surrounds the active portion 120 in a plan view. A region surrounded by the outer peripheral gate line 130 in a plan view may be the active portion 120. Further, the outer peripheral gate wiring 130 is connected to the gate pad 112. The outer peripheral gate line 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum or the like.

The active-side gate wiring 131 is provided in the active portion 120. By providing the source-side gate wiring 131 in the active portion 120, variations in wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

The active-side gate wiring 131 is connected to the gate trench portion of the active portion 120. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 may be a wiring formed of a semiconductor such as polycrystalline silicon doped with impurities.

The active-side gate wiring 131 may be connected to the outer circumferential gate wiring 130. The active-side gate line 131 of this example is provided so as to extend from the outer peripheral gate line 130 on one side to the outer peripheral gate line 130 on the other side in the X-axis direction so as to cross the active portion 120 at substantially the center in the Y-axis direction.

Further, the semiconductor device 100 may include: a temperature sensing portion, not shown, which is a PN junction diode formed of polysilicon or the like; and a current detection unit, not shown, which simulates the operation of the transistor unit provided in the active unit 120.

The semiconductor device 100 of this example includes an edge termination structure 90 between the peripheral gate line 130 and the edge 102. The edge termination structure 90 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, a guard ring and a field plate provided in a ring shape surrounding the active portion 120, and has a structure in which a surface electric field is reduced and these are combined.

Fig. 6 is an enlarged view of the area a in fig. 5. Region a is a region including transistor portion 70, diode portion 80, and active-side gate wiring 131. In the region where the active portion 120 is adjacent to the outer peripheral gate wiring 130, the outer peripheral gate wiring 130 may be disposed instead of the active-side gate wiring 131.

The semiconductor device 100 of this example includes: gate trench portion 40, dummy trench portion 30, well region 11, emitter region 12, base region 14, and contact region 15 provided inside the upper surface side of semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are examples of trench portions. The semiconductor device 100 of this example includes the emitter electrode 52 and the active-side gate line 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided to be separated from each other.

An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in fig. 6. In the interlayer insulating film of this example, the contact hole 54 is provided so as to penetrate the interlayer insulating film. In fig. 6, each contact hole 54 is marked with diagonal hatching.

Emitter electrode 52 is disposed above gate trench portion 40, dummy trench portion 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 is in contact with emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 through contact hole 54. The emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy groove portion 30 at the front end of the dummy groove portion 30 in the Y-axis direction.

The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 may be connected to the gate conductive portion of the gate groove portion 40 at the tip portion 41 of the gate groove portion 40 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy groove portion 30.

The emitter electrode 52 is formed of a material containing a metal. In fig. 6, a range where the emitter electrode 52 is provided is shown. For example, at least a part of the region of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal made of titanium and/or a titanium compound or the like in a lower layer of a region made of aluminum or the like. Further, the contact hole may have a plug formed by embedding tungsten or the like so as to be in contact with a barrier metal, aluminum or the like.

The well region 11 is provided so as to overlap with the active-side gate wiring 131. The well region 11 is provided so as to extend with a predetermined width also in a range not overlapping with the active-side gate wiring 131. The well region 11 in this example is provided so as to be distant from one end of the contact hole 54 in the Y axis direction toward the active-side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. The base region 14 in this example is P-type and the well region 11 is P + -type.

Each of transistor portion 70 and diode portion 80 has a plurality of groove portions arranged in the arrangement direction. In transistor portion 70 of the present example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the array direction. In the diode portion 80 of the present example, a plurality of dummy groove portions 30 are provided along the array direction. In the diode portion 80 of this example, the gate groove portion 40 is not provided.

The gate trench portion 40 of this example may have two straight portions 39 (portions of trenches having a straight line shape along the extending direction) extending in the extending direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39. The extending direction in fig. 6 is the Y-axis direction.

At least a part of the distal end portion 41 is preferably curved in a plan view. The ends of the two straight portions 39 in the Y axis direction are connected to each other by the tip portion 41, and thus the electric field concentration at the ends of the straight portions 39 can be alleviated.

In the transistor portion 70, the dummy trench portion 30 is provided between the respective straight portions 39 of the gate trench portion 40. One dummy groove portion 30 may be provided between the straight portions 39, or a plurality of dummy groove portions 30 may be provided. The dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31, as in the case of the gate trench portion 40. The semiconductor device 100 shown in fig. 6 includes both the dummy groove portion 30 having a straight shape without the front end portion 31 and the dummy groove portion 30 having the front end portion 31. In this specification, each straight line portion of each groove portion may be treated as one groove portion.

The diffusion depth of well region 11 may be deeper than the depths of gate trench portion 40 and dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 at the end in the Y axis direction in a plan view. That is, at the end of each groove portion in the Y axis direction, the bottom portion of each groove portion in the depth direction is covered with the well region 11. This can alleviate the electric field concentration at the bottom of each groove.

In the arrangement direction, mesa portions are provided between the groove portions. The mesa portion is a region sandwiched by the groove portions in the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion of the present example is provided on the upper surface of the semiconductor substrate 10 so as to extend in the extending direction (Y-axis direction) along the trench. In this example, the mesa portion 60 is provided in the transistor portion 70, and the mesa portion 61 is provided in the diode portion 80. In the present specification, in the case of being simply referred to as a mesa portion, each of the mesa portion 60 and the mesa portion 61 is referred to.

The mesa portion 60 which is in contact with the gate trench portion 40 and in which the emitter region 12 is disposed, among the mesa portions 60, is referred to as a gate mesa portion. In this example, all of the mesa portions 60 of the transistor portion 70 are gate mesa portions. In another example, the transistor portion 70 may have a dummy mesa portion which is not in contact with the gate trench portion 40 or in which the emitter region 12 is not provided.

A base region 14 is provided at each mesa portion. In the mesa portion, a region disposed closest to the active-side gate wiring 131 among the base regions 14 exposed on the upper surface of the semiconductor substrate 10 is set as a base region 14-e. In fig. 6, the base regions 14-e are shown as being arranged at one end portion of each mesa portion in the extending direction, but the base regions 14-e are also arranged at the other end portion of each mesa portion. At least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in a region sandwiched by the base regions 14-e in a plan view of each mesa portion. The emitter region 12 is of the N + type and the contact region 15 is of the P + type in this example. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

Mesa portion 60 of transistor portion 70 has emitter region 12 exposed on the upper surface of semiconductor substrate 10. The emitter region 12 is disposed in contact with the gate trench portion 40. The mesa portion 60 contacting the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

The contact region 15 and the emitter region 12 in the mesa portion 60 are respectively provided from a groove portion on one side to a groove portion on the other side in the X-axis direction. For example, the contact regions 15 and the emitter regions 12 of the mesa portion 60 are alternately arranged along the extending direction (Y-axis direction) of the trench portion.

In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the groove portion, and the contact region 15 is provided in a region sandwiched by the emitter region 12.

The emitter region 12 is not provided in the mesa portion 61 of the diode portion 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. On the upper surface of the mesa portion 61, a contact region 15 is provided in a region sandwiched by the base regions 14-e so as to be in contact with each of the base regions 14-e. A base region 14 may be provided on the upper surface of the mesa portion 61 in a region sandwiched by the contact region 15. The base region 14 may be disposed over the entire region sandwiched by the contact regions 15.

In the transistor portion 70, a buffer region may be provided in a region in contact with the diode portion 80. The mesa portion of the buffer is a dummy mesa portion having the same structure as the mesa portion 61 of the diode portion 80. However, the collector region 22 is provided on the lower surface of the dummy mesa portion of the buffer region. By providing the buffer region, the cathode region 82 and the gate mesa portion can be arranged apart from each other, and the flow of carriers between the gate mesa portion and the cathode region 82 can be suppressed.

The mesa portion of the buffer region may have a contact region 15 on the upper surface of the semiconductor substrate 10 instead of at least a part of the base region 14 of the diode portion 80. The area of the contact region 15 in the upper surface of the mesa portion of the buffer region may be larger than the area of the contact region 15 in the upper surface of one mesa portion 60. This makes it easy to extract carriers such as holes to the emitter electrode 52 side at the time of turning off the transistor portion 70.

Contact holes 54 are provided above the mesa portions. The contact hole 54 is disposed in a region sandwiched by the base regions 14-e. The contact hole 54 in this example is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of the mesa portion 60.

In the diode portion 80, an N + -type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P + -type collector region 22 may be provided on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not provided. In fig. 6, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

Fig. 7 is a view showing an example of a section b-b in fig. 6. The b-b cross section is the XZ plane through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has, in this cross section: semiconductor substrate 10, interlayer insulating film 38, emitter electrode 52, and collector electrode 24. The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass to which an impurity such as boron or phosphorus is added, a thermally oxidized film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described in fig. 6.

The emitter electrode 52 is disposed above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, a direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction.

The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

In mesa portion 60 of transistor portion 70, N + -type emitter region 12 and P-type base region 14 are provided in this order from the upper surface 21 side of semiconductor substrate 10. A drift region 18 is provided below the base region 14. The N + -type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

The emitter region 12 is disposed between the upper surface 21 of the semiconductor substrate 10 and the drift region 18. The emitter region 12 is exposed at the upper surface 21 of the semiconductor substrate 10, and is disposed in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

Base region 14 is disposed between emitter region 12 and drift region 18. The base region 14 of this example is arranged in contact with the emitter region 12. The base region 14 may be in contact with the groove portions on both sides of the mesa portion 60.

The accumulation region 16 is disposed below the base region 14. The accumulation region 16 has a higher doping concentration than the drift region 18. By providing the accumulation region 16 with a high concentration between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced, and the on voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

The P-type base region 14 is provided on the mesa portion 61 of the diode portion 80 so as to be in contact with the upper surface 21 of the semiconductor substrate 10. Base region 14 of diode portion 80 functions as an anode region of diode portion 80. A drift region 18 is provided below the base region 14. In the mesa portion 61, the accumulation region 16 may be provided below the base region 14.

In each of the transistor portion 70 and the diode portion 80, an N + -type buffer region 20 may be provided below the drift region 18. The buffer region 20 has a higher doping concentration than the drift region 18. The buffer region 20 can function as a field stop layer for preventing a depletion layer spreading from the lower end of the base region 14 from reaching the P + -type collector region 22 and the N + -type cathode region 82. The buffer 20 may have a plurality of peaks or a single peak in the doping concentration profile in the depth direction.

In the transistor portion 70, a P + -type collector region 22 is provided below the buffer region 20. In the diode portion 80, an N + -type cathode region 82 is provided below the buffer region 20. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24.

One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions to reach the drift region 18. The trench portion penetrating doped region is not limited to a structure manufactured in the order of forming the doped region and then forming the trench portion. A structure in which the doped regions are formed between the trench portions after the trench portions are formed is also included in the structure in which the trench portions penetrate the doped regions.

As described above, the gate trench portion 40 and the dummy trench portion 30 are provided in the transistor portion 70. The diode portion 80 is provided with the dummy trench portion 30 and is not provided with the gate trench portion 40.

In this example, the boundary between the transistor portion 70 and the diode portion 80 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22. In the example of fig. 7, dummy trench portions 30 are disposed at the ends of transistor portion 70 in the X-axis direction.

The gate groove portion 40 includes a gate groove provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding a semiconductor of an inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position inside the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate groove portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed of an inversion layer of electrons is formed in a surface layer of an interface of the base region 14 in contact with the gate groove portion 40.

Although the semiconductor device 100 of the present example has a trench-type gate structure, the semiconductor device 100 of another example may have a planar-type gate structure. That is, the gate conductive portion 44 may be disposed above the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 may be disposed between the gate conductive portion 44 and the upper surface 21 of the semiconductor substrate 10.

The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portions 34 may be formed of the same material as the gate conductive portions 44. The dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portions 34 may have the same length in the depth direction as the gate conductive portions 44.

In the present example, the gate groove portion 40 and the dummy groove portion 30 are covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) so as to be convex downward.

In the transistor portion 70, the oxygen concentration distribution in the depth direction (K-K) of the semiconductor substrate 10 is the same as the oxygen concentration distribution shown in fig. 2 or 3. In the diode portion 80, the oxygen concentration distribution in the depth direction (K-K) of the semiconductor substrate 10 is the same as the oxygen concentration distribution shown in fig. 2 or 3. Thus, transistor portion 70 and diode portion 80 can be formed using semiconductor substrate 10 in which the oxygen concentration is accurately controlled. Therefore, variations in characteristics of the semiconductor device 100 can be reduced.

The semiconductor device 100 in the example of fig. 5 to 7 includes both the transistor portion 70 and the diode portion 80 on one semiconductor substrate 10. In another example, the semiconductor device 100 may include the transistor portion 70 and not include the diode portion 80. In this case, the structure of the transistor portion 70 is the same as that of the transistor portion 70 shown in fig. 6 and 7. The semiconductor device 100 may include the diode portion 80 and not include the transistor portion 70. In this case, the structure of the diode section 80 is the same as the diode section 80 shown in fig. 6 and 7.

Fig. 8 is a view showing another example of the section b-b in fig. 6. The semiconductor device 100 of this example has an upper surface side lifetime control region 92 in addition to the configuration of the semiconductor device 100 described with reference to fig. 7. The upper-surface-side lifetime controlled region 92 is a region that is provided on the upper surface 21 side of the semiconductor substrate 10 and reduces the lifetime of carriers. The upper-surface-side lifetime controlled region 92 contains crystal defects such as VO defects. The carriers of the semiconductor substrate 10 decrease the lifetime of the carriers by recombining with the crystal defects. In fig. 8, the peak position of the density of crystal defects in the depth direction is shown by crosses. The upper-surface-side lifetime controlled region 92 is a region including a peak position of the density of crystal defects. The crystal defects can be formed by irradiating impurities such as helium ions or hydrogen ions from the upper surface 21 or the lower surface 23 side of the semiconductor substrate 10. The peak position of the density of the crystal defect corresponds to the concentration peak position of the impurity irradiated for forming the crystal defect.

Upper surface side lifetime control region 92 is provided in diode portion 80. The upper surface side lifetime control region 92 may be provided in the X axis direction to the entire diode portion 80. By providing the upper surface side lifetime control region 92 in the diode portion 80, the reverse recovery time in the diode portion 80 can be reduced, and the reverse recovery loss can be reduced.

The upper-surface-side lifetime control region 92 may also be provided in the transistor portion 70. The upper surface side lifetime control region 92 may be continuously provided in the X-axis direction to the diode portion 80 and the portion of the transistor portion 70 that is in contact with the diode portion 80. By providing upper surface side lifetime control region 92 also in a portion of transistor portion 70 that is in contact with diode portion 80, it is possible to suppress carriers from flowing from the upper surface side of transistor portion 70 to cathode region 82.

Fig. 9 shows an example of the oxygen concentration distribution and the crystal defect density distribution in the J-J section of fig. 8. The J-J cross section is a YZ cross section through the upper surface side lifetime control region 92. The region in diode portion 80 where upper surface side lifetime control region 92 is provided and the region in transistor portion 70 where upper surface side lifetime control region 92 is provided may both have the distributions shown in fig. 9.

The oxygen concentration distribution shown in fig. 9 is the same as the oxygen concentration distribution shown in fig. 2 or 3. The vertical axis of the oxygen concentration distribution in fig. 9 is an axis showing each oxygen concentration in percentage when the oxygen concentration Omax of the concentration peak 144 is set to 100%. In addition, the oxygen concentration distribution in fig. 9 is enlarged in the vicinity of the concentration peak 144. The vertical axis of the crystal defect density distribution shown in fig. 9 is a logarithmic axis, and the horizontal axis is a linear axis showing the position in the depth direction.

The crystal defect density distribution in the depth direction of the semiconductor substrate 10 has an upper surface side density peak 154 in a region on the upper surface 21 side of the semiconductor substrate 10 (i.e., a region from the central position Dc of the semiconductor substrate 10 to the upper surface 21). The crystal defect density distribution has an upper surface side slope 156 from upper surface side density peak 154 toward upper surface 21, and a lower surface side slope 155 from upper surface side density peak 154 toward lower surface 23. The crystal defects of this example are formed by implanting helium plasma from the upper surface 21 side of the semiconductor substrate 10. In this case, since crystal defects are also formed in the region where the helium plasma passes, the inclination of the upper surface-side slope 156 becomes gentler than the inclination of the lower surface-side slope 155. The depth position of the upper surface side density peak 154 substantially coincides with the peak position of the concentration distribution of helium plasma irradiated for forming crystal defects. In another example, the crystal defects may be formed by implanting helium plasma from the lower surface 23 side of the semiconductor substrate 10. In this case, the inclination of the lower surface-side slope 155 becomes gentler than the inclination of the upper surface-side slope 156.

In the oxygen concentration distribution, a depth range in which the oxygen concentration is 50% or more of the oxygen concentration Omax of the concentration peak 144 is R1, and a depth range in which the oxygen concentration is 80% or more of the oxygen concentration Omax is R2. Upper surface side density peak 154 is preferably arranged within depth range R1.

The difference between the oxygen concentration and the oxygen concentration Omax in the depth range R1 is small, and the oxygen concentration can be accurately controlled by the annealing temperature. Therefore, by setting the range of helium plasma for forming crystal defects in the depth range R1, helium plasma can be implanted into a region where the variation in oxygen concentration is small. Since the density of the formed crystal defects varies depending on the oxygen concentration, the variation in the density peak value Vmax of the upper surface side density peak 154 can be reduced.

Upper surface side density peak 154 may be arranged in depth range R2. This can further reduce the variation in the density peak Vmax.

The concentration peak 144 in the oxygen concentration distribution may be disposed between the upper surface side density peak 154 and the upper surface 21 of the semiconductor substrate 10. That is, the upper surface side density peak 154 may be disposed at a position overlapping the lower surface side slope 145 in the oxygen concentration distribution. Thereby, in the oxygen concentration distribution, the upper surface side density peak 154 can be arranged in a region having a small inclination. Therefore, even if the position of the upper-side density peak 154 in the depth direction is deviated, the deviation of the oxygen concentration due to the positional deviation can be reduced, and the deviation of the density peak Vmax can be reduced. In this case, the upper surface side density peak 154 is also preferably arranged within the range R1 or R2.

The depth range R1 may have a length in the depth direction of 10 μm or more. By setting the depth range R1 long, the upper surface side density peak 154 can be easily set in the depth range R1, and the variation in the density peak value Vmax can be reduced. The depth range R2 may have a length in the depth direction of 10 μm or more. This can further reduce the variation in the density peak Vmax. The length of the depth range R1 or R2 may be 15 μm or more, or 20 μm or more.

The length of the depth range R1 or R2 can be controlled by annealing conditions or the like. By further extending, for example, the annealing time, oxygen can be distributed to a deeper position of the semiconductor substrate 10 at a concentration close to the solid solubility limit. Therefore, the depth range R1 or R2 can be lengthened. The annealing time may be 1 hour or more, 5 hours or more, or 10 hours or more.

The distance L1 between the concentration peak 144 in the oxygen concentration distribution and the upper surface 21 of the semiconductor substrate 10 may be 5 μm or more and 20 μm or less. By reducing the distance L1 to some extent, the length of the region in which the change in the oxygen concentration distribution is relatively steep can be reduced. The distance L1 may be 10 μm or less. The distance L1 may be smaller than the length of the dummy groove portion 30 in the depth direction shown in fig. 5 and the like. On the other hand, the distance between upper surface-side density peak 154 and upper surface 21 may be larger than the length of dummy groove portion 30 in the depth direction. Thereby, the upper surface side density peak 154 is arranged at a position overlapping the lower surface side slope 145 of the oxygen concentration distribution.

The semiconductor device 100 shown in fig. 8 has an upper surface side lifetime control region 92 on the upper surface 21 side of the semiconductor substrate 10, and does not have a lifetime control region on the lower surface 23 side. That is, the crystal defect density distribution, lifetime distribution, and the like in the depth direction do not have extreme values such as peaks or valleys on the lower surface 23 side of the semiconductor substrate 10.

On the lower surface 23 side of the semiconductor substrate 10, the influence of the initial oxygen concentration becomes stronger than on the upper surface 21 side, and the variation in oxygen concentration tends to become larger. By not providing the lifetime control region on the lower surface 23 side, variations in characteristics of the semiconductor device 100 can be reduced.

Fig. 10 is a graph showing the relationship between the oxygen concentration and the forward voltage Vf in the case where the semiconductor substrate having a substantially uniform oxygen concentration distribution in the depth direction is formed with the upper surface side lifetime controlled region 92 as shown in fig. 8. As shown in fig. 10, the crystal defect density fluctuates and the forward voltage Vf also fluctuates according to the change in the oxygen concentration of the semiconductor substrate.

Therefore, in the case of manufacturing a semiconductor device using a semiconductor substrate having no oxygen concentration distribution as shown in fig. 1 to 9, the oxygen concentration of the prepared semiconductor substrate may be measured in advance, and the substrate may be graded according to the oxygen concentration. Then, a grade of semiconductor substrate corresponding to the use of the semiconductor device is used. The oxygen concentration of a semiconductor substrate manufactured by the MCZ method, the FZ method, or the like is likely to vary, and it is difficult to stably prepare a semiconductor substrate having a predetermined oxygen concentration.

In contrast, as in the examples shown in fig. 1 to 9, by annealing the semiconductor substrate 10 under the condition that the solid solubility limit is higher than the initial concentration of the semiconductor substrate 10, the oxygen concentration of the semiconductor substrate 10 can be set to a predetermined concentration, and the variation in the oxygen concentration between the substrates can be reduced. Therefore, the performance variation of the semiconductor device 100 can be suppressed, and the preparation cost of the semiconductor substrate can be reduced.

Fig. 11 is a graph comparing characteristics of the semiconductor device 100 manufactured using two semiconductor substrates 10 having different initial concentrations of oxygen. The initial oxygen concentration of the semiconductor substrate 10 of sample 1 was 4 × 10¹⁶/cm³The initial oxygen concentration of the semiconductor substrate 10 of sample 2 was 4X 10¹⁷/cm³. The structure of the semiconductor device 100 is the same as that of the example of fig. 8. The semiconductor substrate 10 of sample 1 was a substrate manufactured by the FZ method, and the semiconductor substrate 10 of sample 2 was a substrate manufactured by the MCZ method.

At a solid solubility limit of 4X 10^17/cm³The semiconductor substrates 10 are annealed under conditions 1.5 times or more. The annealing conditions were the same for sample 1 and sample 2. The relationship between the collector-emitter voltage (Vce) and the collector current (Ic) was measured in the manufactured semiconductor devices 100 of sample 1 and sample 2 at 25 ℃ and 175 ℃. The properties of sample 1 and sample 2 were approximately the same at either temperature.

Thus, according to the semiconductor device 100 described with reference to fig. 1 to 9, variations in characteristics due to variations in initial oxygen concentration can be reduced. Even when the semiconductor substrate 10 manufactured by a different manufacturing method such as the MCZ method and the FZ method is used, the semiconductor device 100 having substantially the same characteristics can be manufactured.

Fig. 12 is a diagram showing another example of the semiconductor device 100. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in fig. 8 in that it includes a lower surface side lifetime control region 93. The structure other than the lower surface side lifetime control region 93 is the same as the example shown in fig. 8.

The lower-surface-side lifetime controlled region 93 is disposed on the lower surface 23 side of the semiconductor substrate 10 (i.e., a region from the central position Dc in the depth direction of the semiconductor substrate 10 to the lower surface 23). The lower surface side lifetime control region 93 of this example may be provided at a position overlapping the buffer region 20. Further, the lower surface side lifetime control region 93 may be provided in a wider range in the X-axis direction than the upper surface side lifetime control region 92. The lower surface side lifetime control region 93 of this example is provided over the diode portion 80 and the transistor portion 70 in the X axis direction.

The structure and formation method of the lower surface side lifetime controlled region 93 are the same as those of the upper surface side lifetime controlled region 92. However, the lower surface side lifetime controlled region 93 may be formed by irradiating helium plasma from the lower surface 23 side of the semiconductor substrate 10.

By providing the lower surface side lifetime control region 93, the lifetime of carriers in the semiconductor substrate 10 can be controlled more accurately. The lower surface-side lifetime controlled region 93 is preferably provided at a position overlapping the lower surface-side slope 145 in the oxygen concentration distribution. That is, the lower surface side lifetime controlled region 93 is preferably not provided in the flat region 147 shown in fig. 3. This can reduce the influence of variations in the initial oxygen concentration. However, the lower surface side lifetime control region 93 may be provided in the flat region 147.

The present invention has been described above with reference to the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or modifications may be made in the above embodiments. The present invention may be embodied in other forms such as modifications and improvements, which are apparent from the claims.

The claims (modification according to treaty clause 19)

1. A semiconductor device comprising a semiconductor substrate containing oxygen,

the oxygen concentration distribution in the depth direction of the semiconductor substrate has a high oxygen concentration portion having an oxygen concentration higher than that of the lower surface of the semiconductor substrate on a side closer to the upper surface with respect to the center in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1,

the high oxygen concentration portion has a concentration peak in the oxygen concentration distribution.

3. The semiconductor device according to claim 2,

the oxygen concentration decreases from the concentration peak toward the lower surface of the semiconductor substrate until decreasing to the same concentration as the oxygen concentration of the lower surface of the semiconductor substrate.

4. The semiconductor device according to claim 2 or 3,

a density distribution of crystal defects in a depth direction of the semiconductor substrate has an upper surface side density peak on an upper surface side of the semiconductor substrate,

the upper surface side density peak is disposed in a depth range in which the oxygen concentration is 50% or more of a peak value of the concentration peak.

5. The semiconductor device according to claim 4,

the upper surface side density peak is disposed in a depth range in which the oxygen concentration is 80% or more of a peak value of the concentration peak.

6. The semiconductor device according to claim 4,

in the oxygen concentration distribution, a depth range in which the oxygen concentration is 50% or more of a peak value of the concentration peak is 10 μm or more.

7. The semiconductor device according to any one of claims 4 to 6,

the concentration peak is disposed between the upper surface side density peak and the upper surface of the semiconductor substrate.

8. The semiconductor device according to any one of claims 2 to 7,

the peak value of the concentration peak is 1.5 times or more as large as the minimum value of the oxygen concentration in the oxygen concentration distribution.

9. The semiconductor device according to claim 8,

the peak value of the concentration peak is 5 times or more as large as the minimum value of the oxygen concentration in the oxygen concentration distribution.

10. The semiconductor device according to any one of claims 4 to 9,

the distance between the concentration peak in the oxygen concentration distribution and the upper surface of the semiconductor substrate is 5 [ mu ] m or more and 20 [ mu ] m or less.

11. The semiconductor device according to any one of claims 1 to 10,

the semiconductor device further includes:

a gate conductive part disposed on an upper surface of the semiconductor substrate; and

a gate insulating film that insulates the gate conductive portion from the semiconductor substrate.

12. The semiconductor device according to any one of claims 1 to 11,

the semiconductor device further includes:

a cathode region of a first conductivity type provided in contact with a lower surface of the semiconductor substrate; and

an anode region of a second conductivity type disposed in contact with an upper surface of the semiconductor substrate.

13. A method for manufacturing a semiconductor device having a semiconductor substrate containing oxygen,

the manufacturing method comprises:

an annealing step of annealing an initial substrate so that a solid solubility limit concentration of oxygen for the initial substrate is higher than a current oxygen concentration of the initial substrate; and

and a thinning step of thinning the initial substrate from a lower surface side of the initial substrate to form the semiconductor substrate.

14. The manufacturing method according to claim 13, further comprising,

a preparation step of preparing an MCZ substrate as the initial substrate.

15. The manufacturing method according to claim 13, further comprising,

a preparation step of preparing an FZ substrate as the initial substrate.

16. The semiconductor device according to any one of claims 1 to 10,

an active portion and an edge termination structure portion surrounding the active portion are provided on the semiconductor substrate,

the active portion is provided with a transistor portion and a diode portion.

17. The semiconductor device according to claim 16,

the transistor portions and the diode portions are alternately arranged in an array direction.

18. The semiconductor device according to claim 16 or 17,

the transistor portion and the diode portion have a base region of a second conductivity type provided in contact with an upper surface of the semiconductor substrate,

the transistor portion has a collector region of a second conductivity type provided in contact with a lower surface of the semiconductor substrate,

the diode portion has a cathode region of a first conductivity type provided in contact with a lower surface of the semiconductor substrate,

the base region provided in the diode portion functions as an anode region.

19. The semiconductor device according to any one of claims 16 to 18,

a gate trench portion is provided in the transistor portion,

dummy trench portions are provided in the transistor portion and the diode portion,

the gate trench portion includes:

a gate trench disposed on an upper surface of the semiconductor substrate;

a gate insulating film covering an inner wall of the gate trench; and

a gate conductive portion provided inside the gate trench at a position further inside than the gate insulating film,

the dummy groove portion includes:

a dummy trench provided on an upper surface of the semiconductor substrate;

a dummy insulating film covering an inner wall of the dummy trench; and

and a dummy conductive portion provided inside the dummy trench at a position inside the dummy insulating film.

20. The semiconductor device according to any one of claims 16 to 18,

the diode portion is provided with an upper surface side lifetime control region.